Module Name: src
Committed By: matt
Date: Sat Jun 19 19:44:58 UTC 2010
Modified Files:
src/sys/arch/arm/arm: bus_space_asm_generic.S cpufunc.c
cpufunc_asm_armv6.S cpufunc_asm_armv7.S
src/sys/arch/arm/arm32: cpu.c locore.S
src/sys/arch/arm/conf: files.arm
src/sys/arch/arm/include: armreg.h cpuconf.h cpufunc.h
src/sys/arch/arm/omap: omap2_mputmr.c
src/sys/arch/evbarm/conf: BEAGLEBOARD TISDP2420 std.beagle std.igepv2
Added Files:
src/sys/arch/arm/arm32: cortex_pmc.c
Log Message:
Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.
Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/arm/bus_space_asm_generic.S
cvs rdiff -u -r1.95 -r1.96 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/arm/cpufunc_asm_armv6.S
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/arm/cpufunc_asm_armv7.S
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/arm32/cortex_pmc.c
cvs rdiff -u -r1.73 -r1.74 src/sys/arch/arm/arm32/cpu.c
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/arm32/locore.S
cvs rdiff -u -r1.98 -r1.99 src/sys/arch/arm/conf/files.arm
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/arm/include/armreg.h
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/include/cpuconf.h
cvs rdiff -u -r1.50 -r1.51 src/sys/arch/arm/include/cpufunc.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/omap/omap2_mputmr.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbarm/conf/BEAGLEBOARD
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/evbarm/conf/TISDP2420
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbarm/conf/std.beagle
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbarm/conf/std.igepv2
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/bus_space_asm_generic.S
diff -u src/sys/arch/arm/arm/bus_space_asm_generic.S:1.5 src/sys/arch/arm/arm/bus_space_asm_generic.S:1.6
--- src/sys/arch/arm/arm/bus_space_asm_generic.S:1.5 Sun Dec 11 12:16:41 2005
+++ src/sys/arch/arm/arm/bus_space_asm_generic.S Sat Jun 19 19:44:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space_asm_generic.S,v 1.5 2005/12/11 12:16:41 christos Exp $ */
+/* $NetBSD: bus_space_asm_generic.S,v 1.6 2010/06/19 19:44:57 matt Exp $ */
/*
* Copyright (c) 1997 Causality Limited.
@@ -49,7 +49,7 @@
ldrb r0, [r1, r2]
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_r_2)
ldrh r0, [r1, r2]
mov pc, lr
@@ -67,7 +67,7 @@
strb r3, [r1, r2]
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_w_2)
strh r3, [r1, r2]
mov pc, lr
@@ -95,7 +95,7 @@
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_rm_2)
add r0, r1, r2
mov r1, r3
@@ -143,7 +143,7 @@
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_wm_2)
add r0, r1, r2
mov r1, r3
@@ -191,7 +191,7 @@
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_rr_2)
add r0, r1, r2
mov r1, r3
@@ -239,7 +239,7 @@
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_wr_2)
add r0, r1, r2
mov r1, r3
@@ -286,7 +286,7 @@
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_sr_2)
add r0, r1, r2
mov r1, r3
@@ -318,7 +318,7 @@
* copy region
*/
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_c_2)
add r0, r1, r2
ldr r2, [sp, #0]
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.95 src/sys/arch/arm/arm/cpufunc.c:1.96
--- src/sys/arch/arm/arm/cpufunc.c:1.95 Wed Jun 16 22:06:53 2010
+++ src/sys/arch/arm/arm/cpufunc.c Sat Jun 19 19:44:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.95 2010/06/16 22:06:53 jmcneill Exp $ */
+/* $NetBSD: cpufunc.c,v 1.96 2010/06/19 19:44:57 matt Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.95 2010/06/16 22:06:53 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.96 2010/06/19 19:44:57 matt Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -1081,8 +1081,8 @@
#endif
/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */
-#if defined(CPU_CORTEXA8)
-struct cpu_functions cortexa8_cpufuncs = {
+#if defined(CPU_CORTEX)
+struct cpu_functions cortex_cpufuncs = {
/* CPU functions */
.cf_id = cpufunc_id,
@@ -1139,7 +1139,7 @@
.cf_setup = armv7_setup
};
-#endif /* CPU_CORTEXA8 */
+#endif /* CPU_CORTEX */
/*
@@ -1155,7 +1155,7 @@
defined(CPU_FA526) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
- defined(CPU_CORTEXA8)
+ defined(CPU_CORTEX)
static void get_cachetype_cp15(void);
/* Additional cache information local to this file. Log2 of some of the
@@ -1170,10 +1170,10 @@
{
u_int csid;
-#if (CPU_CORTEXA8) > 0
+#if (CPU_CORTEX) > 0
+ __asm volatile(".arch\tarmv7a");
__asm volatile("mcr p15, 2, %0, c0, c0, 0" :: "r" (cssr));
- /* GAS does not have the ISB instruction ATM */
- __asm volatile(".word 0xF57FF06F;"); /* sync to the new cssr */
+ __asm volatile("isb"); /* sync to the new cssr */
#else
__asm volatile("mcr p15, 1, %0, c0, c0, 2" :: "r" (cssr));
#endif
@@ -1693,11 +1693,12 @@
return 0;
}
#endif /* CPU_XSCALE_IXP425 */
-#if defined(CPU_CORTEXA8)
+#if defined(CPU_CORTEX)
if (cputype == CPU_ID_CORTEXA8R1 ||
cputype == CPU_ID_CORTEXA8R2 ||
- cputype == CPU_ID_CORTEXA8R3) {
- cpufuncs = cortexa8_cpufuncs;
+ cputype == CPU_ID_CORTEXA8R3 ||
+ cputype == CPU_ID_CORTEXA9R1) {
+ cpufuncs = cortex_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
cpu_do_powersave = 1; /* Enable powersave */
get_cachetype_cp15();
@@ -1707,7 +1708,7 @@
return 0;
}
-#endif /* CPU_CORTEXA8 */
+#endif /* CPU_CORTEX */
/*
* Bzzzz. And the answer was ...
*/
@@ -2094,7 +2095,7 @@
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARM1136) || \
- defined(CPU_FA526) || defined(CPU_CORTEXA8)
+ defined(CPU_FA526) || defined(CPU_CORTEX)
#define IGN 0
#define OR 1
@@ -2546,7 +2547,7 @@
}
#endif /* CPU_ARM11 */
-#if defined(CPU_CORTEXA8)
+#if defined(CPU_CORTEX)
struct cpu_option armv7_options[] = {
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
@@ -2629,18 +2630,20 @@
for (way = ways; way >= 0; way--) {
/* Clean by set/way */
- u_int sw = (way << wayshift) | (nsets << setshift) |
- (level << 1);
+ const u_int sw = (way << wayshift)
+ | (nsets << setshift)
+ | (level << 1);
- __asm volatile("mcr\tp15, 0, %0, c7, c10, 2" :: "r"(sw));
+ __asm volatile("mcr\tp15, 0, %0, c7, c10, 2"
+ :: "r"(sw));
}
}
}
- __asm volatile("mcr\tp15, 0, r0, c7, c10, 4"); /* DSB */
- __asm volatile(".word 0xF57FF06F;"); /* ISB */
+ __asm volatile("dsb");
+ __asm volatile("isb");
}
-#endif /* CPU_CORTEXA8 */
+#endif /* CPU_CORTEX */
@@ -2965,7 +2968,7 @@
#endif /* CPU_IXP12X0 */
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || defined(CPU_CORTEXA8)
+ defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || defined(CPU_CORTEX)
struct cpu_option xscale_options[] = {
#ifdef COMPAT_12
{ "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
Index: src/sys/arch/arm/arm/cpufunc_asm_armv6.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_armv6.S:1.2 src/sys/arch/arm/arm/cpufunc_asm_armv6.S:1.3
--- src/sys/arch/arm/arm/cpufunc_asm_armv6.S:1.2 Sun Apr 27 18:58:43 2008
+++ src/sys/arch/arm/arm/cpufunc_asm_armv6.S Sat Jun 19 19:44:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_armv6.S,v 1.2 2008/04/27 18:58:43 matt Exp $ */
+/* $NetBSD: cpufunc_asm_armv6.S,v 1.3 2010/06/19 19:44:57 matt Exp $ */
/*
* Copyright (c) 2002, 2005 ARM Limited
@@ -38,6 +38,8 @@
#include <machine/cpu.h>
#include <machine/asm.h>
+ .arch armv6
+
/*
* Functions to set the MMU Translation Table Base register
*
Index: src/sys/arch/arm/arm/cpufunc_asm_armv7.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.1 src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.2
--- src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.1 Wed Jun 16 22:06:53 2010
+++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S Sat Jun 19 19:44:57 2010
@@ -31,128 +31,137 @@
#include <machine/cpu.h>
#include <machine/asm.h>
-#define ISB .word 0xF57FF06F;
-#define DMB .word 0xF57FF05F;
-#define DSB .word 0xF57FF04F;
-#define WFI .word 0xC320F003;
-
-#define DCACHE_SIZE 0x00008000
-
#define entrysize #32
+ .arch armv7a
+
ENTRY(armv7_cpu_sleep)
- tst r0, #0x00000000 @shouldn't sleep 0
- WFI
- RET
+ tst r0, #0x00000000 @shouldn't sleep 0
+ wfi
+ RET
+END(armv7_cpu_sleep)
ENTRY(armv7_wait)
- mrc p15, 0, r0, c2, c0, 0 /* arbitrary read of CP15 */
- add r0, r0, #0 /* a stall */
- RET
+ mrc p15, 0, r0, c2, c0, 0 @arbitrary read of CP15
+ add r0, r0, #0 @a stall
+ RET
+END(armv7_wait)
ENTRY(armv7_context_switch)
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
- mcr p15, 0, r0, c8, c7, 0 /* flush the I+D */
- RET
+ mcr p15, 0, r0, c7, c10, 4 @drain the write buffer
+ mcr p15, 0, r0, c2, c0, 0 @set the new TTB
+ mcr p15, 0, r0, c8, c7, 0 @flush the I+D
+ RET
+END(armv7_context_switch)
ENTRY(armv7_tlb_flushID_SE)
- mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
- RET
+ mcr p15, 0, r0, c8, c7, 1 @flush I+D tlb single entry
+ mcr p15, 0, r0, c7, c10, 4 @drain write buffer
+ RET
+END(armv7_tlb_flushID_SE)
ENTRY(armv7_setttb)
/* Does this even exist on armv7? */
#ifdef PMAP_CACHE_VIVT
- stmdb sp!, {r0, lr}
- bl _C_LABEL(armv7_idcache_wbinv_all) /* Clean the D cache */
- ldmia sp!, {r0, lr}
+ stmdb sp!, {r0, lr}
+ bl _C_LABEL(armv7_idcache_wbinv_all) @clean the D cache
+ ldmia sp!, {r0, lr}
#endif
- mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
+ mcr p15, 0, r0, c2, c0, 0 @load new TTB
+ mcr p15, 0, r0, c8, c7, 0 @invalidate I+D TLBs
+ mcr p15, 0, r0, c7, c10, 4 @drain the write buffer
- RET
+ RET
+END(armv7_setttb)
/* Cache operations. */
/* LINTSTUB: void armv7_icache_sync_range(vaddr_t, vsize_t); */
ENTRY_NP(armv7_icache_sync_range)
1:
- mcr p15, 0, r0, c7, c5, 1 @invalidate the I-Cache line
- mcr p15, 0, r0, c7, c10, 1 @wb the D-Cache line
- add r0, r0, entrysize
- subs r1, r1, entrysize
- bhi 1b
-
- mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB
- RET
+ mcr p15, 0, r0, c7, c5, 1 @invalidate the I-Cache line
+ mcr p15, 0, r0, c7, c10, 1 @wb the D-Cache line
+ add r0, r0, entrysize
+ subs r1, r1, entrysize
+ bhi 1b
+
+ mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB
+ RET
+END(armv7_icache_sync_range)
/* LINTSTUB: void armv7_icache_sync_all(void); */
ENTRY_NP(armv7_icache_sync_all)
- /*
- * We assume that the code here can never be out of sync with the
- * dcache, so that we can safely flush the Icache and fall through
- * into the Dcache cleaning code.
- */
- stmdb sp!, {r0, lr}
- bl _C_LABEL(armv7_idcache_wbinv_all) /* Clean the D cache */
- ldmia sp!, {r0, lr}
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
- RET
+ /*
+ * We assume that the code here can never be out of sync with the
+ * dcache, so that we can safely flush the Icache and fall through
+ * into the Dcache cleaning code.
+ */
+ stmdb sp!, {r0, lr}
+ bl _C_LABEL(armv7_idcache_wbinv_all) @clean the D cache
+ ldmia sp!, {r0, lr}
+ mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB
+ RET
+END(armv7_icache_sync_all)
ENTRY(armv7_dcache_wb_range)
1:
- mcr p15, 0, r0, c7, c10, 1 @wb the D-Cache
- add r0, r0, entrysize
- subs r1, r1, entrysize
- bhi 1b
- mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB
- RET
+ mcr p15, 0, r0, c7, c10, 1 @wb the D-Cache
+ add r0, r0, entrysize
+ subs r1, r1, entrysize
+ bhi 1b
+ mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB
+ RET
+END(armv7_dcache_wb_range)
/* LINTSTUB: void armv7_dcache_wbinv_range(vaddr_t, vsize_t); */
ENTRY(armv7_dcache_wbinv_range)
1:
- mcr p15, 0, r0, c7, c14, 1 @wb and inv the D-Cache line
- add r0, r0, entrysize
- subs r1, r1, entrysize
- bhi 1b
- mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB
- RET
+ mcr p15, 0, r0, c7, c14, 1 @wb and inv the D-Cache line
+ add r0, r0, entrysize
+ subs r1, r1, entrysize
+ bhi 1b
+ mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB
+ RET
+END(armv7_dcache_wbinv_range)
/* * LINTSTUB: void armv7_dcache_inv_range(vaddr_t, vsize_t); */
ENTRY(armv7_dcache_inv_range)
1:
- mcr p15, 0, r0, c7, c6, 1 @invalidate the D-Cache line
- add r0, r0, entrysize
- subs r1, r1, entrysize
- bhi 1b
- mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB
- RET
+ mcr p15, 0, r0, c7, c6, 1 @invalidate the D-Cache line
+ add r0, r0, entrysize
+ subs r1, r1, entrysize
+ bhi 1b
+
+ mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB
+ RET
+END(armv7_dcache_inv_range)
ENTRY(armv7_idcache_wbinv_range)
1:
- mcr p15, 0, r0, c7, c5, 1 @invalidate the I-Cache line
- mcr p15, 0, r0, c7, c14, 1 @wb and inv the D-Cache line
- add r0, r0, entrysize
- subs r1, r1, entrysize
- bhi 1b
- mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB
- RET
+ mcr p15, 0, r0, c7, c5, 1 @invalidate the I-Cache line
+ mcr p15, 0, r0, c7, c14, 1 @wb and inv the D-Cache line
+ add r0, r0, entrysize
+ subs r1, r1, entrysize
+ bhi 1b
+
+ mcr p15, 0, r0, c7, c10, 4 @drain the write buffer, BSB
+ RET
+END(armv7_idcache_wbinv_range)
ENTRY_NP(armv7_idcache_wbinv_all)
- /*
- * We assume that the code here can never be out of sync with the
- * dcache, so that we can safely flush the Icache and fall through
- * into the Dcache purging code.
- */
- DMB
- mcr p15, 0, r0, c7, c5, 0
- b _C_LABEL(armv7_dcache_wbinv_all)
+ /*
+ * We assume that the code here can never be out of sync with the
+ * dcache, so that we can safely flush the Icache and fall through
+ * into the Dcache purging code.
+ */
+ dmb
+ mcr p15, 0, r0, c7, c5, 0
+ b _C_LABEL(armv7_dcache_wbinv_all)
+END(armv7_idcache_wbinv_all)
/*
* armv7_dcache_wbinv_all is in cpufunc.c. It's really too long to
Index: src/sys/arch/arm/arm32/cpu.c
diff -u src/sys/arch/arm/arm32/cpu.c:1.73 src/sys/arch/arm/arm32/cpu.c:1.74
--- src/sys/arch/arm/arm32/cpu.c:1.73 Wed Jun 16 22:06:53 2010
+++ src/sys/arch/arm/arm32/cpu.c Sat Jun 19 19:44:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.73 2010/06/16 22:06:53 jmcneill Exp $ */
+/* $NetBSD: cpu.c,v 1.74 2010/06/19 19:44:57 matt Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.73 2010/06/16 22:06:53 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.74 2010/06/19 19:44:57 matt Exp $");
#include <sys/systm.h>
#include <sys/malloc.h>
@@ -184,6 +184,7 @@
CPU_CLASS_XSCALE,
CPU_CLASS_ARM11J,
CPU_CLASS_ARMV4,
+ CPU_CLASS_CORTEX,
};
static const char * const generic_steppings[16] = {
@@ -406,9 +407,14 @@
pN_steppings },
{ CPU_ID_ARM1176JS, CPU_CLASS_ARM11J, "ARM1176J-S r0",
pN_steppings },
- { CPU_ID_CORTEXA8R1, CPU_CLASS_ARM11J, "Cortex-A8 r1",
+
+ { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEX, "Cortex-A8 r1",
+ pN_steppings },
+ { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEX, "Cortex-A8 r2",
+ pN_steppings },
+ { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEX, "Cortex-A8 r3",
pN_steppings },
- { CPU_ID_CORTEXA8R2, CPU_CLASS_ARM11J, "Cortex-A8 r2",
+ { CPU_ID_CORTEXA9R1, CPU_CLASS_CORTEX, "Cortex-A9 r1",
pN_steppings },
{ CPU_ID_CORTEXA8R3, CPU_CLASS_ARM11J, "Cortex-A8 r3",
pN_steppings },
@@ -425,23 +431,24 @@
};
const struct cpu_classtab cpu_classes[] = {
- { "unknown", NULL }, /* CPU_CLASS_NONE */
- { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */
- { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */
- { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */
- { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */
- { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */
- { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */
- { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */
- { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */
- { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */
- { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */
- { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */
- { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */
- { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */
- { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */
- { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */
- { "ARMv4", "CPU_ARMV4" }, /* CPU_CLASS_ARMV4 */
+ [CPU_CLASS_NONE] = { "unknown", NULL },
+ [CPU_CLASS_ARM2] = { "ARM2", "CPU_ARM2" },
+ [CPU_CLASS_ARM2AS] = { "ARM2as", "CPU_ARM250" },
+ [CPU_CLASS_ARM3] = { "ARM3", "CPU_ARM3" },
+ [CPU_CLASS_ARM6] = { "ARM6", "CPU_ARM6" },
+ [CPU_CLASS_ARM7] = { "ARM7", "CPU_ARM7" },
+ [CPU_CLASS_ARM7TDMI] = { "ARM7TDMI", "CPU_ARM7TDMI" },
+ [CPU_CLASS_ARM8] = { "ARM8", "CPU_ARM8" },
+ [CPU_CLASS_ARM9TDMI] = { "ARM9TDMI", NULL },
+ [CPU_CLASS_ARM9ES] = { "ARM9E-S", "CPU_ARM9E" },
+ [CPU_CLASS_ARM9EJS] = { "ARM9EJ-S", "CPU_ARM9E" },
+ [CPU_CLASS_ARM10E] = { "ARM10E", "CPU_ARM10" },
+ [CPU_CLASS_ARM10EJ] = { "ARM10EJ", "CPU_ARM10" },
+ [CPU_CLASS_SA1] = { "SA-1", "CPU_SA110" },
+ [CPU_CLASS_XSCALE] = { "XScale", "CPU_XSCALE_..." },
+ [CPU_CLASS_ARM11J] = { "ARM11J", "CPU_ARM11" },
+ [CPU_CLASS_ARMV4] = { "ARMv4", "CPU_ARMV4" },
+ [CPU_CLASS_CORTEX] = { "ARMv4", "CPU_CORTEX" },
};
/*
@@ -524,6 +531,7 @@
case CPU_CLASS_XSCALE:
case CPU_CLASS_ARM11J:
case CPU_CLASS_ARMV4:
+ case CPU_CLASS_CORTEX:
if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0)
aprint_normal(" DC disabled");
else
@@ -615,6 +623,7 @@
#endif
#if defined(CPU_ARM11)
case CPU_CLASS_ARM11J:
+ case CPU_CLASS_CORTEX:
#endif
#if defined(CPU_FA526)
case CPU_CLASS_ARMV4:
Index: src/sys/arch/arm/arm32/locore.S
diff -u src/sys/arch/arm/arm32/locore.S:1.24 src/sys/arch/arm/arm32/locore.S:1.25
--- src/sys/arch/arm/arm32/locore.S:1.24 Thu Aug 7 04:18:21 2008
+++ src/sys/arch/arm/arm32/locore.S Sat Jun 19 19:44:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.24 2008/08/07 04:18:21 matt Exp $ */
+/* $NetBSD: locore.S,v 1.25 2010/06/19 19:44:57 matt Exp $ */
/*
* Copyright (C) 1994-1997 Mark Brinicombe
@@ -42,7 +42,7 @@
/* What size should this really be ? It is only used by init_arm() */
#define INIT_ARM_STACK_SIZE 2048
- RCSID("$NetBSD: locore.S,v 1.24 2008/08/07 04:18:21 matt Exp $")
+ RCSID("$NetBSD: locore.S,v 1.25 2010/06/19 19:44:57 matt Exp $")
/*
* This is for kvm_mkdb, and should be the address of the beginning
@@ -58,8 +58,13 @@
adr r1, .Lstart
ldmia r1, {r1, r2, sp} /* Set initial stack and */
sub r2, r2, r1 /* get zero init data */
- mov r3, #0
+#ifdef PROCESS_ID_IS_CURCPU
+ ldr r3, .Lcpu_info_store
+ mcr p15, 0, r3, c13, c0, 4
+#endif
+
+ mov r3, #0
.L1:
str r3, [r1], #0x0004 /* Zero the bss */
subs r2, r2, #4
@@ -82,6 +87,11 @@
b _C_LABEL(panic)
/* NOTREACHED */
+#ifdef PROCESS_ID_IS_CURCPU
+.Lcpu_info_store:
+ .word _C_LABEL(cpu_info_store)
+#endif
+
.Lstart:
.word _edata
.word _end
Index: src/sys/arch/arm/conf/files.arm
diff -u src/sys/arch/arm/conf/files.arm:1.98 src/sys/arch/arm/conf/files.arm:1.99
--- src/sys/arch/arm/conf/files.arm:1.98 Wed Jun 16 22:06:53 2010
+++ src/sys/arch/arm/conf/files.arm Sat Jun 19 19:44:57 2010
@@ -1,4 +1,4 @@
-# $NetBSD: files.arm,v 1.98 2010/06/16 22:06:53 jmcneill Exp $
+# $NetBSD: files.arm,v 1.99 2010/06/19 19:44:57 matt Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defflag ARM32
@@ -8,13 +8,14 @@
defflag opt_cputypes.h CPU_ARM6 CPU_ARM7 CPU_ARM7TDMI CPU_ARM8
CPU_ARM9 CPU_ARM9E CPU_ARM10 CPU_ARM11
CPU_SA110 CPU_SA1100 CPU_SA1110 CPU_IXP12X0
- CPU_FA526
+ CPU_FA526 CPU_CORTEX
CPU_XSCALE_80200 CPU_XSCALE_80321
CPU_XSCALE_PXA250 CPU_XSCALE_PXA270
CPU_XSCALE_IXP425
- CPU_CORTEXA8
defflag opt_cputypes.h CPU_ARM1136: CPU_ARM11
defflag opt_cputypes.h CPU_ARM1176: CPU_ARM11
+defflag opt_cputypes.h CPU_CORTEXA8: CPU_CORTEX
+defflag opt_cputypes.h CPU_CORTEXA9: CPU_CORTEX
defflag opt_cputypes.h FPU_VFP
defparam opt_cpuoptions.h XSCALE_CCLKCFG
@@ -26,8 +27,7 @@
defflag opt_cpuoptions.h ARM9_CACHE_WRITE_THROUGH
defflag opt_cpuoptions.h PROCESS_ID_IS_CURLWP
defflag opt_cpuoptions.h PROCESS_ID_IS_CURCPU
-defflag opt_cpuoptions.h ARM11_PMC
-defflag opt_cpuoptions.h CORTEXA8_PMC
+defflag opt_cpuoptions.h ARM11_PMC CORTEX_PMC
defflag opt_cpuoptions.h ARM11_CACHE_WRITE_THROUGH
# Interrupt implementation header definition.
@@ -106,7 +106,7 @@
file arch/arm/arm/cpufunc_asm_arm8.S cpu_arm8
file arch/arm/arm/cpufunc_asm_arm9.S cpu_arm9
file arch/arm/arm/cpufunc_asm_arm10.S cpu_arm9e | cpu_arm10
-file arch/arm/arm/cpufunc_asm_arm11.S cpu_arm11 | cpu_cortexa8
+file arch/arm/arm/cpufunc_asm_arm11.S cpu_arm11 | cpu_cortex
file arch/arm/arm/cpufunc_asm_arm1136.S cpu_arm1136
file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9 | cpu_arm9e |
cpu_arm10 |
@@ -120,13 +120,11 @@
cpu_xscale_ixp425 |
cpu_xscale_pxa250 |
cpu_xscale_pxa270 |
- cpu_cortexa8
+ cpu_cortex
file arch/arm/arm/cpufunc_asm_armv5.S cpu_arm10
file arch/arm/arm/cpufunc_asm_armv5_ec.S cpu_arm9e | cpu_arm10
-file arch/arm/arm/cpufunc_asm_armv6.S cpu_arm11 | cpu_cortexa8
-file arch/arm/arm/cpufunc_asm_armv7.S cpu_cortexa8
-makeoptions cpu_arm11 "AOPTS.cpufunc_asm_armv6.S"+="-Wa,-march=armv6"
-makeoptions cpu_cortexa8 "AOPTS.cpufunc_asm_armv6.S"+="-Wa,-march=armv6"
+file arch/arm/arm/cpufunc_asm_armv6.S cpu_arm11 | cpu_cortex
+file arch/arm/arm/cpufunc_asm_armv7.S cpu_cortex
file arch/arm/arm/cpufunc_asm_sa1.S cpu_sa110 | cpu_sa1100 |
cpu_sa1110 |
cpu_ixp12x0
@@ -137,7 +135,7 @@
cpu_xscale_ixp425 |
cpu_xscale_pxa250 |
cpu_xscale_pxa270 |
- cpu_cortexa8
+ cpu_cortex
file arch/arm/arm/cpufunc_asm_ixp12x0.S cpu_ixp12x0
file arch/arm/arm/fusu.S
file arch/arm/arm/idle_machdep.c
@@ -172,7 +170,7 @@
# files less common to arm32 implementations...
file kern/kern_cctr.c arm11
file arch/arm/arm32/arm11_pmc.c arm11_pmc
-file arch/arm/arm32/cortexa8_pmc.c cortexa8_pmc
+file arch/arm/arm32/cortex_pmc.c cortex_pmc
# arm32 library functions
file arch/arm/arm32/bcopy_page.S arm32
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.42 src/sys/arch/arm/include/armreg.h:1.43
--- src/sys/arch/arm/include/armreg.h:1.42 Wed Jun 16 22:06:53 2010
+++ src/sys/arch/arm/include/armreg.h Sat Jun 19 19:44:58 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.42 2010/06/16 22:06:53 jmcneill Exp $ */
+/* $NetBSD: armreg.h,v 1.43 2010/06/19 19:44:58 matt Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -201,6 +201,7 @@
#define CPU_ID_CORTEXA8R1 0x411fc080
#define CPU_ID_CORTEXA8R2 0x412fc080
#define CPU_ID_CORTEXA8R3 0x413fc080
+#define CPU_ID_CORTEXA9R1 0x411fc090
#define CPU_ID_SA110 0x4401a100
#define CPU_ID_SA1100 0x4401a110
#define CPU_ID_TI925T 0x54029250
@@ -447,9 +448,9 @@
#define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */
#define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */
-/* Defines for ARM CORTEXA8 performance counters */
-#define CORTEXA8_CNTENS_C __BIT(31) /* Enables the cycle counter */
-#define CORTEXA8_CNTENC_C __BIT(31) /* Disables the cycle counter */
-#define CORTEXA8_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */
+/* Defines for ARM CORTEX performance counters */
+#define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */
+#define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */
+#define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */
#endif /* _ARM_ARMREG_H */
Index: src/sys/arch/arm/include/cpuconf.h
diff -u src/sys/arch/arm/include/cpuconf.h:1.17 src/sys/arch/arm/include/cpuconf.h:1.18
--- src/sys/arch/arm/include/cpuconf.h:1.17 Wed Jun 16 22:06:53 2010
+++ src/sys/arch/arm/include/cpuconf.h Sat Jun 19 19:44:58 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuconf.h,v 1.17 2010/06/16 22:06:53 jmcneill Exp $ */
+/* $NetBSD: cpuconf.h,v 1.18 2010/06/19 19:44:58 matt Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@@ -71,6 +71,9 @@
defined(CPU_ARM11) + \
defined(CPU_ARM1136) + \
defined(CPU_ARM1176) + \
+ defined(CPU_CORTEX) + \
+ defined(CPU_CORTEXA8) + \
+ defined(CPU_CORTEXA9) + \
defined(CPU_SA110) + defined(CPU_SA1100) + \
defined(CPU_SA1110) + \
defined(CPU_FA526) + \
@@ -125,13 +128,19 @@
#define ARM_ARCH_6 0
#endif
+#if defined(CPU_CORTEX)
+#define ARM_ARCH_7 1
+#else
+#define ARM_ARCH_7 0
+#endif
+
#define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \
- ARM_ARCH_5 + ARM_ARCH_6)
+ ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7)
#if ARM_NARCH == 0
#error ARM_NARCH is 0
#endif
-#if ARM_ARCH_5 || ARM_ARCH_6
+#if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7
/*
* We could support Thumb code on v4T, but the lack of clean interworking
* makes that hard.
@@ -198,7 +207,7 @@
#endif
#if !defined(_KERNEL_OPT) || \
- defined(CPU_CORTEXA8)
+ defined(CPU_CORTEX)
#define ARM_MMU_V7 1
#else
#define ARM_MMU_V7 0
Index: src/sys/arch/arm/include/cpufunc.h
diff -u src/sys/arch/arm/include/cpufunc.h:1.50 src/sys/arch/arm/include/cpufunc.h:1.51
--- src/sys/arch/arm/include/cpufunc.h:1.50 Wed Jun 16 22:06:53 2010
+++ src/sys/arch/arm/include/cpufunc.h Sat Jun 19 19:44:58 2010
@@ -409,7 +409,7 @@
extern unsigned armv5_dcache_index_inc;
#endif
-#if defined(CPU_ARM11) || defined(CPU_CORTEXA8)
+#if defined(CPU_ARM11) || defined(CPU_CORTEX)
void arm11_setttb (u_int);
void arm11_tlb_flushID_SE (u_int);
@@ -444,7 +444,7 @@
void armv6_idcache_wbinv_range (vaddr_t, vsize_t);
#endif
-#if defined(CPU_CORTEXA8)
+#if defined(CPU_CORTEX)
void armv7_setttb(u_int);
void armv7_icache_sync_range(vaddr_t, vsize_t);
@@ -480,7 +480,8 @@
defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_FA526) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || defined(CPU_CORTEXA8)
+ defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
+ defined(CPU_CORTEX)
void armv4_tlb_flushID (void);
void armv4_tlb_flushI (void);
@@ -498,7 +499,7 @@
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
- defined(CPU_CORTEXA8)
+ defined(CPU_CORTEX)
void xscale_cpwait (void);
#define cpu_cpwait() cpufuncs.cf_cpwait()
@@ -538,7 +539,7 @@
void xscale_context_switch (u_int);
void xscale_setup (char *);
-#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 || CPU_CORTEXA8 */
+#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 || CPU_CORTEX */
#define tlb_flush cpu_tlb_flushID
#define setttb cpu_setttb
Index: src/sys/arch/arm/omap/omap2_mputmr.c
diff -u src/sys/arch/arm/omap/omap2_mputmr.c:1.2 src/sys/arch/arm/omap/omap2_mputmr.c:1.3
--- src/sys/arch/arm/omap/omap2_mputmr.c:1.2 Wed Jun 16 22:06:54 2010
+++ src/sys/arch/arm/omap/omap2_mputmr.c Sat Jun 19 19:44:58 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_mputmr.c,v 1.2 2010/06/16 22:06:54 jmcneill Exp $ */
+/* $NetBSD: omap2_mputmr.c,v 1.3 2010/06/19 19:44:58 matt Exp $ */
/*
* OMAP 2430 GP timers
@@ -77,7 +77,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap2_mputmr.c,v 1.2 2010/06/16 22:06:54 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap2_mputmr.c,v 1.3 2010/06/19 19:44:58 matt Exp $");
#include "opt_omap.h"
#include "opt_cpuoptions.h"
@@ -254,7 +254,7 @@
tc_init(&mpu_timecounter);
}
-#if !(defined(ARM11_PMC) || defined(CORTEXA8_PMC))
+#if !(defined(ARM11_PMC) || defined(CORTEX_PMC))
void
delay(u_int n)
{
@@ -288,7 +288,7 @@
}
}
}
-#endif /* ARM11_PMC || CORTEXA8_PMC */
+#endif /* ARM11_PMC || CORTEX_PMC */
/*
* OVF_Rate =
Index: src/sys/arch/evbarm/conf/BEAGLEBOARD
diff -u src/sys/arch/evbarm/conf/BEAGLEBOARD:1.8 src/sys/arch/evbarm/conf/BEAGLEBOARD:1.9
--- src/sys/arch/evbarm/conf/BEAGLEBOARD:1.8 Fri Apr 16 13:48:30 2010
+++ src/sys/arch/evbarm/conf/BEAGLEBOARD Sat Jun 19 19:44:58 2010
@@ -1,5 +1,5 @@
#
-# $NetBSD: BEAGLEBOARD,v 1.8 2010/04/16 13:48:30 pooka Exp $
+# $NetBSD: BEAGLEBOARD,v 1.9 2010/06/19 19:44:58 matt Exp $
#
# BEAGLEBOARD -- TI OMAP 3530 Eval Board Kernel
#
@@ -204,8 +204,8 @@
# On-board 16550 UARTs
com0 at obio2 addr 0x49020000 intr 74 mult 4 # UART3 (console)
-options CONSADDR=0x49020000, CONSPEED=57600
-#options CONSADDR=0x49020000, CONSPEED=115200
+#options CONSADDR=0x49020000, CONSPEED=57600
+options CONSADDR=0x49020000, CONSPEED=115200
# Operating System Timer
omapmputmr0 at obio2 addr 0x49032000 intr 38 # GP Timer 2
Index: src/sys/arch/evbarm/conf/TISDP2420
diff -u src/sys/arch/evbarm/conf/TISDP2420:1.12 src/sys/arch/evbarm/conf/TISDP2420:1.13
--- src/sys/arch/evbarm/conf/TISDP2420:1.12 Fri Apr 16 13:48:30 2010
+++ src/sys/arch/evbarm/conf/TISDP2420 Sat Jun 19 19:44:58 2010
@@ -1,5 +1,5 @@
#
-# $NetBSD: TISDP2420,v 1.12 2010/04/16 13:48:30 pooka Exp $
+# $NetBSD: TISDP2420,v 1.13 2010/06/19 19:44:58 matt Exp $
#
# TISDP2420 -- TI OMAP 2420 Eval Board Kernel
#
@@ -236,12 +236,6 @@
##umass* at uhub? port ? configuration ? interface ?
##wd* at umass?
-# Hardware clocking and power management
-
-options HWCLOCK
-options HWCLOCK_MACHINE="<arch/arm/omap/hwclock_omap1.h>"
-options OMAP_CK_REF_SPEED=12000000
-
# Pseudo-Devices
# disk/mass storage pseudo-devices
Index: src/sys/arch/evbarm/conf/std.beagle
diff -u src/sys/arch/evbarm/conf/std.beagle:1.2 src/sys/arch/evbarm/conf/std.beagle:1.3
--- src/sys/arch/evbarm/conf/std.beagle:1.2 Fri Jun 18 00:55:06 2010
+++ src/sys/arch/evbarm/conf/std.beagle Sat Jun 19 19:44:58 2010
@@ -1,4 +1,4 @@
-# $NetBSD: std.beagle,v 1.2 2010/06/18 00:55:06 jmcneill Exp $
+# $NetBSD: std.beagle,v 1.3 2010/06/19 19:44:58 matt Exp $
#
# standard NetBSD/evbarm for BEAGLEBAORD options
@@ -13,10 +13,8 @@
# To support easy transit to ../arch/arm/arm32
options ARM32
-#options ARM11_PMC
-#options ARM11_PMC_CCNT_HZ=500000000
-options CORTEXA8_PMC
-options CORTEXA8_CCNT_HZ=720000000
+options CORTEX_PMC
+options CORTEX_PMC_CCNT_HZ=500000000
options __HAVE_FAST_SOFTINTS # should be in types.h
#options PROCESS_ID_IS_CURLWP
options KERNEL_BASE_EXT=0x80000000
Index: src/sys/arch/evbarm/conf/std.igepv2
diff -u src/sys/arch/evbarm/conf/std.igepv2:1.1 src/sys/arch/evbarm/conf/std.igepv2:1.2
--- src/sys/arch/evbarm/conf/std.igepv2:1.1 Wed Jun 16 22:06:54 2010
+++ src/sys/arch/evbarm/conf/std.igepv2 Sat Jun 19 19:44:58 2010
@@ -1,4 +1,4 @@
-# $NetBSD: std.igepv2,v 1.1 2010/06/16 22:06:54 jmcneill Exp $
+# $NetBSD: std.igepv2,v 1.2 2010/06/19 19:44:58 matt Exp $
#
# standard NetBSD/evbarm for IGEPV2 options
@@ -13,8 +13,8 @@
# To support easy transit to ../arch/arm/arm32
options ARM32
-options CORTEXA8_PMC
-options CORTEXA8_CCNT_HZ=720000000
+options CORTEX_PMC
+options CORTEX_PMC_CCNT_HZ=720000000
options __HAVE_FAST_SOFTINTS # should be in types.h
#options PROCESS_ID_IS_CURLWP
options KERNEL_BASE_EXT=0x80000000
Added files:
Index: src/sys/arch/arm/arm32/cortex_pmc.c
diff -u /dev/null src/sys/arch/arm/arm32/cortex_pmc.c:1.1
--- /dev/null Sat Jun 19 19:44:58 2010
+++ src/sys/arch/arm/arm32/cortex_pmc.c Sat Jun 19 19:44:57 2010
@@ -0,0 +1,149 @@
+/* Copyright (c) 2007 Microsoft
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Microsoft
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/*
+ * support for ARM cortexa8 Performance Monitor Counters
+ * based on arm11_pmc.c
+ */
+
+#include <sys/cdefs.h>
+/* __KERNEL_RCSID(0, "$NetBSD: cortex_pmc.c,v 1.1 2010/06/19 19:44:57 matt Exp $"); */
+#include "opt_perfctrs.h"
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/time.h>
+#include <sys/timetc.h>
+#include <dev/clock_subr.h>
+#include <arm/armreg.h>
+#include <arm/cpufunc.h>
+
+#ifndef CORTEX_PMC_CCNT_HZ
+# define CORTEX_PMC_CCNT_HZ 400000000 /* 400MHz */
+#endif
+
+void cortexa8_pmc_ccnt_init(void);
+
+#define COUNTS_PER_USEC (CORTEX_PMC_CCNT_HZ / 1000000)
+
+static uint32_t counts_per_wrap = ~0UL; /* XXX off by 1 */
+
+#define PMNC "c9, c12, 0"
+#define CCNT "c9, c13, 0"
+
+static inline uint32_t
+cortexa8_pmc_ctrl_read(void)
+{
+ uint32_t val;
+
+ __asm volatile ("mrc p15, 0, %0, " PMNC : "=r" (val));
+
+ return val;
+}
+
+static inline void
+cortexa8_pmc_ctrl_write(uint32_t val)
+{
+ __asm volatile ("mcr p15, 0, %0, " PMNC :: "r" (val));
+}
+
+static inline uint32_t
+cortexa8_pmc_ccnt_read(void)
+{
+ uint32_t val;
+
+ __asm volatile ("mrc p15, 0, %0, " CCNT : "=r" (val));
+
+ return val;
+}
+
+static inline void
+cortexa8_pmc_ccnt_write(uint32_t val)
+{
+ __asm volatile ("mcr p15, 0, %0, c9, c12, 2" :: "r" (CORTEX_CNTENC_C));
+ __asm volatile ("mcr p15, 0, %0, " CCNT :: "r" (val));
+ __asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r" (CORTEX_CNTENS_C));
+}
+
+/*
+ * enable the PMC CCNT for delay()
+ */
+void
+cortexa8_pmc_ccnt_init(void)
+{
+ uint32_t val;
+
+ val = ARM11_PMCCTL_E | ARM11_PMCCTL_P | ARM11_PMCCTL_C;
+
+ cortexa8_pmc_ctrl_write(val);
+ __asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r" (CORTEX_CNTENS_C));
+}
+
+/*
+ * delay - for "at least" arg usec
+ *
+ * NOTE: at 400MHz we are restricted to (uint32_t)~0 "counts"
+ * if this is a problem, accumulate counts in LL vars
+ */
+#define DELAY_ARG_LIMIT (((uint32_t)~0) / COUNTS_PER_USEC) /* about 10 sec */
+void
+delay(u_int arg)
+{
+ uint32_t ctrl;
+ uint32_t cur;
+ uint32_t last;
+ uint32_t delta = 0;
+ uint32_t usecs = 0;
+
+ if (arg > DELAY_ARG_LIMIT)
+ panic("delay: arg %u overflow, limit is %d usec\n", arg, DELAY_ARG_LIMIT);
+
+ last = cortexa8_pmc_ccnt_read();
+ delta = usecs = 0;
+ while (arg > usecs) {
+ cur = cortexa8_pmc_ccnt_read();
+
+ /* overflow flag is moved to a separate register
+ and is not read from PMC Control Register */
+ __asm volatile ("mrc p15, 0, %0, c9, c12, 3" : "=r" (ctrl));
+ if(ctrl & CORTEX_CNTOFL_C){
+ /* Reset overflow flag for cycle counter in overflow register */
+ __asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r" (CORTEX_CNTOFL_C));
+ delta += (last + (counts_per_wrap - cur));
+ } else {
+ delta += (cur - last);
+ }
+ last = cur;
+ if (delta >= COUNTS_PER_USEC) {
+ usecs += delta / COUNTS_PER_USEC;
+ delta %= COUNTS_PER_USEC;
+ }
+ }
+}
