Module Name: src
Committed By: jakllsch
Date: Sun Jul 18 03:00:39 UTC 2010
Modified Files:
src/sys/dev/mii: rgephy.c rgephyreg.h
Log Message:
Use standard MII register definitions from mii.h. No binary change.
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/dev/mii/rgephy.c
cvs rdiff -u -r1.5 -r1.6 src/sys/dev/mii/rgephyreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/rgephy.c
diff -u src/sys/dev/mii/rgephy.c:1.28 src/sys/dev/mii/rgephy.c:1.29
--- src/sys/dev/mii/rgephy.c:1.28 Sun Aug 23 13:41:06 2009
+++ src/sys/dev/mii/rgephy.c Sun Jul 18 03:00:39 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rgephy.c,v 1.28 2009/08/23 13:41:06 tsutsui Exp $ */
+/* $NetBSD: rgephy.c,v 1.29 2010/07/18 03:00:39 jakllsch Exp $ */
/*
* Copyright (c) 2003
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.28 2009/08/23 13:41:06 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.29 2010/07/18 03:00:39 jakllsch Exp $");
/*
@@ -203,9 +203,8 @@
rgephy_reset(sc); /* XXX hardware bug work-around */
- anar = PHY_READ(sc, RGEPHY_MII_ANAR);
- anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
- RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
+ anar = PHY_READ(sc, MII_ANAR);
+ anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10);
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_AUTO:
@@ -213,38 +212,37 @@
/*
* If we're already in auto mode, just return.
*/
- if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
+ if (PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN)
return 0;
#endif
(void)rgephy_mii_phy_auto(sc);
break;
case IFM_1000_T:
- speed = RGEPHY_S1000;
+ speed = BMCR_S1000;
goto setit;
case IFM_100_TX:
- speed = RGEPHY_S100;
- anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
+ speed = BMCR_S100;
+ anar |= ANAR_TX_FD | ANAR_TX;
goto setit;
case IFM_10_T:
- speed = RGEPHY_S10;
- anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
+ speed = BMCR_S10;
+ anar |= ANAR_10_FD | ANAR_10;
setit:
rgephy_loop(sc);
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
- speed |= RGEPHY_BMCR_FDX;
- gig = RGEPHY_1000CTL_AFD;
- anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
+ speed |= BMCR_FDX;
+ gig = GTCR_ADV_1000TFDX;
+ anar &= ~(ANAR_TX | ANAR_10);
} else {
- gig = RGEPHY_1000CTL_AHD;
- anar &=
- ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
+ gig = GTCR_ADV_1000THDX;
+ anar &= ~(ANAR_TX_FD | ANAR_10_FD);
}
if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) {
- PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
- PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
- PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
- RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
+ PHY_WRITE(sc, MII_100T2CR, 0);
+ PHY_WRITE(sc, MII_ANAR, anar);
+ PHY_WRITE(sc, MII_BMCR, speed |
+ BMCR_AUTOEN | BMCR_STARTNEG);
break;
}
@@ -257,14 +255,13 @@
* be a master, otherwise it's a slave.
*/
if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
- PHY_WRITE(sc, RGEPHY_MII_1000CTL,
- gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
+ PHY_WRITE(sc, MII_100T2CR,
+ gig|GTCR_MAN_MS|GTCR_ADV_MS);
} else {
- PHY_WRITE(sc, RGEPHY_MII_1000CTL,
- gig|RGEPHY_1000CTL_MSE);
+ PHY_WRITE(sc, MII_100T2CR, gig|GTCR_MAN_MS);
}
- PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
- RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
+ PHY_WRITE(sc, MII_BMCR, speed |
+ BMCR_AUTOEN | BMCR_STARTNEG);
break;
case IFM_NONE:
PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
@@ -366,20 +363,20 @@
mii->mii_media_status |= IFM_ACTIVE;
}
- bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
- bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
+ bmsr = PHY_READ(sc, MII_BMSR);
+ bmcr = PHY_READ(sc, MII_BMCR);
- if ((bmcr & RGEPHY_BMCR_ISO) != 0) {
+ if ((bmcr & BMCR_ISO) != 0) {
mii->mii_media_active |= IFM_NONE;
mii->mii_media_status = 0;
return;
}
- if ((bmcr & RGEPHY_BMCR_LOOP) != 0)
+ if ((bmcr & BMCR_LOOP) != 0)
mii->mii_media_active |= IFM_LOOP;
- if ((bmcr & RGEPHY_BMCR_AUTOEN) != 0) {
- if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
+ if ((bmcr & BMCR_AUTOEN) != 0) {
+ if ((bmsr & BMSR_ACOMP) == 0) {
/* Erg, still trying, I guess... */
mii->mii_media_active |= IFM_NONE;
return;
@@ -436,15 +433,13 @@
anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA;
if (mii->mii_flags & MIIF_DOPAUSE)
- anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
+ anar |= ANAR_FC | ANAR_X_PAUSE_ASYM;
- PHY_WRITE(mii, RGEPHY_MII_ANAR, anar);
+ PHY_WRITE(mii, MII_ANAR, anar);
DELAY(1000);
- PHY_WRITE(mii, RGEPHY_MII_1000CTL,
- RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
+ PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX);
DELAY(1000);
- PHY_WRITE(mii, RGEPHY_MII_BMCR,
- RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
+ PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
DELAY(100);
return EJUSTRETURN;
@@ -459,13 +454,13 @@
rsc = (struct rgephy_softc *)sc;
if (rsc->mii_revision < 2) {
- PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
+ PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN);
DELAY(1000);
}
for (i = 0; i < 15000; i++) {
- bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
- if ((bmsr & RGEPHY_BMSR_LINK) == 0) {
+ bmsr = PHY_READ(sc, MII_BMSR);
+ if ((bmsr & BMSR_LINK) == 0) {
#if 0
device_printf(sc->mii_dev, "looped %d\n", i);
#endif
@@ -613,15 +608,12 @@
/* Reset capabilities */
/* Step1: write our capability */
/* 10/100 capability */
- PHY_WRITE(sc, RGEPHY_MII_ANAR,
- RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
- RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10 | ANAR_CSMA);
+ PHY_WRITE(sc, MII_ANAR,
+ ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
/* 1000 capability */
- PHY_WRITE(sc, RGEPHY_MII_1000CTL,
- RGEPHY_1000CTL_AFD | RGEPHY_1000CTL_AHD);
+ PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX);
/* Step2: Restart NWay */
/* NWay enable and Restart NWay */
- PHY_WRITE(sc, RGEPHY_MII_BMCR,
- RGEPHY_BMCR_RESET | RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
+ PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
}
Index: src/sys/dev/mii/rgephyreg.h
diff -u src/sys/dev/mii/rgephyreg.h:1.5 src/sys/dev/mii/rgephyreg.h:1.6
--- src/sys/dev/mii/rgephyreg.h:1.5 Fri Jan 9 21:56:35 2009
+++ src/sys/dev/mii/rgephyreg.h Sun Jul 18 03:00:39 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rgephyreg.h,v 1.5 2009/01/09 21:56:35 cegger Exp $ */
+/* $NetBSD: rgephyreg.h,v 1.6 2010/07/18 03:00:39 jakllsch Exp $ */
/*
* Copyright (c) 2003
@@ -41,104 +41,6 @@
* RealTek 8169S/8110S gigE PHY registers
*/
-#define RGEPHY_MII_BMCR 0x00
-#define RGEPHY_BMCR_RESET 0x8000
-#define RGEPHY_BMCR_LOOP 0x4000
-#define RGEPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
-#define RGEPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
-#define RGEPHY_BMCR_PDOWN 0x0800 /* Power down */
-#define RGEPHY_BMCR_ISO 0x0400 /* Isolate */
-#define RGEPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
-#define RGEPHY_BMCR_FDX 0x0100 /* Duplex mode */
-#define RGEPHY_BMCR_CTEST 0x0080 /* Collision test enable */
-#define RGEPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
-
-#define RGEPHY_S1000 RGEPHY_BMCR_SPD1 /* 1000mbps */
-#define RGEPHY_S100 RGEPHY_BMCR_SPD0 /* 100mpbs */
-#define RGEPHY_S10 0 /* 10mbps */
-
-#define RGEPHY_MII_BMSR 0x01
-#define RGEPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */
-#define RGEPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
-#define RGEPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
-#define RGEPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
-#define RGEPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
-#define RGEPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
-#define RGEPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
-#define RGEPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
-#define RGEPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
-#define RGEPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
-#define RGEPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
-#define RGEPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
-#define RGEPHY_BMSR_LINK 0x0004 /* Link status */
-#define RGEPHY_BMSR_JABBER 0x0002 /* Jabber detected */
-#define RGEPHY_BMSR_EXT 0x0001 /* Extended capability */
-
-#define RGEPHY_MII_ANAR 0x04
-#define RGEPHY_ANAR_NP 0x8000 /* Next page */
-#define RGEPHY_ANAR_RF 0x2000 /* Remote fault */
-#define RGEPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */
-#define RGEPHY_ANAR_PC 0x0400 /* Pause capable */
-#define RGEPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */
-#define RGEPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */
-#define RGEPHY_ANAR_TX 0x0080 /* local device supports 100bTx */
-#define RGEPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */
-#define RGEPHY_ANAR_10 0x0020 /* local device supports 10bT */
-#define RGEPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */
-
-#define RGEPHY_MII_ANLPAR 0x05
-#define RGEPHY_ANLPAR_NP 0x8000 /* Next page */
-#define RGEPHY_ANLPAR_RF 0x2000 /* Remote fault */
-#define RGEPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */
-#define RGEPHY_ANLPAR_PC 0x0400 /* Pause capable */
-#define RGEPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */
-#define RGEPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */
-#define RGEPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */
-#define RGEPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */
-#define RGEPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */
-#define RGEPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */
-
-#define RGEPHY_SEL_TYPE 0x0001 /* ethernet */
-
-#define RGEPHY_MII_ANER 0x06
-#define RGEPHY_ANER_PDF 0x0010 /* Parallel detection fault */
-#define RGEPHY_ANER_LPNP 0x0008 /* Link partner can next page */
-#define RGEPHY_ANER_NP 0x0004 /* Local PHY can next page */
-#define RGEPHY_ANER_RX 0x0002 /* Next page received */
-#define RGEPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
-
-#define RGEPHY_MII_NEXTP 0x07 /* Next page */
-
-#define RGEPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */
-
-#define RGEPHY_MII_1000CTL 0x09 /* 1000baseT control */
-#define RGEPHY_1000CTL_TST 0xE000 /* test modes */
-#define RGEPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */
-#define RGEPHY_1000CTL_MSC 0x0800 /* Master/Slave select */
-#define RGEPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
-#define RGEPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
-#define RGEPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
-
-#define RGEPHY_TEST_TX_JITTER 0x2000
-#define RGEPHY_TEST_TX_JITTER_MASTER_MODE 0x4000
-#define RGEPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000
-#define RGEPHY_TEST_TX_DISTORTION 0x8000
-
-#define RGEPHY_MII_1000STS 0x0A /* 1000baseT status */
-#define RGEPHY_1000STS_MSF 0x8000 /* Master/slave fault */
-#define RGEPHY_1000STS_MSR 0x4000 /* Master/slave result */
-#define RGEPHY_1000STS_LRS 0x2000 /* Local receiver status */
-#define RGEPHY_1000STS_RRS 0x1000 /* Remote receiver status */
-#define RGEPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
-#define RGEPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
-#define RGEPHY_1000STS_IEC 0x00FF /* Idle error count */
-
-#define RGEPHY_MII_EXTSTS 0x0F /* Extended status */
-#define RGEPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
-#define RGEPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
-#define RGEPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
-#define RGEPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
-
/* RTL8211B(L)/RTL8211C(L) */
#define RGEPHY_MII_SSR 0x11 /* PHY Specific status register */
#define RGEPHY_SSR_S1000 0x8000 /* 1000Mbps */
