Module Name: src
Committed By: skrll
Date: Wed Nov 10 22:34:25 UTC 2010
Modified Files:
src/sys/arch/hp700/conf: GENERIC
src/sys/dev/pci: files.pci
Added Files:
src/sys/dev/pci: nside.c pciide_natsemi_reg.h
Log Message:
Add nside(4) - a driver for the National Semiconductor PC87415 IDE
controller as found in many HP PA-RISC machines.
>From OpenBSD.
Reviewed by Manuel Bouyer.
To generate a diff of this commit:
cvs rdiff -u -r1.103 -r1.104 src/sys/arch/hp700/conf/GENERIC
cvs rdiff -u -r1.332 -r1.333 src/sys/dev/pci/files.pci
cvs rdiff -u -r0 -r1.1 src/sys/dev/pci/nside.c \
src/sys/dev/pci/pciide_natsemi_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/hp700/conf/GENERIC
diff -u src/sys/arch/hp700/conf/GENERIC:1.103 src/sys/arch/hp700/conf/GENERIC:1.104
--- src/sys/arch/hp700/conf/GENERIC:1.103 Tue Nov 9 12:24:47 2010
+++ src/sys/arch/hp700/conf/GENERIC Wed Nov 10 22:34:24 2010
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.103 2010/11/09 12:24:47 skrll Exp $
+# $NetBSD: GENERIC,v 1.104 2010/11/10 22:34:24 skrll Exp $
#
# GENERIC machine description file
#
@@ -23,7 +23,7 @@
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel
-#ident "GENERIC-$Revision: 1.103 $"
+#ident "GENERIC-$Revision: 1.104 $"
maxusers 32 # estimated number of users
@@ -416,6 +416,7 @@
cypide* at pci? dev ? function ? # Cypress IDE controllers
geodeide* at pci? dev ? function ? # AMD Geode IDE controllers
hptide* at pci? dev ? function ? # Triones/HighPoint IDE controllers
+nside* at pci? dev ? function ? # National Semiconductor IDE controllers
optiide* at pci? dev ? function ? # Opti IDE controllers
pdcide* at pci? dev ? function ? # Promise IDE controllers
pdcsata* at pci? dev ? function ? # Promise SATA150 controllers
Index: src/sys/dev/pci/files.pci
diff -u src/sys/dev/pci/files.pci:1.332 src/sys/dev/pci/files.pci:1.333
--- src/sys/dev/pci/files.pci:1.332 Tue Nov 9 12:24:48 2010
+++ src/sys/dev/pci/files.pci Wed Nov 10 22:34:24 2010
@@ -1,4 +1,4 @@
-# $NetBSD: files.pci,v 1.332 2010/11/09 12:24:48 skrll Exp $
+# $NetBSD: files.pci,v 1.333 2010/11/10 22:34:24 skrll Exp $
#
# Config file and device description for machine-independent PCI code.
# Included by ports that need it. Requires that the SCSI files be
@@ -274,6 +274,11 @@
attach ahcisata at jmide_hl with jmahci
file dev/pci/jmide.c jmide | jmahci needs-flag
+# National Semiconductor IDE controllers
+device nside: ata, ata_dma, ata_udma, pciide_common, wdc_common
+attach nside at pci
+file dev/pci/nside.c nside
+
# Opti IDE controllers
device optiide: ata, ata_dma, pciide_common, wdc_common
attach optiide at pci
Added files:
Index: src/sys/dev/pci/nside.c
diff -u /dev/null src/sys/dev/pci/nside.c:1.1
--- /dev/null Wed Nov 10 22:34:25 2010
+++ src/sys/dev/pci/nside.c Wed Nov 10 22:34:24 2010
@@ -0,0 +1,260 @@
+/* $NetBSD: nside.c,v 1.1 2010/11/10 22:34:24 skrll Exp $ */
+
+/*
+ * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: nside.c,v 1.1 2010/11/10 22:34:24 skrll Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+#include <dev/pci/pciidereg.h>
+#include <dev/pci/pciidevar.h>
+#include <dev/pci/pciide_natsemi_reg.h>
+
+static void natsemi_chip_map(struct pciide_softc*, struct pci_attach_args*);
+static void natsemi_setup_channel(struct ata_channel*);
+static int natsemi_pci_intr(void *);
+static void natsemi_irqack(struct ata_channel *);
+
+static int nside_match(device_t, cfdata_t, void *);
+static void nside_attach(device_t, device_t, void *);
+
+struct nside_softc {
+ struct pciide_softc pciide_sc;
+ struct pci_attach_args pcib_pa;
+};
+
+CFATTACH_DECL_NEW(nside, sizeof(struct nside_softc),
+ nside_match, nside_attach, NULL, NULL);
+
+static const struct pciide_product_desc pciide_natsemi_products[] = {
+ { PCI_PRODUCT_NS_PC87415, /* National Semi PC87415 IDE */
+ 0,
+ "National Semiconductor PC87415 IDE Controller",
+ natsemi_chip_map,
+ },
+ { 0,
+ 0,
+ NULL,
+ NULL
+ }
+};
+
+static int
+nside_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct pci_attach_args *pa = aux;
+
+ if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS &&
+ PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
+ PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
+ if (pciide_lookup_product(pa->pa_id, pciide_natsemi_products))
+ return 2;
+ }
+ return 0;
+}
+
+static void
+nside_attach(device_t parent, device_t self, void *aux)
+{
+ struct pci_attach_args *pa = aux;
+ struct pciide_softc *sc = device_private(self);
+
+ sc->sc_wdcdev.sc_atac.atac_dev = self;
+
+ pciide_common_attach(sc, pa,
+ pciide_lookup_product(pa->pa_id, pciide_natsemi_products));
+}
+
+static void
+natsemi_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
+{
+ struct pciide_channel *cp;
+ int channel;
+ pcireg_t interface, ctl;
+
+ if (pciide_chipen(sc, pa) == 0)
+ return;
+
+ aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
+ "bus-master DMA support present");
+ pciide_mapreg_dma(sc, pa);
+ aprint_verbose("\n");
+
+ sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
+
+ if (sc->sc_dma_ok) {
+ sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
+ sc->sc_wdcdev.irqack = natsemi_irqack;
+ }
+
+ pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CCBT, 0xb7);
+
+ /*
+ * Mask off interrupts from both channels, appropriate channel(s)
+ * will be unmasked later.
+ */
+ pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2,
+ pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) |
+ NATSEMI_CHMASK(0) | NATSEMI_CHMASK(1));
+
+ sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
+ sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
+ sc->sc_wdcdev.sc_atac.atac_set_modes = natsemi_setup_channel;
+ sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
+ sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
+
+ interface = PCI_INTERFACE(pa->pa_class);
+ interface &= ~PCIIDE_CHANSTATUS_EN; /* Reserved on PC87415 */
+
+ /* If we're in PCIIDE mode, unmask INTA, otherwise mask it. */
+ ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1);
+ if (interface & (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1)))
+ ctl &= ~NATSEMI_CTRL1_INTAMASK;
+ else
+ ctl |= NATSEMI_CTRL1_INTAMASK;
+ pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl);
+
+ wdc_allocate_regs(&sc->sc_wdcdev);
+
+ for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; channel++) {
+ cp = &sc->pciide_channels[channel];
+ if (pciide_chansetup(sc, channel, interface) == 0)
+ continue;
+
+ pciide_mapchan(pa, cp, interface, natsemi_pci_intr);
+
+ pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2,
+ pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) &
+ ~(NATSEMI_CHMASK(channel)));
+ }
+}
+
+void
+natsemi_setup_channel(struct ata_channel *chp)
+{
+ struct ata_drive_datas *drvp;
+ int drive, ndrives = 0;
+ uint32_t idedma_ctl = 0;
+ struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
+ struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
+ uint8_t tim;
+
+ /* setup DMA if needed */
+ pciide_channel_dma_setup(cp);
+
+ for (drive = 0; drive < 2; drive++) {
+ drvp = &chp->ch_drive[drive];
+ /* If no drive, skip */
+ if ((drvp->drive_flags & DRIVE) == 0)
+ continue;
+
+ ndrives++;
+ /* add timing values, setup DMA if needed */
+ if ((drvp->drive_flags & DRIVE_DMA) == 0) {
+ tim = natsemi_pio_pulse[drvp->PIO_mode] |
+ (natsemi_pio_recover[drvp->PIO_mode] << 4);
+ } else {
+ /*
+ * use Multiword DMA
+ * Timings will be used for both PIO and DMA,
+ * so adjust DMA mode if needed
+ */
+ if (drvp->PIO_mode >= 3 &&
+ (drvp->DMA_mode + 2) > drvp->PIO_mode) {
+ drvp->DMA_mode = drvp->PIO_mode - 2;
+ }
+ idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
+ tim = natsemi_dma_pulse[drvp->DMA_mode] |
+ (natsemi_dma_recover[drvp->DMA_mode] << 4);
+
+ }
+
+ pciide_pci_write(sc->sc_pc, sc->sc_tag,
+ NATSEMI_RTREG(chp->ch_channel, drive), tim);
+ pciide_pci_write(sc->sc_pc, sc->sc_tag,
+ NATSEMI_WTREG(chp->ch_channel, drive), tim);
+ }
+
+ if (idedma_ctl != 0) {
+ /* Add software bits in status register */
+ bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
+ idedma_ctl);
+
+ }
+ /* Go ahead and ack interrupts generated during probe. */
+ natsemi_irqack(chp);
+}
+
+void
+natsemi_irqack(struct ata_channel *chp)
+{
+ struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
+ struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
+ uint8_t clr;
+
+ /* Errata: The "clear" bits are in the wrong register *sigh* */
+ clr = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0);
+ clr |= bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0) &
+ (IDEDMA_CTL_ERR | IDEDMA_CTL_INTR);
+ bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, clr);
+}
+
+int
+natsemi_pci_intr(void *arg)
+{
+ struct pciide_softc *sc = arg;
+ struct pciide_channel *cp;
+ struct ata_channel *wdc_cp;
+ int i, rv, crv;
+ uint8_t msk;
+
+ rv = 0;
+ msk = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2);
+ for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
+ cp = &sc->pciide_channels[i];
+ wdc_cp = &cp->ata_channel;
+
+ /* If a compat channel skip. */
+ if (cp->compat)
+ continue;
+
+ /* If this channel is masked, skip it. */
+ if (msk & NATSEMI_CHMASK(i))
+ continue;
+
+ crv = wdcintr(wdc_cp);
+ if (crv == 0)
+ ; /* leave alone */
+ else if (crv == 1)
+ rv = 1; /* claim the intr */
+ else if (rv == 0) /* crv should be -1 in this case */
+ rv = crv; /* if we've done no better, take it */
+ }
+ return (rv);
+}
Index: src/sys/dev/pci/pciide_natsemi_reg.h
diff -u /dev/null src/sys/dev/pci/pciide_natsemi_reg.h:1.1
--- /dev/null Wed Nov 10 22:34:25 2010
+++ src/sys/dev/pci/pciide_natsemi_reg.h Wed Nov 10 22:34:24 2010
@@ -0,0 +1,107 @@
+/* $NetBSD: pciide_natsemi_reg.h,v 1.1 2010/11/10 22:34:24 skrll Exp $ */
+
+/* $OpenBSD: pciide_natsemi_reg.h,v 1.7 2007/06/24 12:41:19 kettenis Exp $ */
+
+/*
+ * Copyright (c) 2001 Jason L. Wright ([email protected])
+ * Copyright (c) 2004 Alexander Yurchenko <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_PCI_PCIIDE_NATSEMI_REG_H_
+#define _DEV_PCI_PCIIDE_NATSEMI_REG_H_
+
+/*
+ * Register definitions for National Semiconductor PC87415. Definitions
+ * based on "PC87415: PCI-IDE DMA Master Mode Interface Controller"
+ * (March 1996) datasheet from their website.
+ */
+
+#define NATSEMI_CTRL1 0x40 /* Control register1 */
+#define NATSEMI_CTRL1_SWRST 0x04 /* sw rst to ch1/ch2 on */
+#define NATSEMI_CTRL1_IDEPWR 0x08
+#define NATSEMI_CTRL1_CH1INTMAP 0x10
+#define NATSEMI_CTRL1_CH2INTMAP 0x20
+#define NATSEMI_CTRL1_INTAMASK 0x40
+#define NATSEMI_CTRL1_IDWR 0x80 /* write to did/vid enable */
+
+#define NATSEMI_CTRL2 0x41 /* Control register2 */
+#define NATSEMI_CTRL2_CH1MASK 0x01 /* channel 1 intr masked */
+#define NATSEMI_CTRL2_CH2MASK 0x02 /* channel 2 intr masked */
+#define NATSEMI_CTRL2_BARDIS 0x04 /* PCI BAR 2/3 disable */
+#define NATSEMI_CTRL2_WATCHDOG 0x08 /* enable watchdog timer */
+#define NATSEMI_CTRL2_BUF1BYP 0x10 /* bypass buffer 1 */
+#define NATSEMI_CTRL2_BUF2BYP 0x20 /* bypass buffer 2 */
+#define NATSEMI_CTRL2_IDE1MAP 0x40 /* IDE at bar 1 */
+#define NATSEMI_CTRL2_IDE2MAP 0x80 /* IDE at bar 2 */
+
+#define NATSEMI_CHMASK(chn) (NATSEMI_CTRL2_CH1MASK << (chn))
+
+#define NATSEMI_CTRL3 0x42 /* Control register3 */
+#define NATSEMI_CTRL3_CH1PREDIS 0x01 /* channel 1 prefetch disable */
+#define NATSEMI_CTRL3_CH2PREDIS 0x02 /* channel 2 prefetch disable */
+#define NATSEMI_CTRL3_RSTIDLE 0x04 /* reset idle state */
+#define NATSEMI_CTRL3_C1D1DMARQ 0x10 /* c1d1 dmarq handshaking */
+#define NATSEMI_CTRL3_C1D2DMARQ 0x20 /* c1d2 dmarq handshaking */
+#define NATSEMI_CTRL3_C2D1DMARQ 0x40 /* c2d1 dmarq handshaking */
+#define NATSEMI_CTRL3_C2D2DMARQ 0x80 /* c2d2 dmarq handshaking */
+
+#define NATSEMI_WBS 0x43 /* Write buffer status */
+#define NATSEMI_WBS_WB1NMPTY 0x01 /* chan 1 write buf not empty */
+#define NATSEMI_WBS_WB2NMPTY 0x02 /* chan 2 write buf not empty */
+
+#define NATSEMI_C1D1DRT 0x44 /* Channel 1/device 1 data read timing */
+#define NATSEMI_C1D1DWT 0x45 /* Channel 1/device 1 data write timing */
+#define NATSEMI_C1D2DRT 0x48 /* Channel 1/device 2 data read timing */
+#define NATSEMI_C1D2DWT 0x49 /* Channel 1/device 2 data write timing */
+#define NATSEMI_C2D1DRT 0x4c /* Channel 2/device 1 data read timing */
+#define NATSEMI_C2D1DWT 0x4d /* Channel 2/device 1 data write timing */
+#define NATSEMI_C2D2DRT 0x50 /* Channel 2/device 2 data read timing */
+#define NATSEMI_C2D2DWT 0x51 /* Channel 2/device 2 data write timing */
+
+#define NATSEMI_CCBT 0x54 /* Command and control block timing */
+
+#define NATSEMI_SECT 0x55 /* Sector size */
+#define NATSEMI_SECT_C1UNUSED 0x0f /* not used */
+#define NATSEMI_SECT_C1_512 0x0e /* 512 bytes */
+#define NATSEMI_SECT_C1_1024 0x0c /* 1024 bytes */
+#define NATSEMI_SECT_C1_2048 0x08 /* 2048 bytes */
+#define NATSEMI_SECT_C1_4096 0x00 /* 4096 bytes */
+#define NATSEMI_SECT_C2UNUSED 0xf0 /* not used */
+#define NATSEMI_SECT_C2_512 0xe0 /* 512 bytes */
+#define NATSEMI_SECT_C2_1024 0xc0 /* 1024 bytes */
+#define NATSEMI_SECT_C2_2048 0x80 /* 2048 bytes */
+#define NATSEMI_SECT_C2_4096 0x00 /* 4096 bytes */
+
+#define NATSEMI_RTREG(c,d) (0x44 + (c * 8) + (d * 4) + 0)
+#define NATSEMI_WTREG(c,d) (0x44 + (c * 8) + (d * 4) + 1)
+
+/* 17 - N = number of clocks */
+static u_int8_t natsemi_pio_pulse[] = { 7, 12, 13, 14, 14 };
+static u_int8_t natsemi_dma_pulse[] = { 7, 10, 10 };
+/* 16 - N = number of clocks */
+static u_int8_t natsemi_pio_recover[] = { 6, 8, 11, 13, 15 };
+static u_int8_t natsemi_dma_recover[] = { 6, 8, 9 };
+
+#endif /* !_DEV_PCI_PCIIDE_NATSEMI_REG_H_ */
