Module Name: src
Committed By: matt
Date: Wed Dec 29 00:50:29 UTC 2010
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: locore.S mips_emul.c
mips_fputrap.c
Log Message:
Move from StudlyCaps to more normal names.
To generate a diff of this commit:
cvs rdiff -u -r1.167.38.21 -r1.167.38.22 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r1.14.78.11 -r1.14.78.12 src/sys/arch/mips/mips/mips_emul.c
cvs rdiff -u -r1.5.66.5 -r1.5.66.6 src/sys/arch/mips/mips/mips_fputrap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/locore.S
diff -u src/sys/arch/mips/mips/locore.S:1.167.38.21 src/sys/arch/mips/mips/locore.S:1.167.38.22
--- src/sys/arch/mips/mips/locore.S:1.167.38.21 Wed Dec 22 06:13:36 2010
+++ src/sys/arch/mips/mips/locore.S Wed Dec 29 00:50:29 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.167.38.21 2010/12/22 06:13:36 matt Exp $ */
+/* $NetBSD: locore.S,v 1.167.38.22 2010/12/29 00:50:29 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -575,23 +575,15 @@
#if !defined(NOFPU) || defined(FPEMUL)
/*----------------------------------------------------------------------------
*
- * MachFPInterrupt --
- * MachFPTrap --
+ * mips_fpu_intr --
+ * mips_fpu_trap --
*
* Handle a floating point interrupt (r3k) or trap (r4k).
* the handlers are indentical, only the reporting mechanisms differ.
*
- * MachFPInterrupt(status, cause, pc, frame)
- * unsigned status;
- * unsigned cause;
- * unsigned pc;
- * int *frame;
- *
- * MachFPTrap(status, cause, pc, frame)
- * unsigned status;
- * unsigned cause;
- * unsigned pc;
- * int *frame;
+ * mips_fpu_intr(vaddr_t pc, struct trapframe *tf)
+ *
+ * mips_fpu_trap(vaddr_t pc, struct trapframe *tf)
*
* Results:
* None.
@@ -601,8 +593,8 @@
*
*----------------------------------------------------------------------------
*/
-NESTED(MachFPInterrupt, CALLFRAME_SIZ, ra)
-XNESTED(MachFPTrap)
+NESTED(mips_fpu_intr, CALLFRAME_SIZ, ra)
+XNESTED(mips_fpu_trap)
.mask 0x80000000, -4
PTR_SUBU sp, CALLFRAME_SIZ
mfc0 t0, MIPS_COP_0_STATUS
@@ -611,12 +603,17 @@
mtc0 t0, MIPS_COP_0_STATUS
COP0_HAZARD_FPUENABLE
+ REG_PROLOGUE
+ REG_L t3, TF_REG_CAUSE(a1)
+ REG_EPILOGUE
+
cfc1 t0, MIPS_FPU_CSR # stall til FP done
cfc1 t0, MIPS_FPU_CSR # now get status
nop
sll t2, t0, (31 - 17) # unimplemented operation?
bgez t2, 3f # no, normal trap
- nop
+ nop
+
/*
* We got an unimplemented operation trap so
* We received an unimplemented operation trap.
@@ -626,21 +623,22 @@
*
* fetch the instruction and emulate the instruction.
*/
- bgez a1, 1f # Check the branch delay bit.
- nop
+ bgez t3, 1f # Check the branch delay bit.
+ nop
/*
* The instruction is in the branch delay slot.
*/
+ move a2, a0 # 3rd arg is opcode address
+
b 2f
- lw a0, 4(a2) # a0 = coproc instruction
+ INT_L a0, 4(a0) # a0 = coproc instruction
/*
* This is not in the branch delay slot so calculate the resulting
* PC (epc + 4) into v0 and continue to MachEmulateFP().
*/
1:
- lw a0, 4(a2) # a0 = coproc instruction
+ INT_L a0, 4(a0) # a0 = coproc instruction
2:
- move a2, a1
/*
* Check to see if the instruction to be emulated is a floating-point
@@ -648,24 +646,24 @@
*/
srl t0, a0, MIPS_OPCODE_SHIFT
beq t0, MIPS_OPCODE_C1, 4f
- nop
+ nop
/*
* Send a floating point exception signal to the current LWP.
*/
- li t0, 0xFFFFFF00
- and a1, a1, t0
- ori a1, a1, T_RES_INST << MIPS_CR_EXC_CODE_SHIFT
+ srl t0, 8
+ sll t0, 8
+ ori t3, T_RES_INST << MIPS_CR_EXC_CODE_SHIFT
REG_PROLOGUE
- REG_S a1, TF_REG_CAUSE(a3)
+ REG_S t3, TF_REG_CAUSE(a3)
REG_EPILOGUE
move a1, a0 # code = instruction
jal _C_LABEL(mips_fpuillinst)
- move a0, MIPS_CURLWP # get current LWP
+ move a0, MIPS_CURLWP # get current LWP
b FPReturn
- nop
+ nop
/*
* Send a FPE signal to the current LWP if it tripped the any of
@@ -673,7 +671,7 @@
*/
3:
REG_PROLOGUE
- REG_S a1, TF_REG_CAUSE(a3)
+ REG_S t3, TF_REG_CAUSE(a3)
REG_EPILOGUE
and a0, t0, ~MIPS_FPU_EXCEPTION_BITS
@@ -681,17 +679,18 @@
move a1, t0 # FPU status
jal _C_LABEL(mips_fpuexcept)
- move a0, MIPS_CURLWP # get current LWP
+ move a0, MIPS_CURLWP # get current LWP
b FPReturn
- nop
+ nop
/*
- * Finally, we can call MachEmulateFP() where a0 is the instruction to emulate.
+ * Finally, we can call
+ * mips_emul(uint32_t insn, struct trapframe *tf, vaddr_t pc).
*/
4:
- jal _C_LABEL(MachEmulateFP)
- move a1, a3
+ jal _C_LABEL(mips_emul_fp)
+ nop
/*
* Turn off the floating point coprocessor and return.
@@ -699,12 +698,12 @@
FPReturn:
mfc0 t0, MIPS_COP_0_STATUS
REG_L ra, CALLFRAME_RA(sp)
- and t0, t0, ~MIPS_SR_COP_1_BIT
+ and t0, ~MIPS_SR_COP_1_BIT
mtc0 t0, MIPS_COP_0_STATUS
COP0_SYNC
j ra
- PTR_ADDU sp, CALLFRAME_SIZ
-END(MachFPInterrupt)
+ PTR_ADDU sp, CALLFRAME_SIZ
+END(mips_fpu_intr)
#endif /* !defined(NOFPU) || defined(FPEMUL) */
LEAF(mips_pagecopy)
Index: src/sys/arch/mips/mips/mips_emul.c
diff -u src/sys/arch/mips/mips/mips_emul.c:1.14.78.11 src/sys/arch/mips/mips/mips_emul.c:1.14.78.12
--- src/sys/arch/mips/mips/mips_emul.c:1.14.78.11 Tue Jun 1 19:10:45 2010
+++ src/sys/arch/mips/mips/mips_emul.c Wed Dec 29 00:50:29 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_emul.c,v 1.14.78.11 2010/06/01 19:10:45 matt Exp $ */
+/* $NetBSD: mips_emul.c,v 1.14.78.12 2010/12/29 00:50:29 matt Exp $ */
/*
* Copyright (c) 1999 Shuichiro URATA. All rights reserved.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mips_emul.c,v 1.14.78.11 2010/06/01 19:10:45 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_emul.c,v 1.14.78.12 2010/12/29 00:50:29 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -43,49 +43,10 @@
#include <mips/vmparam.h> /* for VM_MAX_ADDRESS */
#include <mips/trap.h>
-#if !defined(NOFPU) || defined(FPEMUL)
-void MachEmulateFP(uint32_t, struct reg *, uint32_t);
-#endif
-
static inline void send_sigsegv(intptr_t, uint32_t, struct trapframe *,
uint32_t);
static inline void update_pc(struct trapframe *, uint32_t);
-vaddr_t MachEmulateBranch(struct trapframe *, vaddr_t, unsigned, int);
-void MachEmulateInst(uint32_t, uint32_t, vaddr_t, struct trapframe *);
-
-void MachEmulateLWC0(uint32_t, struct trapframe *, uint32_t);
-void MachEmulateSWC0(uint32_t, struct trapframe *, uint32_t);
-void MachEmulateSpecial(uint32_t, struct trapframe *, uint32_t);
-void MachEmulateSpecial3(uint32_t, struct trapframe *, uint32_t);
-void MachEmulateLWC1(uint32_t, struct trapframe *, uint32_t);
-void MachEmulateLDC1(uint32_t, struct trapframe *, uint32_t);
-void MachEmulateSWC1(uint32_t, struct trapframe *, uint32_t);
-void MachEmulateSDC1(uint32_t, struct trapframe *, uint32_t);
-
-void bcemul_lb(uint32_t, struct trapframe *, uint32_t);
-void bcemul_lbu(uint32_t, struct trapframe *, uint32_t);
-void bcemul_lh(uint32_t, struct trapframe *, uint32_t);
-void bcemul_lhu(uint32_t, struct trapframe *, uint32_t);
-void bcemul_lw(uint32_t, struct trapframe *, uint32_t);
-void bcemul_lwl(uint32_t, struct trapframe *, uint32_t);
-void bcemul_lwr(uint32_t, struct trapframe *, uint32_t);
-#if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64)
-void bcemul_ld(uint32_t, struct trapframe *, uint32_t);
-void bcemul_ldl(uint32_t, struct trapframe *, uint32_t);
-void bcemul_ldr(uint32_t, struct trapframe *, uint32_t);
-#endif
-void bcemul_sb(uint32_t, struct trapframe *, uint32_t);
-void bcemul_sh(uint32_t, struct trapframe *, uint32_t);
-void bcemul_sw(uint32_t, struct trapframe *, uint32_t);
-void bcemul_swl(uint32_t, struct trapframe *, uint32_t);
-void bcemul_swr(uint32_t, struct trapframe *, uint32_t);
-#if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64)
-void bcemul_sd(uint32_t, struct trapframe *, uint32_t);
-void bcemul_sdl(uint32_t, struct trapframe *, uint32_t);
-void bcemul_sdr(uint32_t, struct trapframe *, uint32_t);
-#endif
-
/*
* MIPS2 LL instruction emulation state
*/
@@ -99,8 +60,8 @@
* Analyse 'next' PC address taking account of branch/jump instructions
*/
vaddr_t
-MachEmulateBranch(struct trapframe *tf, vaddr_t instpc, unsigned fpuCSR,
- int allowNonBranch)
+mips_emul_branch(struct trapframe *tf, vaddr_t instpc, uint32_t fpuCSR,
+ bool allowNonBranch)
{
#define BRANCHTARGET(pc, i) (4 + (pc) + ((short)(i).IType.imm << 2))
InstFmt inst;
@@ -109,7 +70,7 @@
if (instpc < MIPS_KSEG0_START)
inst.word = ufetch_uint32((void *)instpc);
else
- inst.word = *(unsigned *)instpc;
+ inst.word = *(uint32_t *)instpc;
switch ((int)inst.JType.op) {
case OP_SPECIAL:
@@ -153,7 +114,7 @@
case OP_J:
case OP_JAL:
nextpc = (inst.JType.target << 2) |
- ((unsigned)instpc & 0xF0000000);
+ ((intptr_t)instpc & 0xF0000000);
break;
case OP_BEQ:
@@ -220,7 +181,7 @@
* Emulate instructions (including floating-point instructions)
*/
void
-MachEmulateInst(uint32_t status, uint32_t cause, vaddr_t opc,
+mips_emul_inst(uint32_t status, uint32_t cause, vaddr_t opc,
struct trapframe *tf)
{
uint32_t inst;
@@ -237,40 +198,40 @@
switch (((InstFmt)inst).FRType.op) {
case OP_LWC0:
- MachEmulateLWC0(inst, tf, cause);
+ mips_emul_lwc0(inst, tf, cause);
break;
case OP_SWC0:
- MachEmulateSWC0(inst, tf, cause);
+ mips_emul_swc0(inst, tf, cause);
break;
case OP_SPECIAL:
- MachEmulateSpecial(inst, tf, cause);
+ mips_emul_special(inst, tf, cause);
break;
case OP_SPECIAL3:
- MachEmulateSpecial3(inst, tf, cause);
+ mips_emul_special3(inst, tf, cause);
break;
case OP_COP1:
#if defined(FPEMUL)
- MachEmulateFP(inst, &tf->tf_registers, cause);
+ mips_emul_fp(inst, tf, cause);
break;
#endif
case OP_LWC1:
#if defined(FPEMUL)
- MachEmulateLWC1(inst, tf, cause);
+ mips_emul_lwc1(inst, tf, cause);
break;
#endif
case OP_LDC1:
#if defined(FPEMUL)
- MachEmulateLDC1(inst, tf, cause);
+ mips_emul_ldc1(inst, tf, cause);
break;
#endif
case OP_SWC1:
#if defined(FPEMUL)
- MachEmulateSWC1(inst, tf, cause);
+ mips_emul_swc1(inst, tf, cause);
break;
#endif
case OP_SDC1:
#if defined(FPEMUL)
- MachEmulateSDC1(inst, tf, cause);
+ mips_emul_sdc1(inst, tf, cause);
break;
#else
code = ILL_COPROC;
@@ -297,7 +258,7 @@
uint32_t cause)
{
ksiginfo_t ksi;
- cause = (cause & 0xFFFFFF00) | (exccode << MIPS_CR_EXC_CODE_SHIFT);
+ cause = (cause & ~0xFF) | (exccode << MIPS_CR_EXC_CODE_SHIFT);
tf->tf_regs[_R_CAUSE] = cause;
tf->tf_regs[_R_BADVADDR] = vaddr;
KSI_INIT_TRAP(&ksi);
@@ -314,7 +275,7 @@
if (cause & MIPS_CR_BR_DELAY)
tf->tf_regs[_R_PC] =
- MachEmulateBranch(tf, tf->tf_regs[_R_PC],
+ mips_emul_branch(tf, tf->tf_regs[_R_PC],
PCB_FSR(curpcb), 0);
else
tf->tf_regs[_R_PC] += 4;
@@ -324,7 +285,7 @@
* MIPS2 LL instruction
*/
void
-MachEmulateLWC0(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_lwc0(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -357,7 +318,7 @@
* MIPS2 SC instruction
*/
void
-MachEmulateSWC0(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_swc0(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
uint32_t value;
@@ -408,7 +369,7 @@
}
void
-MachEmulateSpecial(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_special(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
ksiginfo_t ksi;
switch (((InstFmt)inst).RType.func) {
@@ -431,7 +392,7 @@
}
void
-MachEmulateSpecial3(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_special3(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
ksiginfo_t ksi;
switch (((InstFmt)inst).RType.func) {
@@ -463,7 +424,7 @@
#define LWSWC1_MAXLOOP 12
void
-MachEmulateLWC1(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_lwc1(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -526,7 +487,7 @@
}
void
-MachEmulateLDC1(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_ldc1(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -553,7 +514,7 @@
}
void
-MachEmulateSWC1(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_swc1(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -616,7 +577,7 @@
}
void
-MachEmulateSDC1(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_sdc1(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -643,7 +604,7 @@
}
void
-bcemul_lb(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_lb(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -663,17 +624,17 @@
return;
}
- tf->tf_regs[(inst>>16)&0x1F] = (int32_t)x;
+ tf->tf_regs[(inst>>16)&0x1F] = x;
update_pc(tf, cause);
}
void
-bcemul_lbu(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_lbu(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
- uint8_t x;
+ uint8_t x;
offset = inst & 0xFFFF;
vaddr = tf->tf_regs[(inst>>21)&0x1F] + offset;
@@ -689,13 +650,13 @@
return;
}
- tf->tf_regs[(inst>>16)&0x1F] = (mips_ureg_t)x;
+ tf->tf_regs[(inst>>16)&0x1F] = x;
update_pc(tf, cause);
}
void
-bcemul_lh(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_lh(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -721,11 +682,11 @@
}
void
-bcemul_lhu(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_lhu(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
- u_int16_t x;
+ uint16_t x;
offset = inst & 0xFFFF;
vaddr = tf->tf_regs[(inst>>21)&0x1F] + offset;
@@ -747,10 +708,11 @@
}
void
-bcemul_lw(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_lw(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
+ int32_t x;
offset = inst & 0xFFFF;
vaddr = tf->tf_regs[(inst>>21)&0x1F] + offset;
@@ -761,16 +723,18 @@
return;
}
- if (copyin((void *)vaddr, &(tf->tf_regs[(inst>>16)&0x1F]), 4) != 0) {
+ if (copyin((void *)vaddr, &x, 4) != 0) {
send_sigsegv(vaddr, T_TLB_LD_MISS, tf, cause);
return;
}
+ tf->tf_regs[(inst>>16)&0x1F] = x;
+
update_pc(tf, cause);
}
void
-bcemul_lwl(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_lwl(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
uint32_t a, x, shift;
@@ -803,9 +767,9 @@
}
void
-bcemul_lwr(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_lwr(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
- intptr_t vaddr;
+ intptr_t vaddr;
uint32_t a, x, shift;
int16_t offset;
@@ -837,7 +801,33 @@
#if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64)
void
-bcemul_ld(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_lwu(uint32_t inst, struct trapframe *tf, uint32_t cause)
+{
+ intptr_t vaddr;
+ int16_t offset;
+ uint32_t x;
+
+ offset = inst & 0xFFFF;
+ vaddr = tf->tf_regs[(inst>>21)&0x1F] + offset;
+
+ /* segment and alignment check */
+ if (vaddr > VM_MAX_ADDRESS || vaddr & 0x3) {
+ send_sigsegv(vaddr, T_ADDR_ERR_LD, tf, cause);
+ return;
+ }
+
+ if (copyin((void *)vaddr, &x, 4) != 0) {
+ send_sigsegv(vaddr, T_TLB_LD_MISS, tf, cause);
+ return;
+ }
+
+ tf->tf_regs[(inst>>16)&0x1F] = x;
+
+ update_pc(tf, cause);
+}
+
+void
+mips_emul_ld(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -860,7 +850,7 @@
}
void
-bcemul_ldl(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_ldl(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
uint64_t a, x;
@@ -894,7 +884,7 @@
}
void
-bcemul_ldr(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_ldr(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
uint64_t a, x;
@@ -929,7 +919,7 @@
#endif /* defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) */
void
-bcemul_sb(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_sb(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -952,7 +942,7 @@
}
void
-bcemul_sh(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_sh(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -975,7 +965,7 @@
}
void
-bcemul_sw(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_sw(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -998,7 +988,7 @@
}
void
-bcemul_swl(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_swl(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
uint32_t a, x, shift;
@@ -1034,7 +1024,7 @@
}
void
-bcemul_swr(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_swr(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
uint32_t a, x, shift;
@@ -1071,7 +1061,7 @@
#if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64)
void
-bcemul_sd(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_sd(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
int16_t offset;
@@ -1094,7 +1084,7 @@
}
void
-bcemul_sdl(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_sdl(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
uint64_t a, x;
@@ -1131,7 +1121,7 @@
}
void
-bcemul_sdr(uint32_t inst, struct trapframe *tf, uint32_t cause)
+mips_emul_sdr(uint32_t inst, struct trapframe *tf, uint32_t cause)
{
intptr_t vaddr;
uint64_t a, x;
Index: src/sys/arch/mips/mips/mips_fputrap.c
diff -u src/sys/arch/mips/mips/mips_fputrap.c:1.5.66.5 src/sys/arch/mips/mips/mips_fputrap.c:1.5.66.6
--- src/sys/arch/mips/mips/mips_fputrap.c:1.5.66.5 Tue Feb 23 20:33:48 2010
+++ src/sys/arch/mips/mips/mips_fputrap.c Wed Dec 29 00:50:29 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_fputrap.c,v 1.5.66.5 2010/02/23 20:33:48 matt Exp $ */
+/* $NetBSD: mips_fputrap.c,v 1.5.66.6 2010/12/29 00:50:29 matt Exp $ */
/*
* Copyright (c) 2004
@@ -37,12 +37,12 @@
#include <mips/locore.h>
#if defined(FPEMUL) || !defined(NOFPU)
-void mips_fpuexcept(struct lwp *, unsigned int);
-void mips_fpuillinst(struct lwp *, unsigned int, unsigned long);
-static int fpustat2sicode(unsigned int);
+void mips_fpuexcept(struct lwp *, uint32_t);
+void mips_fpuillinst(struct lwp *, uint32_t, vaddr_t);
+static int fpustat2sicode(uint32_t);
void
-mips_fpuexcept(struct lwp *l, unsigned int fpustat)
+mips_fpuexcept(struct lwp *l, uint32_t fpustat)
{
ksiginfo_t ksi;
@@ -54,7 +54,7 @@
}
void
-mips_fpuillinst(struct lwp *l, unsigned int opcode, unsigned long vaddr)
+mips_fpuillinst(struct lwp *l, uint32_t opcode, vaddr_t vaddr)
{
ksiginfo_t ksi;
@@ -66,7 +66,7 @@
(*l->l_proc->p_emul->e_trapsignal)(l, &ksi);
}
-static struct {
+static const struct {
unsigned int bit;
int code;
} fpecodes[] = {
@@ -79,14 +79,14 @@
};
static int
-fpustat2sicode(unsigned int fpustat)
+fpustat2sicode(uint32_t fpustat)
{
- int i;
-
- for (i = 0; i < 6; i++)
+ for (size_t i = 0; i < __arraycount(fpecodes); i++) {
if (fpustat & fpecodes[i].bit)
- return (fpecodes[i].code);
- return (FPE_FLTINV);
+ return fpecodes[i].code;
+ }
+
+ return FPE_FLTINV;
}
#endif /* FPEMUL || !NOFPU */
