Module Name: src
Committed By: mrg
Date: Sun Jan 2 10:43:19 UTC 2011
Modified Files:
src/sys/arch/sparc64/dev: schizo.c schizoreg.h
Log Message:
now that it's optional, kill schizo_pci_find_ino().
prepare to enable the tomatillo iocache.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/sparc64/dev/schizo.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/sparc64/dev/schizoreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/dev/schizo.c
diff -u src/sys/arch/sparc64/dev/schizo.c:1.16 src/sys/arch/sparc64/dev/schizo.c:1.17
--- src/sys/arch/sparc64/dev/schizo.c:1.16 Thu Mar 11 03:54:56 2010
+++ src/sys/arch/sparc64/dev/schizo.c Sun Jan 2 10:43:18 2011
@@ -1,9 +1,10 @@
-/* $NetBSD: schizo.c,v 1.16 2010/03/11 03:54:56 mrg Exp $ */
+/* $NetBSD: schizo.c,v 1.17 2011/01/02 10:43:18 mrg Exp $ */
/* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */
/*
* Copyright (c) 2002 Jason L. Wright (ja...@thought.net)
* Copyright (c) 2003 Henric Jungheim
+ * Copyright (c) 2008, 2009, 2010 Matthew R. Green
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -102,7 +103,6 @@
static int schizo_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
int, int (*)(void *), void *);
-static int schizo_pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *);
static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
bus_size_t, int, bus_dmamap_t *);
@@ -141,6 +141,7 @@
uint64_t reg, eccctrl;
int *busranges = NULL, nranges;
char *str;
+ bool no_sc;
aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr);
str = prom_getpropstring(ma->ma_node, "compatible");
@@ -213,7 +214,10 @@
is = &pbm->sp_is;
pbm->sp_sb.sb_is = is;
- if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) {
+ no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0;
+ if (no_sc)
+ aprint_debug("%s: no streaming buffers\n", sc->sc_dv.dv_xname);
+ else {
vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40];
/*
@@ -227,8 +231,6 @@
bus_space_subregion(pbm->sp_regt, pbm->sp_regh,
offsetof(struct schizo_pbm_regs, strbuf),
sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb);
- } else {
- aprint_debug("%s: no streaming buffers\n", sc->sc_dv.dv_xname);
}
aprint_normal("%s: ", sc->sc_dv.dv_xname);
@@ -297,6 +299,22 @@
schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc,
SCZ_SERR_INO, "safari");
+#if 0
+ if (sc->sc_tomatillo) {
+ /*
+ * We should enable the IOCACHE here.
+ */
+ uint64_t iocache_csr;
+ char bits[128];
+
+ iocache_csr = schizo_pbm_read(pbm, SCZ_PCI_IOCACHE_CSR);
+
+ snprintb(bits, sizeof(bits), TOM_IOCACHE_CSR_BITS, iocache_csr);
+ printf("IOCACHE_CSR=%s\n", bits);
+ printf("IOCACHE_CSR=%" PRIx64 "\n", iocache_csr);
+ }
+#endif
+
config_found(&sc->sc_dv, &pba, schizo_print);
}
@@ -605,7 +623,7 @@
npc->spc_conf_write = schizo_conf_write;
npc->spc_intr_map = schizo_pci_intr_map;
npc->spc_intr_establish = schizo_pci_intr_establish;
- npc->spc_find_ino = schizo_pci_find_ino;
+ npc->spc_find_ino = NULL;
return (npc);
}
@@ -814,54 +832,3 @@
DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie));
return (cookie);
}
-
-static int
-schizo_pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
-{
-#if 0
- struct schizo_pbm *pbm = pa->pa_pc->cookie;
- struct schizo_softc *sc = pbm->sp_sc;
- u_int bus;
- u_int dev;
- u_int pin;
-#endif
-
- DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n",
- PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag),
- (int)PCITAG_DEV(pa->pa_tag),
- (int)PCITAG_FUN(pa->pa_tag)));
- DPRINTF(SDB_INTMAP,
- ("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n",
- pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin));
- DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n",
- PCITAG_NODE(pa->pa_intrtag),
- (int)PCITAG_BUS(pa->pa_intrtag),
- (int)PCITAG_DEV(pa->pa_intrtag),
- (int)PCITAG_FUN(pa->pa_intrtag)));
-
-#if 0
- bus = (pp->pp_id == PSYCHO_PBM_B);
- /*
- * If we are on a ppb, use the devno on the underlying bus when forming
- * the ivec.
- */
- if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0)
- dev = PCITAG_DEV(pa->pa_intrtag);
- else
- dev = pa->pa_device;
- dev--;
-
- if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
- pp->pp_id == PSYCHO_PBM_B)
- dev--;
-
- pin = pa->pa_intrpin - 1;
- DPRINTF(SDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, pin %d\n",
- sc->sc_mode, pp->pp_id, dev, pin));
-
- *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) |
- ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT);
-#endif
-
- return (0);
-}
Index: src/sys/arch/sparc64/dev/schizoreg.h
diff -u src/sys/arch/sparc64/dev/schizoreg.h:1.6 src/sys/arch/sparc64/dev/schizoreg.h:1.7
--- src/sys/arch/sparc64/dev/schizoreg.h:1.6 Sat Feb 13 11:55:48 2010
+++ src/sys/arch/sparc64/dev/schizoreg.h Sun Jan 2 10:43:18 2011
@@ -1,8 +1,9 @@
-/* $NetBSD: schizoreg.h,v 1.6 2010/02/13 11:55:48 nakayama Exp $ */
+/* $NetBSD: schizoreg.h,v 1.7 2011/01/02 10:43:18 mrg Exp $ */
/* $OpenBSD: schizoreg.h,v 1.20 2008/07/12 13:08:04 kettenis Exp $ */
/*
* Copyright (c) 2002 Jason L. Wright (ja...@thought.net)
+ * Copyright (c) 2010 Matthew R. Green
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -129,6 +130,9 @@
#define SCZ_PCI_AFAR 0x02018
#define SCZ_PCI_DIAG 0x02020
#define SCZ_PCI_ESTAR 0x02028
+#define SCZ_PCI_IOCACHE_CSR 0x02248
+#define SCZ_PCI_IOCACHE_TAG_DIAG_BASE 0x02250
+#define SCZ_PCI_IOCACHE_TAG_DATA_BASE 0x02290
#define SCZ_PCI_STRBUF_CTRL 0x02800
#define SCZ_PCI_STRBUF_FLUSH 0x02808
#define SCZ_PCI_STRBUF_FSYNC 0x02810
@@ -251,6 +255,30 @@
#define SCZ_PCIDIAG_I_PIODPAR (1UL << 2UL) /* invert pio data parity */
#define SCZ_PCIDIAG_I_PIOAPAR (1UL << 1UL) /* invert pio addr parity */
+/* Enable prefetch bits */
+#define TOM_IOCACHE_CSR_WRT_PEN (1UL << 19UL) /* for partial line writes */
+#define TOM_IOCACHE_CSR_NCP_RDM (1UL << 18UL) /* memory read multiple (NC) */
+#define TOM_IOCACHE_CSR_NCP_ONE (1UL << 17UL) /* memory read (NC) */
+#define TOM_IOCACHE_CSR_NCP_LINE (1UL << 16UL) /* memory read line (NC) */
+#define TOM_IOCACHE_CSR_PEN_RDM (1UL << 2UL) /* memory read multiple */
+#define TOM_IOCACHE_CSR_PEN_ONE (1UL << 1UL) /* memory read */
+#define TOM_IOCACHE_CSR_PEN_LINE (1UL << 0UL) /* memory read line */
+/* Prefetch lines selection 0x0 = 1, 0x3 = 4 */
+#define TOM_IOCACHE_CSR_PLEN_RDM_MASK 0x000000000000c000UL /* read multiple */
+#define TOM_IOCACHE_CSR_PLEN_RDM_SHIFT 14
+#define TOM_IOCACHE_CSR_PLEN_ONE_MASK 0x0000000000003000UL /* read one */
+#define TOM_IOCACHE_CSR_PLEN_ONE_SHIFT 12
+#define TOM_IOCACHE_CSR_PLEN_LINE_MASK 0x0000000000000c00UL /* read line */
+#define TOM_IOCACHE_CSR_PLEN_LINE_SHIFT 10
+/* Prefetch offset selection 0x00 = 1, 0x7e = 127, 0x7f = invalid */
+#define TOM_IOCACHE_CSR_POFFSET_MASK 0x00000000000003f8UL
+
+#define TOM_IOCACHE_CSR_BITS "\177\020" \
+ "b\19WRT_PEN\0b\18NCP_RDM\0b17NCP_ONE\0b\16NCP_LINE\0" \
+ "f\14\2PLEN_RDM\0f\12\2PEN_ONE\0f\10\2PEN_LINE\0" \
+ "f\3\7POFFSET\0" \
+ "b\2PEN_RDM\0b\1PEN_ONE\0b\0PEN_LINE\0\0"
+
#define TOM_IOMMU_ERR (1UL << 24)
#define TOM_IOMMU_ERR_MASK (3UL << 25)
#define TOM_IOMMU_PROT_ERR (0UL << 25)
