Module Name: src
Committed By: jmcneill
Date: Mon Jan 10 12:23:21 UTC 2011
Modified Files:
src/sys/dev/pci: pcireg.h ppb.c
Log Message:
ppb_fix_pcix changes:
- rename to ppb_fix_pcie
- support version PCI-E 2.0
- print version and device/port type information
- use constants from pcireg.h instead of magic numbers
changes:
ppb2 at pci0 dev 21 function 0: vendor 0x15ad product 0x07a0 (rev. 0x01)
ppb2: unsupported PCI Express version
to:
ppb2 at pci0 dev 21 function 0: vendor 0x15ad product 0x07a0 (rev. 0x01)
ppb2: PCI Express 2.0 <Root Port of PCI-E Root Complex>
To generate a diff of this commit:
cvs rdiff -u -r1.68 -r1.69 src/sys/dev/pci/pcireg.h
cvs rdiff -u -r1.43 -r1.44 src/sys/dev/pci/ppb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.68 src/sys/dev/pci/pcireg.h:1.69
--- src/sys/dev/pci/pcireg.h:1.68 Sat Dec 11 18:17:39 2010
+++ src/sys/dev/pci/pcireg.h Mon Jan 10 12:23:21 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.68 2010/12/11 18:17:39 matt Exp $ */
+/* $NetBSD: pcireg.h,v 1.69 2011/01/10 12:23:21 jmcneill Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -604,6 +604,17 @@
* PCI Express; access via capability pointer.
*/
#define PCI_PCIE_XCAP 0x00
+#define PCI_PCIE_XCAP_VER_MASK 0x000f0000
+#define PCI_PCIE_XCAP_VER_1_0 0x00010000
+#define PCI_PCIE_XCAP_VER_2_0 0x00020000
+#define PCI_PCIE_XCAP_TYPE_MASK 0x00f00000
+#define PCI_PCIE_XCAP_TYPE_PCIE_DEV 0x00000000
+#define PCI_PCIE_XCAP_TYPE_PCI_DEV 0x00100000
+#define PCI_PCIE_XCAP_TYPE_ROOT 0x00400000
+#define PCI_PCIE_XCAP_TYPE_UP 0x00500000
+#define PCI_PCIE_XCAP_TYPE_DOWN 0x00600000
+#define PCI_PCIE_XCAP_TYPE_PCIE2PCI 0x00700000
+#define PCI_PCIE_XCAP_TYPE_PCI2PCIE 0x00800000
#define PCI_PCIE_XCAP_SI 0x01000000
#define PCI_PCIE_DCAP 0x04
#define PCI_PCIE_DCSR 0x08
Index: src/sys/dev/pci/ppb.c
diff -u src/sys/dev/pci/ppb.c:1.43 src/sys/dev/pci/ppb.c:1.44
--- src/sys/dev/pci/ppb.c:1.43 Sat Dec 11 18:25:02 2010
+++ src/sys/dev/pci/ppb.c Mon Jan 10 12:23:21 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: ppb.c,v 1.43 2010/12/11 18:25:02 matt Exp $ */
+/* $NetBSD: ppb.c,v 1.44 2011/01/10 12:23:21 jmcneill Exp $ */
/*
* Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.43 2010/12/11 18:25:02 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.44 2011/01/10 12:23:21 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -43,6 +43,10 @@
#include <dev/pci/ppbreg.h>
#include <dev/pci/pcidevs.h>
+#define PCI_PCIE_SLCSR_NOTIFY_MASK \
+ (PCI_PCIE_SLCSR_ABE | PCI_PCIE_SLCSR_PFE | PCI_PCIE_SLCSR_MSE | \
+ PCI_PCIE_SLCSR_PDE | PCI_PCIE_SLCSR_CCE | PCI_PCIE_SLCSR_HPE)
+
struct ppb_softc {
device_t sc_dev; /* generic device glue */
pci_chipset_tag_t sc_pc; /* our PCI chipset... */
@@ -83,7 +87,7 @@
}
static void
-ppb_fix_pcix(device_t self)
+ppb_fix_pcie(device_t self)
{
struct ppb_softc *sc = device_private(self);
pcireg_t reg;
@@ -93,15 +97,54 @@
&off, ®))
return; /* Not a PCIe device */
- if ((reg & 0x000f0000) != 0x00010000) {
- aprint_normal_dev(self, "unsupported PCI Express version\n");
+ aprint_normal_dev(self, "PCI Express ");
+ switch (reg & PCI_PCIE_XCAP_VER_MASK) {
+ case PCI_PCIE_XCAP_VER_1_0:
+ aprint_normal("1.0");
+ case PCI_PCIE_XCAP_VER_2_0:
+ aprint_normal("2.0");
+ break;
+ default:
+ aprint_normal_dev(self, "version unsupported (0x%x)\n",
+ (reg & PCI_PCIE_XCAP_VER_MASK) >> 16);
return;
}
- reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + 0x18);
- if (reg & 0x003f) {
- aprint_normal_dev(self, "disabling notification events\n");
- reg &= ~0x003f;
- pci_conf_write(sc->sc_pc, sc->sc_tag, off + 0x18, reg);
+ aprint_normal(" <");
+ switch (reg & PCI_PCIE_XCAP_TYPE_MASK) {
+ case PCI_PCIE_XCAP_TYPE_PCIE_DEV:
+ aprint_normal("PCI-E Endpoint device");
+ break;
+ case PCI_PCIE_XCAP_TYPE_PCI_DEV:
+ aprint_normal("Legacy PCI-E Endpoint device");
+ break;
+ case PCI_PCIE_XCAP_TYPE_ROOT:
+ aprint_normal("Root Port of PCI-E Root Complex");
+ break;
+ case PCI_PCIE_XCAP_TYPE_UP:
+ aprint_normal("Upstream Port of PCI-E Switch");
+ break;
+ case PCI_PCIE_XCAP_TYPE_DOWN:
+ aprint_normal("Downstream Port of PCI-E Switch");
+ break;
+ case PCI_PCIE_XCAP_TYPE_PCIE2PCI:
+ aprint_normal("PCI-E to PCI/PCI-X Bridge");
+ break;
+ case PCI_PCIE_XCAP_TYPE_PCI2PCIE:
+ aprint_normal("PCI/PCI-X to PCI-E Bridge");
+ break;
+ default:
+ aprint_normal("Device/Port Type 0x%x",
+ (reg & PCI_PCIE_XCAP_TYPE_MASK) >> 20);
+ break;
+ }
+ aprint_normal(">\n");
+
+ reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCI_PCIE_SLCSR);
+ if (reg & PCI_PCIE_SLCSR_NOTIFY_MASK) {
+ aprint_debug_dev(self, "disabling notification events\n");
+ reg &= ~PCI_PCIE_SLCSR_NOTIFY_MASK;
+ pci_conf_write(sc->sc_pc, sc->sc_tag,
+ off + PCI_PCIE_SLCSR, reg);
}
}
@@ -131,7 +174,7 @@
return;
}
- ppb_fix_pcix(self);
+ ppb_fix_pcie(self);
#if 0
/*
@@ -193,7 +236,7 @@
sc->sc_pciconfext[(off - 0x40)/4]);
}
- ppb_fix_pcix(dv);
+ ppb_fix_pcie(dv);
return true;
}
