Module Name: src
Committed By: phx
Date: Thu Jan 13 21:54:15 UTC 2011
Modified Files:
src/sys/arch/sandpoint/stand/netboot: siisata.c
Log Message:
Configure transfer mode registers to PIO mode. It seems to work without, but
just to be on the safe side.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/sandpoint/stand/netboot/siisata.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sandpoint/stand/netboot/siisata.c
diff -u src/sys/arch/sandpoint/stand/netboot/siisata.c:1.14 src/sys/arch/sandpoint/stand/netboot/siisata.c:1.15
--- src/sys/arch/sandpoint/stand/netboot/siisata.c:1.14 Mon Jan 10 20:13:47 2011
+++ src/sys/arch/sandpoint/stand/netboot/siisata.c Thu Jan 13 21:54:14 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: siisata.c,v 1.14 2011/01/10 20:13:47 phx Exp $ */
+/* $NetBSD: siisata.c,v 1.15 2011/01/13 21:54:14 phx Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
@@ -58,7 +58,7 @@
void *
siisata_init(unsigned tag, void *data)
{
- unsigned val;
+ unsigned idreg;
int nchan, n;
struct dkdev_ata *l;
@@ -67,6 +67,7 @@
l->iobuf = allocaligned(512, 16);
l->tag = tag;
+ idreg = pcicfgread(tag, PCI_ID_REG);
l->bar[0] = pciiobase + (pcicfgread(tag, 0x10) &~ 01);
l->bar[1] = pciiobase + (pcicfgread(tag, 0x14) &~ 01);
l->bar[2] = pciiobase + (pcicfgread(tag, 0x18) &~ 01);
@@ -74,8 +75,7 @@
l->bar[4] = pciiobase + (pcicfgread(tag, 0x20) &~ 01);
l->bar[5] = pcicfgread(tag, 0x24) &~ 0x3ff;
- val = pcicfgread(tag, PCI_ID_REG);
- if ((PCI_PRODUCT(val) & 0xf) == 0x2) {
+ if ((PCI_PRODUCT(idreg) & 0xf) == 0x2) {
/* 3112/3512 */
l->chan[0].cmd = l->bar[0];
l->chan[0].ctl = l->chan[0].alt = l->bar[1] | 02;
@@ -98,6 +98,10 @@
nchan = 4;
}
+ /* configure PIO transfer mode */
+ pcicfgwrite(tag, 0x80, 0x00);
+ pcicfgwrite(tag, 0x84, 0x00);
+
for (n = 0; n < nchan; n++) {
if (satapresense(l, n)) {
/* drive present, now check whether soft reset works */
