Module Name: src Committed By: kiyohara Date: Wed Feb 2 04:29:59 UTC 2011
Modified Files: src/sys/arch/mmeye/dev: mmeyepcmciareg.h Log Message: Indent. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mmeye/dev/mmeyepcmciareg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/mmeye/dev/mmeyepcmciareg.h diff -u src/sys/arch/mmeye/dev/mmeyepcmciareg.h:1.1 src/sys/arch/mmeye/dev/mmeyepcmciareg.h:1.2 --- src/sys/arch/mmeye/dev/mmeyepcmciareg.h:1.1 Sun Mar 24 18:08:46 2002 +++ src/sys/arch/mmeye/dev/mmeyepcmciareg.h Wed Feb 2 04:29:59 2011 @@ -1,4 +1,4 @@ -/* $NetBSD: mmeyepcmciareg.h,v 1.1 2002/03/24 18:08:46 uch Exp $ */ +/* $NetBSD: mmeyepcmciareg.h,v 1.2 2011/02/02 04:29:59 kiyohara Exp $ */ /* * Copyright (c) 1997 Marc Horowitz. All rights reserved. @@ -51,7 +51,7 @@ /* general setup registers */ -#define MMEYEPCMCIA_IDENT 0x00 /* RO */ +#define MMEYEPCMCIA_IDENT 0x00 /* RO */ #define MMEYEPCMCIA_IDENT_IFTYPE_MASK 0xC0 #define MMEYEPCMCIA_IDENT_IFTYPE_IO_ONLY 0x00 #define MMEYEPCMCIA_IDENT_IFTYPE_MEM_ONLY 0x40 @@ -74,10 +74,10 @@ #define MMEYEPCMCIA_IF_STATUS_BATTERY_DEAD2 0x01 #define MMEYEPCMCIA_IF_STATUS_BATTERY_WARNING 0x02 #define MMEYEPCMCIA_IF_STATUS_BATTERY_GOOD 0x03 -#define MMEYEPCMCIA_IF_STATUS_RESET 0x08 -#define MMEYEPCMCIA_IF_STATUS_BUSWIDTH 0x40 +#define MMEYEPCMCIA_IF_STATUS_RESET 0x08 +#define MMEYEPCMCIA_IF_STATUS_BUSWIDTH 0x40 -#define MMEYEPCMCIA_PWRCTL 0x02 /* RW */ +#define MMEYEPCMCIA_PWRCTL 0x02 /* RW */ #define MMEYEPCMCIA_PWRCTL_OE 0x80 /* output enable */ #define MMEYEPCMCIA_PWRCTL_DISABLE_RESETDRV 0x40 #define MMEYEPCMCIA_PWRCTL_AUTOSWITCH_ENABLE 0x20 @@ -104,19 +104,19 @@ #define MMEYEPCMCIA_CSC_BATTDEAD 0x01 /* for memory cards */ #define MMEYEPCMCIA_CSC_RI 0x01 /* for i/o cards */ -#define MMEYEPCMCIA_ADDRWIN_ENABLE 0x06 /* RW */ +#define MMEYEPCMCIA_ADDRWIN_ENABLE 0x06 /* RW */ #define MMEYEPCMCIA_ADDRWIN_ENABLE_IO1 0x80 #define MMEYEPCMCIA_ADDRWIN_ENABLE_IO0 0x40 #define MMEYEPCMCIA_ADDRWIN_ENABLE_MEMCS16 0x20 /* rtfds if you care */ -#define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM4 0x10 -#define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM3 0x08 -#define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM2 0x04 -#define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM1 0x02 -#define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM0 0x01 +#define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM4 0x10 +#define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM3 0x08 +#define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM2 0x04 +#define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM1 0x02 +#define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM0 0x01 #define MMEYEPCMCIA_CARD_DETECT 0x16 /* RW */ #define MMEYEPCMCIA_CARD_DETECT_RESERVED 0xC0 -#define MMEYEPCMCIA_CARD_DETECT_SW_INTR 0x20 +#define MMEYEPCMCIA_CARD_DETECT_SW_INTR 0x20 #define MMEYEPCMCIA_CARD_DETECT_RESUME_ENABLE 0x10 #define MMEYEPCMCIA_CARD_DETECT_GPI_TRANSCTL 0x08 #define MMEYEPCMCIA_CARD_DETECT_GPI_ENABLE 0x04 @@ -125,13 +125,13 @@ /* interrupt registers */ -#define MMEYEPCMCIA_INTR 0x03 /* RW */ +#define MMEYEPCMCIA_INTR 0x03 /* RW */ #define MMEYEPCMCIA_INTR_RI_ENABLE 0x80 #define MMEYEPCMCIA_INTR_RESET 0x40 /* active low (zero) */ #define MMEYEPCMCIA_INTR_CARDTYPE_MASK 0x20 #define MMEYEPCMCIA_INTR_CARDTYPE_IO 0x20 #define MMEYEPCMCIA_INTR_CARDTYPE_MEM 0x00 -#define MMEYEPCMCIA_INTR_ENABLE 0x10 +#define MMEYEPCMCIA_INTR_ENABLE 0x10 #define MMEYEPCMCIA_INTR_IRQ_MASK 0x0F #define MMEYEPCMCIA_INTR_IRQ_SHIFT 0 #define MMEYEPCMCIA_INTR_IRQ_NONE 0x00 @@ -147,13 +147,13 @@ #define MMEYEPCMCIA_INTR_IRQ10 0x0A #define MMEYEPCMCIA_INTR_IRQ11 0x0B #define MMEYEPCMCIA_INTR_IRQ12 0x0C -#define MMEYEPCMCIA_INTR_IRQ_RESERVED13 0x0D +#define MMEYEPCMCIA_INTR_IRQ_RESERVED13 0x0D #define MMEYEPCMCIA_INTR_IRQ14 0x0E #define MMEYEPCMCIA_INTR_IRQ15 0x0F #define MMEYEPCMCIA_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */ -#define MMEYEPCMCIA_CSC_INTR 0x05 /* RW */ +#define MMEYEPCMCIA_CSC_INTR 0x05 /* RW */ #define MMEYEPCMCIA_CSC_INTR_IRQ_MASK 0xF0 #define MMEYEPCMCIA_CSC_INTR_IRQ_SHIFT 4 #define MMEYEPCMCIA_CSC_INTR_IRQ_NONE 0x00 @@ -184,8 +184,8 @@ #define MMEYEPCMCIA_IO_WINS 2 -#define MMEYEPCMCIA_IOCTL 0x07 /* RW */ -#define MMEYEPCMCIA_IOCTL_IO1_WAITSTATE 0x80 +#define MMEYEPCMCIA_IOCTL 0x07 /* RW */ +#define MMEYEPCMCIA_IOCTL_IO1_WAITSTATE 0x80 #define MMEYEPCMCIA_IOCTL_IO1_ZEROWAIT 0x40 #define MMEYEPCMCIA_IOCTL_IO1_IOCS16SRC_MASK 0x20 #define MMEYEPCMCIA_IOCTL_IO1_IOCS16SRC_CARD 0x20 @@ -193,7 +193,7 @@ #define MMEYEPCMCIA_IOCTL_IO1_DATASIZE_MASK 0x10 #define MMEYEPCMCIA_IOCTL_IO1_DATASIZE_16BIT 0x10 #define MMEYEPCMCIA_IOCTL_IO1_DATASIZE_8BIT 0x00 -#define MMEYEPCMCIA_IOCTL_IO0_WAITSTATE 0x08 +#define MMEYEPCMCIA_IOCTL_IO0_WAITSTATE 0x08 #define MMEYEPCMCIA_IOCTL_IO0_ZEROWAIT 0x04 #define MMEYEPCMCIA_IOCTL_IO0_IOCS16SRC_MASK 0x02 #define MMEYEPCMCIA_IOCTL_IO0_IOCS16SRC_CARD 0x02 @@ -229,14 +229,14 @@ #define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT 0x80 #define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT 0x00 #define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_ZEROWAIT 0x40 -#define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK 0x30 +#define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK 0x30 #define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_ADDR_MASK 0x0F #define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK 0xC0 -#define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT0 0x00 -#define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT1 0x40 -#define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT2 0x80 -#define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT3 0xC0 +#define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT0 0x00 +#define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT1 0x40 +#define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT2 0x80 +#define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT3 0xC0 #define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK 0x0F /*