Module Name: src
Committed By: matt
Date: Tue Feb 8 06:16:03 UTC 2011
Modified Files:
src/sys/arch/powerpc/include/booke: openpicreg.h
Log Message:
Add MPC8555/41, MPC8568/67, and P2020 variations.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/powerpc/include/booke/openpicreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/include/booke/openpicreg.h
diff -u src/sys/arch/powerpc/include/booke/openpicreg.h:1.2 src/sys/arch/powerpc/include/booke/openpicreg.h:1.3
--- src/sys/arch/powerpc/include/booke/openpicreg.h:1.2 Tue Jan 18 01:02:54 2011
+++ src/sys/arch/powerpc/include/booke/openpicreg.h Tue Feb 8 06:16:03 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: openpicreg.h,v 1.2 2011/01/18 01:02:54 matt Exp $ */
+/* $NetBSD: openpicreg.h,v 1.3 2011/02/08 06:16:03 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -179,6 +179,22 @@
#define OPENPIC_MSIVPR(n) (0x11c00 + 0x20 * (n))
#define OPENPIC_MSIDR(n) (0x11c10 + 0x20 * (n))
+#define MPC8536_EXTERNALSOURCES 12
+#define MPC8536_ONCHIPSOURCES 64
+#define MPC8536_ONCHIPBITMAP { 0xfe07ffff, 0x05501c00 }
+#define MPC8536_IPISOURCES 8
+#define MPC8536_TIMERSOURCES 8
+#define MPC8536_MISOURCES 4
+#define MPC8536_MSIGROUPSOURCES 8
+#define MPC8536_NCPUS 1
+#define MPC8536_SOURCES /* 104 */ \
+ (MPC8536_EXTERNALSOURCES \
+ + MPC8536_ONCHIPSOURCES \
+ + MPC8536_MSIGROUPSOURCES \
+ + MPC8536_NCPUS*(MPC8536_IPISOURCES \
+ + MPC8536_TIMERSOURCES \
+ + MPC8536_MISOURCES))
+
#define MPC8544_EXTERNALSOURCES 12
#define MPC8544_ONCHIPSOURCES 48
#define MPC8544_ONCHIPBITMAP { 0x3c3fefff, 0x00000000 }
@@ -187,7 +203,7 @@
#define MPC8544_MISOURCES 4
#define MPC8544_MSIGROUPSOURCES 8
#define MPC8544_NCPUS 1
-#define MPC8544_SOURCES \
+#define MPC8544_SOURCES /* 80 */ \
(MPC8544_EXTERNALSOURCES \
+ MPC8544_ONCHIPSOURCES \
+ MPC8544_MSIGROUPSOURCES \
@@ -203,7 +219,7 @@
#define MPC8548_MISOURCES 4
#define MPC8548_MSIGROUPSOURCES 8
#define MPC8548_NCPUS 1
-#define MPC8548_SOURCES \
+#define MPC8548_SOURCES /* 80 */ \
(MPC8548_EXTERNALSOURCES \
+ MPC8548_ONCHIPSOURCES \
+ MPC8548_MSIGROUPSOURCES \
@@ -211,21 +227,37 @@
+ MPC8548_TIMERSOURCES \
+ MPC8548_MISOURCES))
-#define MPC8536_EXTERNALSOURCES 12
-#define MPC8536_ONCHIPSOURCES 64
-#define MPC8536_ONCHIPBITMAP { 0xfe07ffff, 0x05501c00 }
-#define MPC8536_IPISOURCES 8
-#define MPC8536_TIMERSOURCES 8
-#define MPC8536_MISOURCES 4
-#define MPC8536_MSIGROUPSOURCES 8
-#define MPC8536_NCPUS 1
-#define MPC8536_SOURCES \
- (MPC8536_EXTERNALSOURCES \
- + MPC8536_ONCHIPSOURCES \
- + MPC8536_MSIGROUPSOURCES \
- + MPC8536_NCPUS*(MPC8536_IPISOURCES \
- + MPC8536_TIMERSOURCES \
- + MPC8536_MISOURCES))
+#define MPC8555_EXTERNALSOURCES 12
+#define MPC8555_ONCHIPSOURCES 32
+#define MPC8555_ONCHIPBITMAP { 0x7d1c63ff, 0 }
+#define MPC8555_IPISOURCES 4
+#define MPC8555_TIMERSOURCES 4
+#define MPC8555_MISOURCES 4
+#define MPC8555_MSIGROUPSOURCES 0
+#define MPC8555_NCPUS 1
+#define MPC8555_SOURCES /* 56 */ \
+ (MPC8555_EXTERNALSOURCES \
+ + MPC8555_ONCHIPSOURCES \
+ + MPC8555_MSIGROUPSOURCES \
+ + MPC8555_NCPUS*(MPC8555_IPISOURCES \
+ + MPC8555_TIMERSOURCES \
+ + MPC8555_MISOURCES))
+
+#define MPC8568_EXTERNALSOURCES 12
+#define MPC8568_ONCHIPSOURCES 48
+#define MPC8568_ONCHIPBITMAP { 0xfd1c65ff, 0x000b9e7 }
+#define MPC8568_IPISOURCES 4
+#define MPC8568_TIMERSOURCES 4
+#define MPC8568_MISOURCES 4
+#define MPC8568_MSIGROUPSOURCES 8
+#define MPC8568_NCPUS 1
+#define MPC8568_SOURCES /* 80 */ \
+ (MPC8568_EXTERNALSOURCES \
+ + MPC8568_ONCHIPSOURCES \
+ + MPC8568_MSIGROUPSOURCES \
+ + MPC8568_NCPUS*(MPC8568_IPISOURCES \
+ + MPC8568_TIMERSOURCES \
+ + MPC8568_MISOURCES))
#define MPC8572_EXTERNALSOURCES 12
#define MPC8572_ONCHIPSOURCES 64
@@ -235,7 +267,7 @@
#define MPC8572_MISOURCES 4
#define MPC8572_MSIGROUPSOURCES 8
#define MPC8572_NCPUS 2
-#define MPC8572_SOURCES \
+#define MPC8572_SOURCES /* 108 */ \
(MPC8572_EXTERNALSOURCES \
+ MPC8572_ONCHIPSOURCES \
+ MPC8572_MSIGROUPSOURCES \
@@ -243,6 +275,30 @@
+ MPC8572_TIMERSOURCES \
+ MPC8572_MISOURCES))
+#define P20x0_EXTERNALSOURCES 12
+#define P20x0_ONCHIPSOURCES 64
+#define P20x0_ONCHIPBITMAP { 0xdd1ff7ff, 0xf9700de7 }
+#define P20x0_IPISOURCES 4
+#define P20x0_TIMERSOURCES 4
+#define P20x0_MISOURCES 4
+#define P20x0_MSIGROUPSOURCES 8
+#define P2020_NCPUS 2
+#define P2020_SOURCES /* 108 */ \
+ (P20x0_EXTERNALSOURCES \
+ + P20x0_ONCHIPSOURCES \
+ + P20x0_MSIGROUPSOURCES \
+ + P2020_NCPUS*(P20x0_IPISOURCES \
+ + P20x0_TIMERSOURCES \
+ + P20x0_MISOURCES))
+#define P2010_NCPUS 1
+#define P2010_SOURCES \
+ (P20x0_EXTERNALSOURCES \
+ + P20x0_ONCHIPSOURCES \
+ + P20x0_MSIGROUPSOURCES \
+ + P2010_NCPUS*(P20x0_IPISOURCES \
+ + P20x0_TIMERSOURCES \
+ + P20x0_MISOURCES))
+
/*
* Per-CPU Registers
*/
@@ -262,15 +318,13 @@
#define ISOURCE_DMA_CHAN2 5
#define ISOURCE_DMA_CHAN3 6
#define ISOURCE_DMA_CHAN4 7
-#define ISOURCE_PCIEX3_MPC8572 8 /* MPC8572 */
-#define ISOURCE_PCI1 8 /* MPC8548/MPC8544/MPC8536 */
+#define ISOURCE_PCIEX3_MPC8572 8 /* MPC8572/P20x0 */
+#define ISOURCE_PCI1 8 /* MPC8548/MPC8544/MPC8536/MPC8555 */
#define ISOURCE_PCI2 9 /* MPC8548 */
-#define ISOURCE_PCIEX2 9 /* MPC8544/MPC8572/MPC8536 */
+#define ISOURCE_PCIEX2 9 /* MPC8544/MPC8572/MPC8536/P20x0 */
#define ISOURCE_PCIEX 10
-#define ISOURCE_11 11
#define ISOURCE_PCIEX3 11 /* MPC8544/MPC8536 */
-#define ISOURCE_12 12
-#define ISOURCE_USB1 12 /* MPC8536 */
+#define ISOURCE_USB1 12 /* MPC8536/P20x0 */
#define ISOURCE_ETSEC1_TX 13
#define ISOURCE_ETSEC1_RX 14
#define ISOURCE_ETSEC3_TX 15
@@ -279,9 +333,9 @@
#define ISOURCE_ETSEC1_ERR 18
#define ISOURCE_ETSEC2_TX 19 /* !MPC8544/!MPC8536 */
#define ISOURCE_ETSEC2_RX 20 /* !MPC8544/!MPC8536 */
-#define ISOURCE_ETSEC4_TX 21 /* !MPC8544/!MPC8536 */
-#define ISOURCE_ETSEC4_RX 22 /* !MPC8544/!MPC8536 */
-#define ISOURCE_ETSEC4_ERR 23 /* !MPC8544/!MPC8536 */
+#define ISOURCE_ETSEC4_TX 21 /* !MPC8544/!MPC8536/!P20x0 */
+#define ISOURCE_ETSEC4_RX 22 /* !MPC8544/!MPC8536/!P20x0 */
+#define ISOURCE_ETSEC4_ERR 23 /* !MPC8544/!MPC8536/!P20x0 */
#define ISOURCE_ETSEC2_ERR 24 /* !MPC8544/!MPC8536 */
#define ISOURCE_FEC 25 /* MPC8572 */
#define ISOURCE_SATA2 25 /* MPC8536 */
@@ -289,44 +343,44 @@
#define ISOURCE_I2C 27
#define ISOURCE_PERFMON 28
#define ISOURCE_SECURITY1 29
-#define ISOURCE_30 30
+#define ISOURCE_CPM 30 /* MPC8555 */
+#define ISOURCE_QEB_LOW 30 /* MPC8568 */
#define ISOURCE_USB2 30 /* MPC8536 */
#define ISOURCE_GPIO 31 /* MPC8572/!MPC8548 */
-#define ISOURCE_SRIO_EWPU 32 /* !MPC8548 */
-#define ISOURCE_SRIO_ODBELL 33 /* !MPC8548 */
-#define ISOURCE_SRIO_IDBELL 34 /* !MPC8548 */
+#define ISOURCE_QEB_PORT 31 /* MPC8568 */
+#define ISOURCE_SRIO_EWPU 32 /* !MPC8548&!P20x0 */
+#define ISOURCE_SRIO_ODBELL 33 /* !MPC8548&!P20x0 */
+#define ISOURCE_SRIO_IDBELL 34 /* !MPC8548&!P20x0 */
#define ISOURCE_35 35
#define ISOURCE_36 36
-#define ISOURCE_SRIO_OMU1 37 /* !MPC8548 */
-#define ISOURCE_SRIO_IMU1 38
-#define ISOURCE_SRIO_OMU2 39
-#define ISOURCE_SRIO_IMU2 40
+#define ISOURCE_SRIO_OMU1 37 /* !MPC8548&!P20x0 */
+#define ISOURCE_SRIO_IMU1 38 /* !MPC8548&!P20x0 */
+#define ISOURCE_SRIO_OMU2 39 /* !MPC8548&!P20x0 */
+#define ISOURCE_SRIO_IMU2 40 /* !MPC8548&!P20x0 */
#define ISOURCE_PME_GENERAL 41 /* MPC8572 */
-#define ISOURCE_SECURITY2 42 /* MPC8572|MPC8536 */
-#define ISOURCE_43 43
-#define ISOURCE_SPI 43 /* MPC8536 */
-#define ISOURCE_44 44
+#define ISOURCE_SECURITY2 42 /* MPC8572|MPC8536|P20x0 */
+#define ISOURCE_SPI 43 /* MPC8536|P20x0 */
+#define ISOURCE_QEB_IECC 43 /* MPC8568 */
#define ISOURCE_USB3 44 /* MPC8536 */
-#define ISOURCE_TLU1 45 /* MPC8572 */
+#define ISOURCE_QEB_MUECC 44 /* MPC8568 */
+#define ISOURCE_TLU1 45 /* MPC8568/MPC8572 */
#define ISOURCE_46 46
-#define ISOURCE_47 47
+#define ISOURCE_QEB_HIGH 47 /* MPC8548 */
#define ISOURCE_PME_CHAN1 48 /* MPC8572 */
#define ISOURCE_PME_CHAN2 49 /* MPC8572 */
#define ISOURCE_PME_CHAN3 50 /* MPC8572 */
#define ISOURCE_PME_CHAN4 51 /* MPC8572 */
-#define ISOURCE_ETSEC1_PTP 52 /* MPC8572|MPC8536 */
-#define ISOURCE_ETSEC2_PTP 53 /* MPC8572 */
-#define ISOURCE_ETSEC3_PTP 54 /* MPC8572|MPC8536 */
+#define ISOURCE_ETSEC1_PTP 52 /* MPC8572|MPC8536|P20x0 */
+#define ISOURCE_ETSEC2_PTP 53 /* MPC8572|P20x0 */
+#define ISOURCE_ETSEC3_PTP 54 /* MPC8572|MPC8536|P20x0 */
#define ISOURCE_ETSEC4_PTP 55 /* MPC8572 */
-#define ISOURCE_56 56
-#define ISOURCE_ESDHC 56 /* MPC8536 */
+#define ISOURCE_ESDHC 56 /* MPC8536|P20x0 */
#define ISOURCE_57 57
-#define ISOURCE_58 58
#define ISOURCE_SATA1 58 /* MPC8536 */
#define ISOURCE_TLU2 59 /* MPC8572 */
-#define ISOURCE_DMA2_CHAN1 60 /* MPC8572 */
-#define ISOURCE_DMA2_CHAN2 61 /* MPC8572 */
-#define ISOURCE_DMA2_CHAN3 62 /* MPC8572 */
-#define ISOURCE_DMA2_CHAN4 63 /* MPC8572 */
+#define ISOURCE_DMA2_CHAN1 60 /* MPC8572|P20x0 */
+#define ISOURCE_DMA2_CHAN2 61 /* MPC8572|P20x0 */
+#define ISOURCE_DMA2_CHAN3 62 /* MPC8572|P20x0 */
+#define ISOURCE_DMA2_CHAN4 63 /* MPC8572|P20x0 */
#endif /* _POWERPC_BOOKE_OPENPICREG_H_ */
