Module Name: src
Committed By: cegger
Date: Tue Feb 15 10:11:25 UTC 2011
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
update cpuid bits
To generate a diff of this commit:
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.49 src/sys/arch/x86/include/specialreg.h:1.50
--- src/sys/arch/x86/include/specialreg.h:1.49 Tue Oct 12 00:39:08 2010
+++ src/sys/arch/x86/include/specialreg.h Tue Feb 15 10:11:25 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.49 2010/10/12 00:39:08 jakllsch Exp $ */
+/* $NetBSD: specialreg.h,v 1.50 2011/02/15 10:11:25 cegger Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -158,7 +158,7 @@
/* Intel Fn80000001 extended features - %ecx */
#define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/
-#define CPUID_INTEL_FLAGS4 "\20\1LAHF"
+#define CPUID_INTEL_FLAGS4 "\20\1LAHF\02B02\03B03"
/* AMD/VIA Fn80000001 extended features - %edx */
@@ -173,8 +173,9 @@
#define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
#define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
-#define CPUID_EXT_FLAGS "\20\14SYSCALL/SYSRET\24MPC\25NOX\27MXX\32FFXSR" \
- "\33P1GB\34RDTSCP\36LONG\0373DNOW2\0403DNOW"
+#define CPUID_EXT_FLAGS "\20\14SYSCALL/SYSRET\24MPC\25NOX" \
+ "\27MXX\32FFXSR\33P1GB\34RDTSCP" \
+ "\36LONG\0373DNOW2\0403DNOW" \
/* AMD Fn80000001 extended features - %ecx */
#define CPUID_LAHF 0x00000001 /* LAHF/SAHF instruction */
@@ -188,24 +189,40 @@
#define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */
#define CPUID_OSVW 0x00000200 /* OS visible workarounds */
#define CPUID_IBS 0x00000400 /* Instruction Based Sampling */
-#define CPUID_SSE5 0x00000800 /* SSE5 instruction set */
+#define CPUID_XOP 0x00000800 /* XOP instruction set */
#define CPUID_SKINIT 0x00001000 /* SKINIT */
#define CPUID_WDT 0x00002000 /* watchdog timer support */
+#define CPUID_LWP 0x00008000 /* Light Weight Profiling */
+#define CPUID_FMA4 0x00010000 /* FMA4 instructions */
+#define CPUID_NODEID 0x00080000 /* NodeID MSR available*/
+#define CPUID_TBM 0x00200000 /* TBM instructions */
+#define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */
#define CPUID_AMD_FLAGS4 "\20\1LAHF\2CMPLEGACY\3SVM\4EAPIC\5ALTMOVCR0" \
"\6LZCNT\7SSE4A\10MISALIGNSSE" \
"\0113DNOWPREFETCH\12OSVW\13IBS" \
- "\14SSE5\15SKINIT\16WDT"
+ "\14XOP\15SKINIT\16WDT\20LWP" \
+ "\21FMA4\22B17\23B18\24NodeID\25B20\26TBM" \
+ "\27TopoExt\30B23\31B24" \
+ "\32B25\33B25\34B26" \
+ "\35B27\36B28\37B29\40B30\41B31\42B32"
/* AMD Fn8000000a %edx features (SVM features) */
#define CPUID_AMD_SVM_NP 0x00000001
#define CPUID_AMD_SVM_LbrVirt 0x00000002
#define CPUID_AMD_SVM_SVML 0x00000004
#define CPUID_AMD_SVM_NRIPS 0x00000008
-#define CPUID_AMD_SVM_Ssse3Sse5Dis 0x00000200
+#define CPUID_AMD_SVM_TSCRateCtrl 0x00000010
+#define CPUID_AMD_SVM_VMCBCleanBits 0x00000020
+#define CPUID_AMD_SVM_FlushByASID 0x00000040
+#define CPUID_AMD_SVM_DecodeAssist 0x00000080
#define CPUID_AMD_SVM_PauseFilter 0x00000400
#define CPUID_AMD_SVM_FLAGS "\20\1NP\2LbrVirt\3SVML\4NRIPS" \
- "\12Ssse3Sse5Dis\13PauseFilter"
+ "\5TSCRate\6VMCBCleanBits\7FlushByASID" \
+ "\10DecodeAssist\11B08" \
+ "\12B09\13PauseFilter" \
+ "\14B11\15B12" \
+ "\16B13\17B17\20B18\21B19"
/*
* AMD Advanced Power Management
@@ -221,9 +238,10 @@
#define CPUID_APM_HWP 0x00000080 /* HW P-State control */
#define CPUID_APM_TSC 0x00000100 /* TSC invariant */
#define CPUID_APM_CPB 0x00000200 /* Core performance boost */
+#define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */
#define CPUID_APM_FLAGS "\20\1TS\2FID\3VID\4TTP\5HTC\6STC\007100" \
- "\10HWP\11TSC\12CPB"
+ "\10HWP\11TSC\12CPB\13EffFreq\14B11\15B12"
/*
* Centaur Extended Feature flags
@@ -246,6 +264,7 @@
*/
#define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
+#define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */
#define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */
#define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
#define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
@@ -263,13 +282,18 @@
#define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */
#define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */
#define CPUID2_POPCNT 0x00800000 /* popcount instruction available */
+#define CPUID2_AES 0x02000000 /* AES instructions */
+#define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */
+#define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */
+#define CPUID2_AVX 0x10000000 /* AVX instructions */
+#define CPUID2_F16C 0x20000000 /* half precision conversion */
#define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */
-#define CPUID2_FLAGS1 "\20\1SSE3\2B01\3DTES64\4MONITOR\5DS-CPL\6VMX\7SMX" \
+#define CPUID2_FLAGS1 "\20\1SSE3\2PCLMULQDQ\3DTES64\4MONITOR\5DS-CPL\6VMX\7SMX" \
"\10EST\11TM2\12SSSE3\13CID\14B11\15B12\16CX16" \
"\17xTPR\20PDCM\21B16\22B17\23DCA\24SSE41\25SSE42" \
- "\26X2APIC\27MOVBE\30POPCNT\31B24\32B25\33XSAVE" \
- "\34OSXSAVE\35B28\36B29\37B30\40RAZ"
+ "\26X2APIC\27MOVBE\30POPCNT\31B24\32AES\33XSAVE" \
+ "\34OSXSAVE\35AVX\36F16C\37B30\40RAZ"
#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf)
#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf)
