Module Name: src
Committed By: jruoho
Date: Sun Feb 20 13:42:46 UTC 2011
Modified Files:
src/sys/arch/amd64/conf: GENERIC
src/sys/arch/i386/conf: ALL GENERIC
src/sys/arch/x86/conf: files.x86
src/sys/arch/x86/include: cpu.h cpuvar.h
src/sys/arch/x86/x86: coretemp.c cpu.c identcpu.c
Log Message:
Modularize coretemp(4). Ok jmcneill@.
To generate a diff of this commit:
cvs rdiff -u -r1.309 -r1.310 src/sys/arch/amd64/conf/GENERIC
cvs rdiff -u -r1.289 -r1.290 src/sys/arch/i386/conf/ALL
cvs rdiff -u -r1.1018 -r1.1019 src/sys/arch/i386/conf/GENERIC
cvs rdiff -u -r1.58 -r1.59 src/sys/arch/x86/conf/files.x86
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/x86/include/cpu.h
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/x86/include/cpuvar.h
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/x86/x86/coretemp.c
cvs rdiff -u -r1.81 -r1.82 src/sys/arch/x86/x86/cpu.c
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/x86/x86/identcpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/amd64/conf/GENERIC
diff -u src/sys/arch/amd64/conf/GENERIC:1.309 src/sys/arch/amd64/conf/GENERIC:1.310
--- src/sys/arch/amd64/conf/GENERIC:1.309 Sat Feb 19 00:13:55 2011
+++ src/sys/arch/amd64/conf/GENERIC Sun Feb 20 13:42:45 2011
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.309 2011/02/19 00:13:55 jmcneill Exp $
+# $NetBSD: GENERIC,v 1.310 2011/02/20 13:42:45 jruoho Exp $
#
# GENERIC machine description file
#
@@ -22,7 +22,7 @@
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "GENERIC-$Revision: 1.309 $"
+#ident "GENERIC-$Revision: 1.310 $"
maxusers 64 # estimated number of users
@@ -86,6 +86,9 @@
# AMD PowerNow! and Cool`n'Quiet technology
options POWERNOW_K8
+# Intel Core's on-die Thermal sensor
+coretemp* at cpu?
+
# Intel(R) On Demand Clock Modulation (aka ODCM)
# options INTEL_ONDEMAND_CLOCKMOD
@@ -465,9 +468,6 @@
piixpm* at pci? dev ? function ? # PIIX4 compatible PM controller
iic* at piixpm? # SMBus on PIIX4
-# Intel Core's on-die Thermal sensor
-options INTEL_CORETEMP
-
# Intel ICH SMBus controller
ichsmb* at pci? dev ? function ?
iic* at ichsmb?
Index: src/sys/arch/i386/conf/ALL
diff -u src/sys/arch/i386/conf/ALL:1.289 src/sys/arch/i386/conf/ALL:1.290
--- src/sys/arch/i386/conf/ALL:1.289 Sat Feb 19 13:52:27 2011
+++ src/sys/arch/i386/conf/ALL Sun Feb 20 13:42:45 2011
@@ -1,4 +1,4 @@
-# $NetBSD: ALL,v 1.289 2011/02/19 13:52:27 jmcneill Exp $
+# $NetBSD: ALL,v 1.290 2011/02/20 13:42:45 jruoho Exp $
# From NetBSD: GENERIC,v 1.787 2006/10/01 18:37:54 bouyer Exp
#
# ALL machine description file
@@ -17,7 +17,7 @@
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "ALL-$Revision: 1.289 $"
+#ident "ALL-$Revision: 1.290 $"
maxusers 64 # estimated number of users
@@ -42,6 +42,9 @@
# VIA PadLock
padlock0 at cpu0
+# Intel Core's on-die Thermal sensor
+coretemp* at cpu?
+
# Intel(R) On Demand Clock Modulation (aka ODCM)
options INTEL_ONDEMAND_CLOCKMOD
@@ -685,9 +688,6 @@
alipm* at pci? dev ? function ?
iic* at alipm?
-# Intel Core's on-die Thermal sensor
-options INTEL_CORETEMP
-
# VIA C7 Temperature sensor
options VIA_C7TEMP
Index: src/sys/arch/i386/conf/GENERIC
diff -u src/sys/arch/i386/conf/GENERIC:1.1018 src/sys/arch/i386/conf/GENERIC:1.1019
--- src/sys/arch/i386/conf/GENERIC:1.1018 Sat Feb 19 13:52:27 2011
+++ src/sys/arch/i386/conf/GENERIC Sun Feb 20 13:42:45 2011
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.1018 2011/02/19 13:52:27 jmcneill Exp $
+# $NetBSD: GENERIC,v 1.1019 2011/02/20 13:42:45 jruoho Exp $
#
# GENERIC machine description file
#
@@ -22,7 +22,7 @@
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "GENERIC-$Revision: 1.1018 $"
+#ident "GENERIC-$Revision: 1.1019 $"
maxusers 64 # estimated number of users
@@ -47,6 +47,9 @@
# AMD PowerNow! and Cool`n'Quiet technology
options POWERNOW_K8
+# Intel Core's on-die Thermal sensor
+coretemp* at cpu?
+
# VIA PadLock
#padlock0 at cpu0
@@ -643,9 +646,6 @@
alipm* at pci? dev ? function ?
iic* at alipm?
-# Intel Core's on-die Thermal sensor
-options INTEL_CORETEMP
-
# VIA C7 Temperature sensor
options VIA_C7TEMP
Index: src/sys/arch/x86/conf/files.x86
diff -u src/sys/arch/x86/conf/files.x86:1.58 src/sys/arch/x86/conf/files.x86:1.59
--- src/sys/arch/x86/conf/files.x86:1.58 Sat Feb 19 13:52:28 2011
+++ src/sys/arch/x86/conf/files.x86 Sun Feb 20 13:42:45 2011
@@ -1,4 +1,4 @@
-# $NetBSD: files.x86,v 1.58 2011/02/19 13:52:28 jmcneill Exp $
+# $NetBSD: files.x86,v 1.59 2011/02/20 13:42:45 jruoho Exp $
# options for MP configuration through the MP spec
defflag opt_mpbios.h MPBIOS MPVERBOSE MPDEBUG MPBIOS_SCANPCI
@@ -17,9 +17,6 @@
defflag ENHANCED_SPEEDSTEP
defflag opt_est.h EST_FREQ_USERWRITE
-# Intel On Die Temperature sensor
-defflag opt_intel_coretemp.h INTEL_CORETEMP: sysmon_envsys
-
# Pentium 4+ Thermal Monitor ODCM (aka On Demand Clock Modulation)
defflag opt_intel_odcm.h INTEL_ONDEMAND_CLOCKMOD
@@ -44,6 +41,10 @@
attach cpu at cpubus
file arch/x86/x86/cpu.c cpu
+device coretemp: sysmon_envsys
+attach coretemp at cpufeaturebus
+file arch/x86/x86/coretemp.c coretemp
+
device padlock: opencrypto
attach padlock at cpufeaturebus
file arch/x86/x86/via_padlock.c padlock
@@ -107,9 +108,6 @@
file arch/x86/x86/est.c enhanced_speedstep
file arch/x86/x86/intel_busclock.c enhanced_speedstep
-# Intel On-Die Temperature sensor
-file arch/x86/x86/coretemp.c intel_coretemp
-
# VIA C7 Temperature sensor
file arch/x86/x86/viac7temp.c via_c7temp
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.28 src/sys/arch/x86/include/cpu.h:1.29
--- src/sys/arch/x86/include/cpu.h:1.28 Sun Feb 20 12:47:21 2011
+++ src/sys/arch/x86/include/cpu.h Sun Feb 20 13:42:45 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.28 2011/02/20 12:47:21 jmcneill Exp $ */
+/* $NetBSD: cpu.h,v 1.29 2011/02/20 13:42:45 jruoho Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -180,6 +180,7 @@
struct evcnt ci_ipi_events[X86_NIPI];
device_t ci_padlock; /* VIA PadLock private storage */
+ device_t ci_tempsensor; /* Intel coretemp(4) or equivalent */
struct i386tss ci_tss; /* Per-cpu TSS; shared among LWPs */
char ci_iomap[IOMAPSIZE]; /* I/O Bitmap */
Index: src/sys/arch/x86/include/cpuvar.h
diff -u src/sys/arch/x86/include/cpuvar.h:1.39 src/sys/arch/x86/include/cpuvar.h:1.40
--- src/sys/arch/x86/include/cpuvar.h:1.39 Sat Feb 19 13:52:28 2011
+++ src/sys/arch/x86/include/cpuvar.h Sun Feb 20 13:42:45 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuvar.h,v 1.39 2011/02/19 13:52:28 jmcneill Exp $ */
+/* $NetBSD: cpuvar.h,v 1.40 2011/02/20 13:42:45 jruoho Exp $ */
/*-
* Copyright (c) 2000, 2007 The NetBSD Foundation, Inc.
@@ -96,7 +96,6 @@
#include "opt_multiprocessor.h"
#include "opt_enhanced_speedstep.h"
#ifndef XEN
-#include "opt_intel_coretemp.h"
#include "opt_intel_odcm.h"
#include "opt_via_c7temp.h"
#endif
@@ -129,10 +128,6 @@
void viac7temp_register(struct cpu_info *);
#endif
-#ifdef INTEL_CORETEMP
-void coretemp_register(struct cpu_info *);
-#endif
-
#ifdef INTEL_ONDEMAND_CLOCKMOD
void clockmod_init(void);
#endif
Index: src/sys/arch/x86/x86/coretemp.c
diff -u src/sys/arch/x86/x86/coretemp.c:1.16 src/sys/arch/x86/x86/coretemp.c:1.17
--- src/sys/arch/x86/x86/coretemp.c:1.16 Wed Aug 25 05:07:43 2010
+++ src/sys/arch/x86/x86/coretemp.c Sun Feb 20 13:42:46 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: coretemp.c,v 1.16 2010/08/25 05:07:43 jruoho Exp $ */
+/* $NetBSD: coretemp.c,v 1.17 2011/02/20 13:42:46 jruoho Exp $ */
/*-
* Copyright (c) 2007 Juan Romero Pardines.
@@ -36,81 +36,170 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.16 2010/08/25 05:07:43 jruoho Exp $");
+__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.17 2011/02/20 13:42:46 jruoho Exp $");
#include <sys/param.h>
#include <sys/device.h>
-#include <sys/kmem.h>
-#include <sys/xcall.h>
#include <sys/cpu.h>
+#include <sys/module.h>
+#include <sys/xcall.h>
#include <dev/sysmon/sysmonvar.h>
#include <machine/cpuvar.h>
-#include <machine/specialreg.h>
#include <machine/cpufunc.h>
+#include <machine/cputypes.h>
+#include <machine/specialreg.h>
+
+static int coretemp_match(device_t, cfdata_t, void *);
+static void coretemp_attach(device_t, device_t, void *);
+static int coretemp_detach(device_t, int);
+static int coretemp_quirks(struct cpu_info *);
+static void coretemp_ext_config(device_t);
+static void coretemp_refresh(struct sysmon_envsys *, envsys_data_t *);
+static void coretemp_refresh_xcall(void *, void *);
struct coretemp_softc {
+ device_t sc_dev;
struct cpu_info *sc_ci;
- struct sysmon_envsys *sc_sme;
- envsys_data_t sc_sensor;
- char sc_dvname[32];
- int sc_tjmax;
+ struct sysmon_envsys *sc_sme;
+ envsys_data_t sc_sensor;
+ int sc_tjmax;
};
-static void coretemp_refresh(struct sysmon_envsys *, envsys_data_t *);
-static void coretemp_refresh_xcall(void *, void *);
+CFATTACH_DECL_NEW(coretemp, sizeof(struct coretemp_softc),
+ coretemp_match, coretemp_attach, coretemp_detach, NULL);
-void
-coretemp_register(struct cpu_info *ci)
+static int
+coretemp_match(device_t parent, cfdata_t cf, void *aux)
{
- struct coretemp_softc *sc;
+ struct cpufeature_attach_args *cfaa = aux;
+ struct cpu_info *ci = cfaa->ci;
uint32_t regs[4];
- uint64_t msr;
- int cpumodel, cpuextmodel, cpumask;
- /*
- * Don't attach on anything but the first SMT ID.
- */
- if (ci->ci_smt_id != 0)
- return;
+ if (strcmp(cfaa->name, "coretemp") != 0)
+ return 0;
+
+ if (cpu_vendor != CPUVENDOR_INTEL || cpuid_level < 0x06)
+ return 0;
/*
- * CPUID 0x06 returns 1 if the processor has on-die thermal
- * sensors. EBX[0:3] contains the number of sensors.
+ * CPUID 0x06 returns 1 if the processor
+ * has on-die thermal sensors. EBX[0:3]
+ * contains the number of sensors.
*/
x86_cpuid(0x06, regs);
+
if ((regs[0] & CPUID_DSPM_DTS) == 0)
- return;
+ return 0;
+
+ return coretemp_quirks(ci);
+}
+
+static void
+coretemp_attach(device_t parent, device_t self, void *aux)
+{
+ struct coretemp_softc *sc = device_private(self);
+ struct cpufeature_attach_args *cfaa = aux;
+ struct cpu_info *ci = cfaa->ci;
+
+ sc->sc_ci = ci;
+ sc->sc_dev = self;
+
+ aprint_naive("\n");
+ aprint_normal(": Intel on-die thermal sensor\n");
+
+ sc->sc_sensor.units = ENVSYS_STEMP;
+ sc->sc_sensor.flags = ENVSYS_FMONCRITICAL;
+
+ (void)pmf_device_register(self, NULL, NULL);
+ (void)snprintf(sc->sc_sensor.desc, sizeof(sc->sc_sensor.desc),
+ "%s temperature", device_xname(ci->ci_dev));
+
+ sc->sc_sme = sysmon_envsys_create();
+
+ if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor) != 0)
+ goto fail;
+
+ sc->sc_sme->sme_cookie = sc;
+ sc->sc_sme->sme_name = device_xname(self);
+ sc->sc_sme->sme_refresh = coretemp_refresh;
+
+ if (sysmon_envsys_register(sc->sc_sme) != 0)
+ goto fail;
+
+ coretemp_ext_config(self);
+
+ return;
+
+fail:
+ sysmon_envsys_destroy(sc->sc_sme);
+ sc->sc_sme = NULL;
+}
+
+static int
+coretemp_detach(device_t self, int flags)
+{
+ struct coretemp_softc *sc = device_private(self);
+
+ if (sc->sc_sme != NULL)
+ sysmon_envsys_unregister(sc->sc_sme);
+
+ return 0;
+}
+
+static int
+coretemp_quirks(struct cpu_info *ci)
+{
+ uint32_t mask, model;
+ uint64_t msr;
+
+ mask = ci->ci_signature & 0x0F;
+ model = CPUID2MODEL(ci->ci_signature);
+
+ /*
+ * Check if the MSR contains thermal
+ * reading valid bit, this avoid false
+ * positives on systems that fake up
+ * a compatible CPU that doesn't have
+ * access to these MSRs; such as VMWare.
+ */
+ msr = rdmsr(MSR_THERM_STATUS);
- sc = kmem_zalloc(sizeof(struct coretemp_softc), KM_NOSLEEP);
- if (!sc)
- return;
-
- (void)snprintf(sc->sc_dvname, sizeof(sc->sc_dvname), "coretemp%d",
- (int)device_unit(ci->ci_dev));
- cpumodel = CPUID2MODEL(ci->ci_signature);
- /* extended model */
- cpuextmodel = CPUID2EXTMODEL(ci->ci_signature);
- cpumask = ci->ci_signature & 15;
-
- /*
- * Check for errata AE18.
- * "Processor Digital Thermal Sensor (DTS) Readout stops
- * updating upon returning from C3/C4 state."
+ if ((msr & __BIT(31)) == 0)
+ return 0;
+
+ /*
+ * Check for errata AE18, "Processor Digital
+ * Thermal Sensor (DTS) Readout stops updating
+ * upon returning from C3/C4 state".
*
* Adapted from the Linux coretemp driver.
*/
- if (cpumodel == 0xe && cpumask < 0xc) {
+ if (model == 0x0E && mask < 0x0C) {
+
msr = rdmsr(MSR_BIOS_SIGN);
msr = msr >> 32;
- if (msr < 0x39) {
- aprint_debug("%s: not supported (Intel errata AE18), "
- "try updating your BIOS\n", sc->sc_dvname);
- goto bad;
- }
+
+ if (msr < 0x39)
+ return 0;
}
+ return 1;
+}
+
+void
+coretemp_ext_config(device_t self)
+{
+ struct coretemp_softc *sc = device_private(self);
+ struct cpu_info *ci = sc->sc_ci;
+ uint32_t emodel, mask, model;
+ uint64_t msr;
+
+ mask = ci->ci_signature & 0x0F;
+ model = CPUID2MODEL(ci->ci_signature);
+ emodel = CPUID2EXTMODEL(ci->ci_signature);
+
/*
* On some Core 2 CPUs, there's an undocumented MSR that
* can tell us if Tj(max) is 100 or 85.
@@ -121,73 +210,31 @@
* MSR_IA32_EXT_CONFIG is NOT safe on all CPUs
*/
sc->sc_tjmax = 100;
- if ((cpumodel == 0xf && cpumask >= 2) ||
- (cpumodel == 0xe && cpuextmodel != 1)) {
- msr = rdmsr(MSR_IA32_EXT_CONFIG);
- if (msr & (1 << 30))
- sc->sc_tjmax = 85;
- }
- /*
- * Check if the MSR contains thermal reading valid bit, this
- * avoid false positives on systems that fake up a compatible
- * CPU that doesn't have access to these MSRs; such as VMWare.
- */
- msr = rdmsr(MSR_THERM_STATUS);
- if ((msr & __BIT(31)) == 0)
- goto bad;
-
- sc->sc_ci = ci;
+ if ((model == 0x0F && mask >= 2) || (model == 0x0E && emodel != 1)) {
- /*
- * Only a temperature sensor and monitor for a critical state.
- */
- sc->sc_sensor.units = ENVSYS_STEMP;
- sc->sc_sensor.flags = ENVSYS_FMONCRITICAL;
- (void)snprintf(sc->sc_sensor.desc, sizeof(sc->sc_sensor.desc),
- "%s temperature", device_xname(ci->ci_dev));
-
- sc->sc_sme = sysmon_envsys_create();
- if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) {
- sysmon_envsys_destroy(sc->sc_sme);
- goto bad;
- }
-
- /*
- * Hook into the system monitor.
- */
- sc->sc_sme->sme_name = sc->sc_dvname;
- sc->sc_sme->sme_cookie = sc;
- sc->sc_sme->sme_refresh = coretemp_refresh;
+ msr = rdmsr(MSR_IA32_EXT_CONFIG);
- if (sysmon_envsys_register(sc->sc_sme)) {
- aprint_error("%s: unable to register with sysmon\n",
- sc->sc_dvname);
- sysmon_envsys_destroy(sc->sc_sme);
- goto bad;
+ if (msr & (1 << 30))
+ sc->sc_tjmax = 85;
}
-
- return;
-
-bad:
- kmem_free(sc, sizeof(struct coretemp_softc));
}
static void
coretemp_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
{
struct coretemp_softc *sc = sme->sme_cookie;
- uint64_t where;
+ uint64_t xc;
- where = xc_unicast(0, coretemp_refresh_xcall, sc, edata, sc->sc_ci);
- xc_wait(where);
+ xc = xc_unicast(0, coretemp_refresh_xcall, sc, edata, sc->sc_ci);
+ xc_wait(xc);
}
static void
coretemp_refresh_xcall(void *arg0, void *arg1)
{
- struct coretemp_softc *sc = (struct coretemp_softc *)arg0;
- envsys_data_t *edata = (envsys_data_t *)arg1;
+ struct coretemp_softc *sc = arg0;
+ envsys_data_t *edata = arg1;
uint64_t msr;
/*
@@ -205,17 +252,17 @@
/*
* Check for Thermal Status and Thermal Status Log.
*/
- if ((msr & 0x3) == 0x3)
- aprint_debug("%s: PROCHOT asserted\n", sc->sc_dvname);
+ if ((msr & 0x03) == 0x03)
+ aprint_debug_dev(sc->sc_dev, "PROCHOT asserted\n");
/*
- * Bit 31 contains "Reading valid"
+ * Bit 31 contains "Reading valid".
*/
- if (((msr >> 31) & 0x1) == 1) {
+ if (((msr >> 31) & 0x01) == 1) {
/*
* Starting on bit 16 and ending on bit 22.
*/
- edata->value_cur = sc->sc_tjmax - ((msr >> 16) & 0x7f);
+ edata->value_cur = sc->sc_tjmax - ((msr >> 16) & 0x7F);
/*
* Convert to mK.
*/
@@ -236,6 +283,35 @@
* If we reach a critical level, send a critical event to
* powerd(8) (if running).
*/
- if (((msr >> 4) & 0x3) == 0x3)
+ if (((msr >> 4) & 0x03) == 0x03)
edata->state = ENVSYS_SCRITICAL;
}
+
+MODULE(MODULE_CLASS_DRIVER, coretemp, NULL);
+
+#ifdef _MODULE
+#include "ioconf.c"
+#endif
+
+static int
+coretemp_modcmd(modcmd_t cmd, void *aux)
+{
+ int error = 0;
+
+ switch (cmd) {
+ case MODULE_CMD_INIT:
+#ifdef _MODULE
+ error = config_init_component(cfdriver_ioconf_coretemp,
+ cfattach_ioconf_coretemp, cfdata_ioconf_coretemp);
+#endif
+ return error;
+ case MODULE_CMD_FINI:
+#ifdef _MODULE
+ error = config_fini_component(cfdriver_ioconf_coretemp,
+ cfattach_ioconf_coretemp, cfdata_ioconf_coretemp);
+#endif
+ return error;
+ default:
+ return ENOTTY;
+ }
+}
Index: src/sys/arch/x86/x86/cpu.c
diff -u src/sys/arch/x86/x86/cpu.c:1.81 src/sys/arch/x86/x86/cpu.c:1.82
--- src/sys/arch/x86/x86/cpu.c:1.81 Sat Feb 19 13:52:28 2011
+++ src/sys/arch/x86/x86/cpu.c Sun Feb 20 13:42:46 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.81 2011/02/19 13:52:28 jmcneill Exp $ */
+/* $NetBSD: cpu.c,v 1.82 2011/02/20 13:42:46 jruoho Exp $ */
/*-
* Copyright (c) 2000, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -62,7 +62,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.81 2011/02/19 13:52:28 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.82 2011/02/20 13:42:46 jruoho Exp $");
#include "opt_ddb.h"
#include "opt_mpbios.h" /* for MPDEBUG */
@@ -463,11 +463,18 @@
cfaa.ci = ci;
if (ifattr_match(ifattr, "cpufeaturebus")) {
+
if (ci->ci_padlock == NULL) {
cfaa.name = "padlock";
ci->ci_padlock = config_found_ia(self,
"cpufeaturebus", &cfaa, NULL);
}
+
+ if (ci->ci_tempsensor == NULL) {
+ cfaa.name = "coretemp";
+ ci->ci_tempsensor = config_found_ia(self,
+ "cpufeaturebus", &cfaa, NULL);
+ }
}
return 0;
@@ -479,6 +486,9 @@
struct cpu_softc *sc = device_private(self);
struct cpu_info *ci = sc->sc_info;
+ if (ci->ci_tempsensor == child)
+ ci->ci_tempsensor = NULL;
+
if (ci->ci_padlock == child)
ci->ci_padlock = NULL;
}
Index: src/sys/arch/x86/x86/identcpu.c
diff -u src/sys/arch/x86/x86/identcpu.c:1.23 src/sys/arch/x86/x86/identcpu.c:1.24
--- src/sys/arch/x86/x86/identcpu.c:1.23 Sat Feb 19 13:52:28 2011
+++ src/sys/arch/x86/x86/identcpu.c Sun Feb 20 13:42:46 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu.c,v 1.23 2011/02/19 13:52:28 jmcneill Exp $ */
+/* $NetBSD: identcpu.c,v 1.24 2011/02/20 13:42:46 jruoho Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,11 +30,10 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.23 2011/02/19 13:52:28 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.24 2011/02/20 13:42:46 jruoho Exp $");
#include "opt_enhanced_speedstep.h"
#include "opt_intel_odcm.h"
-#include "opt_intel_coretemp.h"
#include "opt_via_c7temp.h"
#include "opt_powernow_k8.h"
#include "opt_xen.h"
@@ -810,11 +809,6 @@
}
#endif /* ENHANCED_SPEEDSTEP */
-#ifdef INTEL_CORETEMP
- if (cpu_vendor == CPUVENDOR_INTEL && cpuid_level >= 0x06)
- coretemp_register(ci);
-#endif
-
#ifdef VIA_C7TEMP
if (cpu_vendor == CPUVENDOR_IDT &&
CPUID2FAMILY(ci->ci_signature) == 6 &&
