Module Name: src
Committed By: matt
Date: Tue Feb 22 08:20:20 UTC 2011
Modified Files:
src/sys/arch/emips/conf: files.emips
src/sys/arch/emips/emips: autoconf.c bus_dma.c cpu.c interrupt.c
machdep.c xilinx_ml40x.c xs_bee3.c
src/sys/arch/emips/include: intr.h sysconf.h
Log Message:
Bring emips forward to the new mips world order.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/emips/conf/files.emips
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/emips/emips/autoconf.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/emips/emips/bus_dma.c \
src/sys/arch/emips/emips/cpu.c src/sys/arch/emips/emips/interrupt.c \
src/sys/arch/emips/emips/xilinx_ml40x.c \
src/sys/arch/emips/emips/xs_bee3.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/emips/emips/machdep.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/emips/include/intr.h \
src/sys/arch/emips/include/sysconf.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/emips/conf/files.emips
diff -u src/sys/arch/emips/conf/files.emips:1.1 src/sys/arch/emips/conf/files.emips:1.2
--- src/sys/arch/emips/conf/files.emips:1.1 Wed Jan 26 01:18:50 2011
+++ src/sys/arch/emips/conf/files.emips Tue Feb 22 08:20:20 2011
@@ -1,4 +1,4 @@
-# $NetBSD: files.emips,v 1.1 2011/01/26 01:18:50 pooka Exp $
+# $NetBSD: files.emips,v 1.2 2011/02/22 08:20:20 matt Exp $
# eMIPS-specific configuration info
# maxpartitions must be first item in files.${ARCH}.
@@ -98,8 +98,6 @@
file common/bus_dma/bus_dmamem_common.c
-file arch/mips/mips/softintr.c
-
#
# Workstation console devices
#
Index: src/sys/arch/emips/emips/autoconf.c
diff -u src/sys/arch/emips/emips/autoconf.c:1.2 src/sys/arch/emips/emips/autoconf.c:1.3
--- src/sys/arch/emips/emips/autoconf.c:1.2 Tue Feb 8 20:20:11 2011
+++ src/sys/arch/emips/emips/autoconf.c Tue Feb 22 08:20:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.2 2011/02/08 20:20:11 rmind Exp $ */
+/* $NetBSD: autoconf.c,v 1.3 2011/02/22 08:20:20 matt Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -39,7 +39,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.2 2011/02/08 20:20:11 rmind Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.3 2011/02/22 08:20:20 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -74,7 +74,7 @@
(*platform.bus_reset)();
/* Configuration is finished, turn on interrupts. */
- _splnone(); /* enable all source forcing SOFT_INTs cleared */
+ spl0(); /* enable all source forcing SOFT_INTs cleared */
}
/*
Index: src/sys/arch/emips/emips/bus_dma.c
diff -u src/sys/arch/emips/emips/bus_dma.c:1.1 src/sys/arch/emips/emips/bus_dma.c:1.2
--- src/sys/arch/emips/emips/bus_dma.c:1.1 Wed Jan 26 01:18:50 2011
+++ src/sys/arch/emips/emips/bus_dma.c Tue Feb 22 08:20:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma.c,v 1.1 2011/01/26 01:18:50 pooka Exp $ */
+/* $NetBSD: bus_dma.c,v 1.2 2011/02/22 08:20:20 matt Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.1 2011/01/26 01:18:50 pooka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.2 2011/02/22 08:20:20 matt Exp $");
#include "opt_cputype.h"
@@ -470,7 +470,7 @@
* NOTE: Even though this is `wbinv_all', since the cache is
* write-though, it just invalidates it.
*/
- if (len >= mips_pdcache_size) {
+ if (len >= mips_cache_info.mci_pdcache_size) {
mips_dcache_wbinv_all();
return;
}
@@ -658,12 +658,10 @@
bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs,
int flags)
{
- extern paddr_t avail_start, avail_end; /* XXX */
-
return (_bus_dmamem_alloc_range_common(t, size, alignment, boundary,
segs, nsegs, rsegs, flags,
- avail_start /*low*/,
- avail_end - PAGE_SIZE /*high*/));
+ mips_avail_start /*low*/,
+ mips_avail_end - PAGE_SIZE /*high*/));
}
/*
Index: src/sys/arch/emips/emips/cpu.c
diff -u src/sys/arch/emips/emips/cpu.c:1.1 src/sys/arch/emips/emips/cpu.c:1.2
--- src/sys/arch/emips/emips/cpu.c:1.1 Wed Jan 26 01:18:50 2011
+++ src/sys/arch/emips/emips/cpu.c Tue Feb 22 08:20:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.1 2011/01/26 01:18:50 pooka Exp $ */
+/* $NetBSD: cpu.c,v 1.2 2011/02/22 08:20:20 matt Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@@ -28,7 +28,9 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.1 2011/01/26 01:18:50 pooka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.2 2011/02/22 08:20:20 matt Exp $");
+
+#include "ioconf.h"
#include <sys/param.h>
#include <sys/device.h>
@@ -38,18 +40,14 @@
#include <machine/autoconf.h>
-static int cpumatch __P((struct device *, struct cfdata *, void *));
-static void cpuattach __P((struct device *, struct device *, void *));
+static int cpumatch(device_t, cfdata_t, void *);
+static void cpuattach(device_t, device_t, void *);
-CFATTACH_DECL(cpu, sizeof (struct device),
+CFATTACH_DECL_NEW(cpu, 0,
cpumatch, cpuattach, NULL, NULL);
-extern struct cfdriver cpu_cd;
static int
-cpumatch(parent, cf, aux)
- struct device *parent;
- struct cfdata *cf;
- void *aux;
+cpumatch(device_t parent, cfdata_t cf, void *aux)
{
struct mainbus_attach_args *ma = aux;
@@ -61,11 +59,9 @@
}
static void
-cpuattach(parent, dev, aux)
- struct device *parent, *dev;
- void *aux;
+cpuattach(device_t parent, device_t self, void *aux)
{
printf(": ");
- cpu_identify();
+ cpu_identify(self);
}
Index: src/sys/arch/emips/emips/interrupt.c
diff -u src/sys/arch/emips/emips/interrupt.c:1.1 src/sys/arch/emips/emips/interrupt.c:1.2
--- src/sys/arch/emips/emips/interrupt.c:1.1 Wed Jan 26 01:18:50 2011
+++ src/sys/arch/emips/emips/interrupt.c Tue Feb 22 08:20:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.1 2011/01/26 01:18:50 pooka Exp $ */
+/* $NetBSD: interrupt.c,v 1.2 2011/02/22 08:20:20 matt Exp $ */
/*-
* Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.1 2011/01/26 01:18:50 pooka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.2 2011/02/22 08:20:20 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -41,6 +41,7 @@
#include <mips/psl.h>
+#include <machine/locore.h>
#include <machine/autoconf.h>
#include <machine/sysconf.h>
#include <machine/intr.h>
@@ -55,8 +56,6 @@
struct evcnt emips_memerr_evcnt =
EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "memerr", "intr");
-extern void MachFPInterrupt(unsigned, unsigned, unsigned, struct frame *);
-
static const char * const intrnames[MAX_DEV_NCOOKIES] = {
"int-0", "int-1", "int-2", "int-3", "int-4",
"int-5", "int-6", "int-7", "int-8", "int-9",
@@ -73,29 +72,27 @@
int i;
if (phase == 0) {
- for (i = 0; i < MAX_DEV_NCOOKIES; i++)
+ for (i = 0; i < MAX_DEV_NCOOKIES; i++) {
evcnt_attach_dynamic(&intrtab[i].ih_count,
EVCNT_TYPE_INTR, NULL, "emips", intrnames[i]);
+ }
return;
}
if (phase == 1) {
/* I am trying to make this standard so its here. Bah. */
- struct mips1_tlb {
- u_int32_t tlb_hi;
- u_int32_t tlb_lo;
- } tlb;
- void mips1_TLBWrite(int, struct mips1_tlb *);
+ struct tlbmask tlb;
/* This is ugly but efficient. Sigh. */
#define TheAic ((struct _Aic *)INTERRUPT_CONTROLLER_DEFAULT_ADDRESS)
tlb.tlb_hi = INTERRUPT_CONTROLLER_DEFAULT_ADDRESS;
- tlb.tlb_lo = INTERRUPT_CONTROLLER_DEFAULT_ADDRESS | 0xf02;
- mips1_TLBWrite(4, &tlb);
+ tlb.tlb_lo0 = INTERRUPT_CONTROLLER_DEFAULT_ADDRESS | 0xf02;
+ tlb_write_indexed(4, &tlb);
+
tlb.tlb_hi = TIMER_DEFAULT_ADDRESS;
- tlb.tlb_lo = TIMER_DEFAULT_ADDRESS | 0xf02;
- mips1_TLBWrite(5, &tlb);
+ tlb.tlb_lo0 = TIMER_DEFAULT_ADDRESS | 0xf02;
+ tlb_write_indexed(5, &tlb);
}
}
@@ -103,49 +100,29 @@
* emips uses one line for all I/O interrupts (0x8000).
*/
void
-cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+cpu_intr(int ppl, uint32_t status, vaddr_t pc)
{
+ uint32_t ipending;
+ int ipl;
curcpu()->ci_data.cpu_nintr++;
- /* device interrupts */
- if (ipending & MIPS_INT_MASK_5) {
- (*platform.iointr)(status, cause, pc, ipending);
+ while (ppl < (ipl = splintr(&ipending))) {
+ splx(ipl);
+ /* device interrupts */
+ if (ipending & MIPS_INT_MASK_5) {
+ (*platform.iointr)(status, pc, ipending);
+ }
+ (void)splhigh();
}
-
-#ifdef notyet
- ipending &= (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0);
- if (ipending == 0)
- return;
-
- _clrsoftintr(ipending);
- mips_softint_dispatch(ipending);
-#endif
-}
-
-/* Rightmost 1. BUGBUG optimize in assembly
- */
-static int __inline Rightmost1(uint32_t Val);
-
-static int __inline Rightmost1(uint32_t Val)
-{
- uint32_t Mask;
-
- Mask = Val & -Val;
- return ((Mask & 0xFFFF0000)!=0) << 4
- | ((Mask & 0xFF00FF00)!=0) << 3
- | ((Mask & 0xF0F0F0F0)!=0) << 2
- | ((Mask & 0xCCCCCCCC)!=0) << 1
- | ((Mask & 0xAAAAAAAA)!=0);
}
/*
* Interrupt dispatcher for standard AIC-style interrupt controller
*/
void
-emips_aic_intr(unsigned status, unsigned cause, unsigned pc, unsigned ipending)
+emips_aic_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
{
- int index;
struct clockframe cf;
cf.pc = pc;
@@ -155,15 +132,12 @@
while (ipending) {
/* Take one (most likely, the only one) */
- index = Rightmost1(ipending);
- ipending = ipending & ~(1 << index);
+ int index = ffs(ipending) - 1;
+ ipending &= ~(1 << index);
intrtab[index].ih_count.ev_count++;
(*intrtab[index].ih_func)(intrtab[index].ih_arg, &cf);
}
-
- /* Not so sure about this. Why dont we just return and reload status? */
- _splset(MIPS_SR_INT_IE | (status & ~(cause & MIPS_HARD_INT_MASK)));
}
@@ -186,12 +160,3 @@
/* Third, enable and done. */
TheAic->IrqEnable = 1 << index;
}
-
-const int *ipl2spl_table;
-
-ipl_cookie_t
-makeiplcookie(ipl_t ipl)
-{
-
- return (ipl_cookie_t){._spl = ipl2spl_table[ipl]};
-}
Index: src/sys/arch/emips/emips/xilinx_ml40x.c
diff -u src/sys/arch/emips/emips/xilinx_ml40x.c:1.1 src/sys/arch/emips/emips/xilinx_ml40x.c:1.2
--- src/sys/arch/emips/emips/xilinx_ml40x.c:1.1 Wed Jan 26 01:18:51 2011
+++ src/sys/arch/emips/emips/xilinx_ml40x.c Tue Feb 22 08:20:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: xilinx_ml40x.c,v 1.1 2011/01/26 01:18:51 pooka Exp $ */
+/* $NetBSD: xilinx_ml40x.c,v 1.2 2011/02/22 08:20:20 matt Exp $ */
/*-
* Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -31,15 +31,20 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: xilinx_ml40x.c,v 1.1 2011/01/26 01:18:51 pooka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: xilinx_ml40x.c,v 1.2 2011/02/22 08:20:20 matt Exp $");
+
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
+#include <uvm/uvm_extern.h>
+
#include <machine/cpu.h>
#include <machine/intr.h>
#include <machine/sysconf.h>
+#include <machine/locore.h>
#include <emips/emips/machdep.h>
#include <emips/emips/cons.h>
@@ -53,7 +58,7 @@
#if 0
#define NOINTS (MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
#else
-#define NOINTS MIPS_SPLHIGH
+#define NOINTS MIPS_INT_MASK
#endif
/* BUGBUG Rewrite this to go off to the interrupt controller masks */
@@ -66,13 +71,18 @@
splvec.splstatclock = MIPS_SPL_0_1_2_3; //0x3f00
#endif
-static const int xilinx_ml40x_ipl2spl_table[] = {
+static const struct ipl_sr_map xilinx_ml40x_ipl_sr_map = {
+ .sr_bits = {
[IPL_NONE] = 0,
- [IPL_SOFTCLOCK] = NOINTS,
- [IPL_SOFTSERIAL] = NOINTS,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
[IPL_VM] = NOINTS,
[IPL_SCHED] = NOINTS,
+ [IPL_DDB] = NOINTS,
[IPL_HIGH] = NOINTS,
+ },
};
void
@@ -92,7 +102,7 @@
sprintf(cpu_model, "Xilinx ML%s (eMIPS)", (systype == XS_ML40x) ? "40x" : "50x");
- ipl2spl_table = xilinx_ml40x_ipl2spl_table;
+ ipl_sr_map = xilinx_ml40x_ipl_sr_map;
}
static void
@@ -106,17 +116,12 @@
pmap_kenter_pa(USART_DEFAULT_ADDRESS,
USART_DEFAULT_ADDRESS,VM_PROT_WRITE|VM_PROT_READ);
#else
- struct mips1_tlb {
- u_int32_t tlb_hi;
- u_int32_t tlb_lo;
- } tlb;
- void mips1_TLBWrite(int, struct mips1_tlb *);
+ struct tlbmask tlb;
tlb.tlb_hi = USART_DEFAULT_ADDRESS;
- tlb.tlb_lo = USART_DEFAULT_ADDRESS | 0xf02;
- mips1_TLBWrite(3, &tlb);
+ tlb.tlb_lo0 = USART_DEFAULT_ADDRESS | 0xf02;
+ tlb_write_indexed(3, &tlb);
#endif
dz_ebus_cnsetup(USART_DEFAULT_ADDRESS);
}
-
Index: src/sys/arch/emips/emips/xs_bee3.c
diff -u src/sys/arch/emips/emips/xs_bee3.c:1.1 src/sys/arch/emips/emips/xs_bee3.c:1.2
--- src/sys/arch/emips/emips/xs_bee3.c:1.1 Wed Jan 26 01:18:51 2011
+++ src/sys/arch/emips/emips/xs_bee3.c Tue Feb 22 08:20:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: xs_bee3.c,v 1.1 2011/01/26 01:18:51 pooka Exp $ */
+/* $NetBSD: xs_bee3.c,v 1.2 2011/02/22 08:20:20 matt Exp $ */
/*-
* Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -31,15 +31,20 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: xs_bee3.c,v 1.1 2011/01/26 01:18:51 pooka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: xs_bee3.c,v 1.2 2011/02/22 08:20:20 matt Exp $");
+
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
+#include <sys/cpu.h>
+#include <sys/intr.h>
+
+#include <uvm/uvm_extern.h>
-#include <machine/cpu.h>
-#include <machine/intr.h>
#include <machine/sysconf.h>
+#include <machine/locore.h>
#include <emips/emips/machdep.h>
#include <emips/emips/cons.h>
@@ -52,7 +57,7 @@
#if 0
#define NOINTS (MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
#else
-#define NOINTS MIPS_SPLHIGH
+#define NOINTS MIPS_INT_MASK
#endif
/* BUGBUG Rewrite this to go off to the interrupt controller masks */
@@ -65,13 +70,18 @@
splvec.splstatclock = MIPS_SPL_0_1_2_3; //0x3f00
#endif
-static const int xs_bee3_ipl2spl_table[] = {
+static const struct ipl_sr_map xs_bee3_ipl_sr_map = {
+ .sr_bits = {
[IPL_NONE] = 0,
- [IPL_SOFTCLOCK] = NOINTS,
- [IPL_SOFTSERIAL] = NOINTS,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
[IPL_VM] = NOINTS,
[IPL_SCHED] = NOINTS,
+ [IPL_DDB] = NOINTS,
[IPL_HIGH] = NOINTS,
+ },
};
void
@@ -90,7 +100,7 @@
cpuspeed = 8; /* xxx */
sprintf(cpu_model, "BeSquare BEE3 (eMIPS)");
- ipl2spl_table = xs_bee3_ipl2spl_table;
+ ipl_sr_map = xs_bee3_ipl_sr_map;
}
static void
@@ -105,15 +115,11 @@
pmap_kenter_pa(USART_DEFAULT_ADDRESS,
USART_DEFAULT_ADDRESS,VM_PROT_WRITE|VM_PROT_READ);
#else
- struct mips1_tlb {
- u_int32_t tlb_hi;
- u_int32_t tlb_lo;
- } tlb;
- void mips1_TLBWrite(int, struct mips1_tlb *);
+ struct tlbmask tlb;
tlb.tlb_hi = USART_DEFAULT_ADDRESS;
- tlb.tlb_lo = USART_DEFAULT_ADDRESS | 0xf02;
- mips1_TLBWrite(3, &tlb);
+ tlb.tlb_lo0 = USART_DEFAULT_ADDRESS | 0xf02;
+ tlb_write_indexed(3, &tlb);
#endif
dz_ebus_cnsetup(USART_DEFAULT_ADDRESS);
Index: src/sys/arch/emips/emips/machdep.c
diff -u src/sys/arch/emips/emips/machdep.c:1.3 src/sys/arch/emips/emips/machdep.c:1.4
--- src/sys/arch/emips/emips/machdep.c:1.3 Sun Feb 20 08:01:10 2011
+++ src/sys/arch/emips/emips/machdep.c Tue Feb 22 08:20:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.3 2011/02/20 08:01:10 matt Exp $ */
+/* $NetBSD: machdep.c,v 1.4 2011/02/22 08:20:20 matt Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -39,7 +39,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.3 2011/02/20 08:01:10 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.4 2011/02/22 08:20:20 matt Exp $");
#include "opt_ddb.h"
@@ -110,28 +110,12 @@
int mem_cluster_cnt;
phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
-/*
- * During autoconfiguration or after a panic, a sleep will simply
- * lower the priority briefly to allow interrupts, then return.
- * The priority to be used (safepri) is machine-dependent, thus this
- * value is initialized and maintained in the machine-dependent layers.
- * This priority will typically be 0, or the lowest priority
- * that is safe for use on the interrupt stack; it can be made
- * higher to block network software interrupts after panics.
- */
-/*
- * safepri is a safe priority for sleep to set for a spin-wait
- * during autoconfiguration or after a panic.
- * Used as an argument to splx().
- */
-int safepri = MIPS3_PSL_LOWIPL; /* XXX */
-
void mach_init (int, char *[], int, intptr_t, u_int, char *); /* XXX */
/* Motherboard or system-specific initialization vector */
static void unimpl_bus_reset(void);
static void unimpl_cons_init(void);
-static void unimpl_iointr(unsigned, unsigned, unsigned, unsigned);
+static void unimpl_iointr(uint32_t, vaddr_t, uint32_t);
static void unimpl_intr_establish(struct device *, void *, int,
int (*)(void *, void *), void *);
static int unimpl_memsize(void *);
@@ -732,7 +716,7 @@
}
static void
-unimpl_iointr(u_int mask, u_int pc, u_int statusreg, u_int causereg)
+unimpl_iointr(uint32_t status, vaddr_t pc, uint32_t ipending)
{
panic("sysconf.init didn't set intr");
Index: src/sys/arch/emips/include/intr.h
diff -u src/sys/arch/emips/include/intr.h:1.1 src/sys/arch/emips/include/intr.h:1.2
--- src/sys/arch/emips/include/intr.h:1.1 Wed Jan 26 01:18:51 2011
+++ src/sys/arch/emips/include/intr.h Tue Feb 22 08:20:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.1 2011/01/26 01:18:51 pooka Exp $ */
+/* $NetBSD: intr.h,v 1.2 2011/02/22 08:20:20 matt Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -36,63 +36,16 @@
#include <sys/evcnt.h>
#include <sys/queue.h>
-#define IPL_NONE 0 /* disable only this interrupt */
-#define IPL_SOFTCLOCK 1 /* clock software interrupts (SI 0) */
-#define IPL_SOFTBIO 1 /* generic software interrupts (SI 0) */
-#define IPL_SOFTNET 2 /* network software interrupts (SI 1) */
-#define IPL_SOFTSERIAL 2 /* serial software interrupts (SI 1) */
-#define IPL_VM 3
-#define IPL_SCHED 4
-#define IPL_HIGH 5
-
-#define _IPL_N 6
-
-#define _IPL_SI0_FIRST IPL_SOFTCLOCK
-#define _IPL_SI0_LAST IPL_SOFTBIO
-
-#define _IPL_SI1_FIRST IPL_SOFTNET
-#define _IPL_SI1_LAST IPL_SOFTSERIAL
+#include <mips/intr.h>
#ifdef _KERNEL
#ifndef _LOCORE
-#include <mips/cpuregs.h>
-#include <mips/locore.h>
-
-#define spl0() (void)_spllower(0)
-#define splx(s) (void)_splset(s)
-#define splvm() splraiseipl(makeiplcookie(IPL_VM))
-#define splsched() splraiseipl(makeiplcookie(IPL_SCHED))
-#define splhigh() _splraise(MIPS_INT_MASK)
-
-#define _SPL_SOFT MIPS_SOFT_INT_MASK_0
-#define _SPL_SOFTCLOCK MIPS_SOFT_INT_MASK_0
-#define _SPL_SOFTNET (MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
-#define _SPL_SOFTSERIAL (MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
-
-#define splsoftclock() _splraise(_SPL_SOFTCLOCK)
-#define splsoftbio() _splraise(_SPL_SOFTBIO)
-#define splsoftnet() _splraise(_SPL_SOFTNET)
-#define splsoftserial() _splraise(_SPL_SOFTSERIAL)
-
-extern const int *ipl2spl_table;
-
-typedef int ipl_t;
-typedef struct {
- int _spl;
-} ipl_cookie_t;
-
-ipl_cookie_t makeiplcookie(ipl_t);
-
-static inline int
-splraiseipl(ipl_cookie_t icookie)
-{
-
- return _splraise(icookie._spl);
-}
-
-/* Conventionals ... */
+extern struct evcnt emips_clock_evcnt;
+extern struct evcnt emips_fpu_evcnt;
+extern struct evcnt emips_memerr_evcnt;
+#if 0
#define MIPS_SPLHIGH (MIPS_INT_MASK)
#define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
#define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
@@ -101,6 +54,7 @@
#define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1)
#define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1)
#define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2)
+#endif
struct intrhand {
int (*ih_func)(void *, void *);
@@ -116,12 +70,6 @@
void *ih_arg;
};
-#include <mips/softintr.h>
-
-extern struct evcnt emips_clock_evcnt;
-extern struct evcnt emips_fpu_evcnt;
-extern struct evcnt emips_memerr_evcnt;
-
void intr_init(int);
#endif /* !_LOCORE */
#endif /* _KERNEL */
Index: src/sys/arch/emips/include/sysconf.h
diff -u src/sys/arch/emips/include/sysconf.h:1.1 src/sys/arch/emips/include/sysconf.h:1.2
--- src/sys/arch/emips/include/sysconf.h:1.1 Wed Jan 26 01:18:52 2011
+++ src/sys/arch/emips/include/sysconf.h Tue Feb 22 08:20:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: sysconf.h,v 1.1 2011/01/26 01:18:52 pooka Exp $ */
+/* $NetBSD: sysconf.h,v 1.2 2011/02/22 08:20:20 matt Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -63,7 +63,7 @@
*/
void (*bus_reset) (void);
void (*cons_init) (void);
- void (*iointr) (unsigned, unsigned, unsigned, unsigned);
+ void (*iointr) (uint32_t, vaddr_t, uint32_t);
void (*intr_establish) (struct device *, void *, int,
int (*)(void *, void *), void *);
int (*memsize) (void *);
@@ -93,7 +93,7 @@
void noop(void);
void emips_intr_establish(struct device *, void *, int,
int (*)(void *, void *), void *);
-void emips_aic_intr(unsigned, unsigned, unsigned, unsigned);
+void emips_aic_intr(uint32_t, vaddr_t, uint32_t);
#endif /* _KERNEL */
#endif /* !_EMIPS_SYSCONF_H_ */
