Module Name: src
Committed By: tsutsui
Date: Sat Feb 26 12:54:41 UTC 2011
Modified Files:
src/sys/arch/hpcmips/tx: tx39icu.c
Log Message:
Mechanically adapt to new interrupt/spl framework. Untested.
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/hpcmips/tx/tx39icu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/hpcmips/tx/tx39icu.c
diff -u src/sys/arch/hpcmips/tx/tx39icu.c:1.29 src/sys/arch/hpcmips/tx/tx39icu.c:1.30
--- src/sys/arch/hpcmips/tx/tx39icu.c:1.29 Sat Feb 26 12:09:34 2011
+++ src/sys/arch/hpcmips/tx/tx39icu.c Sat Feb 26 12:54:41 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: tx39icu.c,v 1.29 2011/02/26 12:09:34 tsutsui Exp $ */
+/* $NetBSD: tx39icu.c,v 1.30 2011/02/26 12:54:41 tsutsui Exp $ */
/*-
* Copyright (c) 1999-2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tx39icu.c,v 1.29 2011/02/26 12:09:34 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tx39icu.c,v 1.30 2011/02/26 12:54:41 tsutsui Exp $");
#include "opt_vr41xx.h"
#include "opt_tx39xx.h"
@@ -39,6 +39,8 @@
#include "opt_tx39icu_debug.h"
#include "opt_tx39_watchdogtimer.h"
+#define __INTR_PRIVATE
+
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
@@ -49,8 +51,8 @@
#include <uvm/uvm_extern.h>
#include <mips/cpuregs.h>
-#include <mips/locore.h>
#include <machine/bus.h>
+#include <machine/intr.h>
#include <hpcmips/tx/tx39var.h>
#include <hpcmips/tx/tx39icureg.h>
@@ -66,7 +68,7 @@
#else
#define TX_INTR cpu_intr /* locore_mips3 directly call this */
#endif
-void TX_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
+void TX_INTR(int, vaddr_t, uint32_t);
#ifdef TX39ICU_DEBUG
#define DPRINTF_ENABLE
@@ -74,29 +76,26 @@
#endif
#include <machine/debug.h>
-u_int32_t tx39intrvec;
+uint32_t tx39intrvec;
/*
* This is a mask of bits to clear in the SR when we go to a
* given interrupt priority level.
*/
-const u_int32_t __ipl_sr_bits_tx[_IPL_N] = {
- 0, /* IPL_NONE */
-
- MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_4, /* IPL_VM */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_4, /* IPL_SCHED */
+const struct ipl_sr_map __ipl_sr_map_tx = {
+ .sr_bits = {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_2
+ | MIPS_INT_MASK_4,
+ [IPL_SCHED] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_2
+ | MIPS_INT_MASK_4,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
};
/* IRQHIGH lines list */
@@ -201,14 +200,13 @@
int tx39icu_match(struct device *, struct cfdata *, void *);
void tx39icu_attach(struct device *, struct device *, void *);
-int tx39icu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
void tx39_intr_dump(struct tx39icu_softc *);
void tx39_intr_decode(int, int *, int *);
void tx39_irqhigh_disestablish(tx_chipset_tag_t, int, int, int);
void tx39_irqhigh_establish(tx_chipset_tag_t, int, int, int,
int (*)(void *), void *);
-void tx39_irqhigh_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
+void tx39_irqhigh_intr(uint32_t, uint32_t, uint32_t);
int tx39_irqhigh(int, int);
CFATTACH_DECL(tx39icu, sizeof(struct tx39icu_softc),
@@ -306,23 +304,15 @@
}
void
-TX_INTR(u_int32_t status, u_int32_t cause, vaddr_t pc, u_int32_t ipending)
+TX_INTR(int ppl, vaddr_t pc, uint32_t status)
{
+ uint32_t ipending;
+ int ipl;
struct tx39icu_softc *sc;
tx_chipset_tag_t tc;
- struct cpu_info *ci;
txreg_t reg, pend, *regs;
int i, j;
- ci = curcpu();
- ci->ci_idepth++;
- ci->ci_data.cpu_nintr++;
-
-#ifdef __HAVE_FAST_SOFTINTS
- if ((ipending & MIPS_HARD_INT_MASK) == 0)
- goto softintr;
-#endif
-
tc = tx_conf_get_tag();
sc = tc->tc_intrt;
/*
@@ -340,89 +330,92 @@
regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG);
#endif
+ while (ppl < (ipl = splintr(&ipending))) {
#ifdef TX39ICU_DEBUG
- if (!(ipending & MIPS_INT_MASK_4) && !(ipending & MIPS_INT_MASK_2)) {
- dbg_bit_print(ipending);
- panic("bogus HwInt");
- }
- if (tx39icu_debug > 1) {
- tx39_intr_dump(sc);
- }
+ if (!(ipending & MIPS_INT_MASK_4) &&
+ !(ipending & MIPS_INT_MASK_2)) {
+ dbg_bit_print(ipending);
+ panic("bogus HwInt");
+ }
+ if (tx39icu_debug > 1) {
+ tx39_intr_dump(sc);
+ }
#endif /* TX39ICU_DEBUG */
- /* IRQHIGH */
- if (ipending & MIPS_INT_MASK_4) {
- tx39_irqhigh_intr(ipending, pc, status, cause);
-
-#ifdef __HAVE_FAST_SOFTINTS
- goto softintr;
-#endif
- }
+ /* IRQHIGH */
+ if (ipending & MIPS_INT_MASK_4) {
+ tx39_irqhigh_intr(ipending, pc, status);
+ }
- /* IRQLOW */
- if (ipending & MIPS_INT_MASK_2) {
- for (i = 1; i <= TX39_INTRSET_MAX; i++) {
- int ofs;
+ /* IRQLOW */
+ if (ipending & MIPS_INT_MASK_2) {
+ for (i = 1; i <= TX39_INTRSET_MAX; i++) {
+ int ofs;
#ifdef TX392X
- if (i == 6)
- continue;
+ if (i == 6)
+ continue;
#endif /* TX392X */
- ofs = TX39_INTRSTATUS_REG(i);
- pend = sc->sc_regs[i];
- reg = sc->sc_le_mask[i] & pend;
- /* Clear interrupts */
- tx_conf_write(tc, ofs, reg);
- /* Dispatch handler */
- for (j = 0 ; j < 32; j++) {
- if ((reg & (1 << j)) &&
- sc->sc_le_fun[i][j]) {
+ ofs = TX39_INTRSTATUS_REG(i);
+ pend = sc->sc_regs[i];
+ reg = sc->sc_le_mask[i] & pend;
+ /* Clear interrupts */
+ tx_conf_write(tc, ofs, reg);
+ /* Dispatch handler */
+ for (j = 0 ; j < 32; j++) {
+ if ((reg & (1 << j)) &&
+ sc->sc_le_fun[i][j]) {
#ifdef TX39ICU_DEBUG
- if (tx39icu_debug > 1) {
- tx39intrvec = (i << 16) | j;
- DPRINTF("IRQLOW %d:%d\n", i, j);
- }
+ if (tx39icu_debug > 1) {
+ tx39intrvec =
+ (i << 16) | j;
+ DPRINTF("IRQLOW "
+ "%d:%d\n", i, j);
+ }
#endif /* TX39ICU_DEBUG */
- (*sc->sc_le_fun[i][j])
- (sc->sc_le_arg[i][j]);
+ (*sc->sc_le_fun[i][j])
+ (sc->sc_le_arg[i][j]);
+ }
}
- }
#ifdef TX39ICU_DEBUG_PRINT_PENDING_INTERRUPT
- pend &= ~reg;
- if (pend) {
- printf("%d pending:", i);
- dbg_bit_print(pend);
- }
+ pend &= ~reg;
+ if (pend) {
+ printf("%d pending:", i);
+ dbg_bit_print(pend);
+ }
#endif
+ }
}
- }
#ifdef TX39_WATCHDOGTIMER
- {
- extern int tx39biu_intr(void *);
- /* Bus error (If watch dog timer is enabled)*/
- if (ipending & MIPS_INT_MASK_1) {
- tx39biu_intr(0); /* Clear bus error */
+ {
+ extern int tx39biu_intr(void *);
+ /* Bus error (If watch dog timer is enabled)*/
+ if (ipending & MIPS_INT_MASK_1) {
+ tx39biu_intr(0); /* Clear bus error */
+ }
}
- }
+ /*
+ * Read regsiter again
+ */
+ regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG);
+ regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG);
+ regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG);
+ regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG);
+ regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG);
+ regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG);
+#ifdef TX392X
+ regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG);
+ regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG);
#endif
+#endif
+ }
#if 0
/* reset priority mask */
reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, 0xffff);
tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
#endif
-
-#ifdef __HAVE_FAST_SOFTINTS
- softintr:
-#endif
- ci->ci_idepth--;
-#ifdef __HAVE_FAST_SOFTINTS
- ipending &= MIPS_SOFT_INT_MASK;
- if (ipending == 0)
- return;
- softint_process(ipending);
-#endif
}
int
@@ -441,8 +434,7 @@
}
void
-tx39_irqhigh_intr(u_int32_t ipending, u_int32_t pc, u_int32_t status,
- u_int32_t cause)
+tx39_irqhigh_intr(uint32_t ipending, uint32_t pc, uint32_t status)
{
struct txintr_high_entry *he;
struct tx39icu_softc *sc;
@@ -460,6 +452,7 @@
TX39_INTRSTATUS5_PERINT);
cf.pc = pc;
cf.sr = status;
+ cf.intr = (curcpu()->ci_idepth > 1);
hardclock(&cf);
return;
@@ -618,7 +611,7 @@
}
}
-u_int32_t
+uint32_t
tx_intr_status(tx_chipset_tag_t tc, int r)
{
struct tx39icu_softc *sc = tc->tc_intrt;
@@ -626,7 +619,7 @@
if (r < 0 || r >= TX39_INTRSET_MAX + 1)
panic("tx_intr_status: invalid index %d", r);
- return (u_int32_t)(sc->sc_regs[r]);
+ return (uint32_t)(sc->sc_regs[r]);
}
#ifdef USE_POLL
