Module Name:    src
Committed By:   macallan
Date:           Mon Feb 28 10:03:50 UTC 2011

Modified Files:
        src/sys/arch/arm/arm32: pmap.c
        src/sys/arch/arm/include/arm32: pmap.h

Log Message:
implement arm32_pmap_flags() to allow mappings with write buffering enabled,
mostly for video memory
Tested on shark


To generate a diff of this commit:
cvs rdiff -u -r1.219 -r1.220 src/sys/arch/arm/arm32/pmap.c
cvs rdiff -u -r1.97 -r1.98 src/sys/arch/arm/include/arm32/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/arm32/pmap.c
diff -u src/sys/arch/arm/arm32/pmap.c:1.219 src/sys/arch/arm/arm32/pmap.c:1.220
--- src/sys/arch/arm/arm32/pmap.c:1.219	Fri Nov 12 07:59:25 2010
+++ src/sys/arch/arm/arm32/pmap.c	Mon Feb 28 10:03:49 2011
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.c,v 1.219 2010/11/12 07:59:25 uebayasi Exp $	*/
+/*	$NetBSD: pmap.c,v 1.220 2011/02/28 10:03:49 macallan Exp $	*/
 
 /*
  * Copyright 2003 Wasabi Systems, Inc.
@@ -211,7 +211,7 @@
 #include <machine/param.h>
 #include <arm/arm32/katelib.h>
 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.219 2010/11/12 07:59:25 uebayasi Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.220 2011/02/28 10:03:49 macallan Exp $");
 
 #ifdef PMAP_DEBUG
 
@@ -2745,6 +2745,16 @@
 	return (pm);
 }
 
+u_int
+arm32_mmap_flags(paddr_t pa)
+{
+	/*
+	 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff
+	 * and we're using the upper bits in page numbers to pass flags around
+	 * so we might as well use the same bits
+	 */
+	return (u_int)pa & PMAP_MD_MASK;
+}
 /*
  * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot,
  *      u_int flags)
@@ -2953,9 +2963,12 @@
 		/*
 		 * Make sure the vector table is mapped cacheable
 		 */
-		if (pm != pmap_kernel() && va == vector_page)
+		if ((pm != pmap_kernel() && va == vector_page) ||
+		    (flags & ARM32_MMAP_CACHEABLE)) {
 			npte |= pte_l2_s_cache_mode;
-
+		} else if (flags & ARM32_MMAP_WRITECOMBINE) {
+			npte |= pte_l2_s_wc_mode;
+		}
 		if (opg) {
 			/*
 			 * Looks like there's an existing 'managed' mapping
@@ -5917,14 +5930,17 @@
  */
 
 pt_entry_t	pte_l1_s_cache_mode;
+pt_entry_t	pte_l1_s_wc_mode;
 pt_entry_t	pte_l1_s_cache_mode_pt;
 pt_entry_t	pte_l1_s_cache_mask;
 
 pt_entry_t	pte_l2_l_cache_mode;
+pt_entry_t	pte_l2_l_wc_mode;
 pt_entry_t	pte_l2_l_cache_mode_pt;
 pt_entry_t	pte_l2_l_cache_mask;
 
 pt_entry_t	pte_l2_s_cache_mode;
+pt_entry_t	pte_l2_s_wc_mode;
 pt_entry_t	pte_l2_s_cache_mode_pt;
 pt_entry_t	pte_l2_s_cache_mask;
 
@@ -5956,12 +5972,15 @@
 {
 
 	pte_l1_s_cache_mode = L1_S_B|L1_S_C;
+	pte_l1_s_wc_mode = L1_S_B;
 	pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
 
 	pte_l2_l_cache_mode = L2_B|L2_C;
+	pte_l2_l_wc_mode = L2_B;
 	pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
 
 	pte_l2_s_cache_mode = L2_B|L2_C;
+	pte_l2_s_wc_mode = L2_B;
 	pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
 
 	/*
@@ -6040,6 +6059,10 @@
 	pte_l2_l_cache_mode = L2_C;
 	pte_l2_s_cache_mode = L2_C;
 
+	pte_l1_s_wc_mode = L1_S_B;
+	pte_l2_l_wc_mode = L2_B;
+	pte_l2_s_wc_mode = L2_B;
+
 	pte_l1_s_cache_mode_pt = L1_S_C;
 	pte_l2_l_cache_mode_pt = L2_C;
 	pte_l2_s_cache_mode_pt = L2_C;
@@ -6062,6 +6085,10 @@
 	pte_l2_l_cache_mode = L2_B | L2_C;
 	pte_l2_s_cache_mode = L2_B | L2_C;
 
+	pte_l1_s_cache_mode = L1_S_B;
+	pte_l2_l_cache_mode = L2_B;
+	pte_l2_s_cache_mode = L2_B;
+
 	pte_l1_s_cache_mode_pt = L1_S_C;
 	pte_l2_l_cache_mode_pt = L2_C;
 	pte_l2_s_cache_mode_pt = L2_C;
@@ -6084,6 +6111,10 @@
 	pte_l2_l_cache_mode = L2_C;
 	pte_l2_s_cache_mode = L2_C;
 
+	pte_l1_s_wc_mode = L1_S_B;
+	pte_l2_l_wc_mode = L2_B;
+	pte_l2_s_wc_mode = L2_B;
+
 	pte_l1_s_cache_mode_pt = L1_S_C;
 	pte_l2_l_cache_mode_pt = L2_C;
 	pte_l2_s_cache_mode_pt = L2_C;
@@ -6123,12 +6154,15 @@
 	int write_through = 0;
 
 	pte_l1_s_cache_mode = L1_S_B|L1_S_C;
+	pte_l1_s_wc_mode = L1_S_B;
 	pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
 
 	pte_l2_l_cache_mode = L2_B|L2_C;
+	pte_l2_l_wc_mode = L2_B;
 	pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
 
 	pte_l2_s_cache_mode = L2_B|L2_C;
+	pte_l2_s_wc_mode = L2_B;
 	pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
 
 	pte_l1_s_cache_mode_pt = L1_S_C;

Index: src/sys/arch/arm/include/arm32/pmap.h
diff -u src/sys/arch/arm/include/arm32/pmap.h:1.97 src/sys/arch/arm/include/arm32/pmap.h:1.98
--- src/sys/arch/arm/include/arm32/pmap.h:1.97	Sun Nov 14 13:33:21 2010
+++ src/sys/arch/arm/include/arm32/pmap.h	Mon Feb 28 10:03:49 2011
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.h,v 1.97 2010/11/14 13:33:21 uebayasi Exp $	*/
+/*	$NetBSD: pmap.h,v 1.98 2011/02/28 10:03:49 macallan Exp $	*/
 
 /*
  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -278,6 +278,10 @@
 #define	pmap_copy(dp, sp, da, l, sa)	/* nothing */
 
 #define pmap_phys_address(ppn)		(arm_ptob((ppn)))
+u_int arm32_mmap_flags(paddr_t);
+#define ARM32_MMAP_WRITECOMBINE	0x40000000
+#define ARM32_MMAP_CACHEABLE		0x20000000
+#define pmap_mmap_flags(ppn)			arm32_mmap_flags(ppn)
 
 /*
  * Functions that we need to export
@@ -500,6 +504,10 @@
 extern pt_entry_t		pte_l2_l_cache_mode_pt;
 extern pt_entry_t		pte_l2_s_cache_mode_pt;
 
+extern pt_entry_t		pte_l1_s_wc_mode;
+extern pt_entry_t		pte_l2_l_wc_mode;
+extern pt_entry_t		pte_l2_s_wc_mode;
+
 extern pt_entry_t		pte_l1_s_prot_u;
 extern pt_entry_t		pte_l1_s_prot_w;
 extern pt_entry_t		pte_l1_s_prot_ro;

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