Module Name: src
Committed By: matt
Date: Thu Mar 3 18:44:59 UTC 2011
Modified Files:
src/sys/arch/mips/include: cpuregs.h locore.h
src/sys/arch/mips/mips: db_interface.c mips_machdep.c
Log Message:
Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL
To generate a diff of this commit:
cvs rdiff -u -r1.80 -r1.81 src/sys/arch/mips/include/cpuregs.h
cvs rdiff -u -r1.83 -r1.84 src/sys/arch/mips/include/locore.h
cvs rdiff -u -r1.68 -r1.69 src/sys/arch/mips/mips/db_interface.c
cvs rdiff -u -r1.234 -r1.235 src/sys/arch/mips/mips/mips_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.80 src/sys/arch/mips/include/cpuregs.h:1.81
--- src/sys/arch/mips/include/cpuregs.h:1.80 Sun Feb 20 07:45:47 2011
+++ src/sys/arch/mips/include/cpuregs.h Thu Mar 3 18:44:58 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.80 2011/02/20 07:45:47 matt Exp $ */
+/* $NetBSD: cpuregs.h,v 1.81 2011/03/03 18:44:58 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -457,13 +457,18 @@
* 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
* 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
* 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
+ * 4/2 MIPS_COP_0_USERLOCAL ..36 UserLocal.
* 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
* 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
+ * 7 MIPS_COP_0_HWRENA ..33 rdHWR Enable
* 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
* 9 MIPS_COP_0_COUNT .333 Count register.
* 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
* 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
* 12 MIPS_COP_0_STATUS 3333 Status register.
+ * 12/1 MIPS_COP_0_INTCTL ..33 Interrupt Control
+ * 12/2 MIPS_COP_0_SRSCTL ..33 Shadow Register Set Selectors
+ * 12/3 MIPS_COP_0_SRSMAP ..33 Shadow Set Map
* 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
* 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
* 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
@@ -472,6 +477,8 @@
* 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
* 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
* 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
+ * 16/7 MIPS_COP_0_CONFIG6 ..33 Configuration register 6.
+ * 16/7 MIPS_COP_0_CONFIG7 ..33 Configuration register 7.
* 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
* 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
* 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.83 src/sys/arch/mips/include/locore.h:1.84
--- src/sys/arch/mips/include/locore.h:1.83 Sun Feb 20 07:45:47 2011
+++ src/sys/arch/mips/include/locore.h Thu Mar 3 18:44:58 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.83 2011/02/20 07:45:47 matt Exp $ */
+/* $NetBSD: locore.h,v 1.84 2011/03/03 18:44:58 matt Exp $ */
/*
* This file should not be included by MI code!!!
@@ -544,7 +544,15 @@
#define MIPS_CP0FL_EIMR __BIT(4)
#define MIPS_CP0FL_EBASE __BIT(5)
#define MIPS_CP0FL_CONFIG __BIT(6)
-#define MIPS_CP0FL_CONFIGn(n) (__BIT(7) << ((n) & 7))
+#define MIPS_CP0FL_CONFIG1 __BIT(7)
+#define MIPS_CP0FL_CONFIG2 __BIT(8)
+#define MIPS_CP0FL_CONFIG3 __BIT(9)
+#define MIPS_CP0FL_CONFIG4 __BIT(10)
+#define MIPS_CP0FL_CONFIG5 __BIT(11)
+#define MIPS_CP0FL_CONFIG6 __BIT(12)
+#define MIPS_CP0FL_CONFIG7 __BIT(13)
+#define MIPS_CP0FL_USERLOCAL __BIT(14)
+#define MIPS_CP0FL_HWRENA __BIT(15)
/*
* cpu_cidflags defines, by company
@@ -552,10 +560,10 @@
/*
* RMI company-specific cpu_cidflags
*/
-#define MIPS_CIDFL_RMI_TYPE __BITS(2,0)
-# define CIDFL_RMI_TYPE_XLR 0
-# define CIDFL_RMI_TYPE_XLS 1
-# define CIDFL_RMI_TYPE_XLP 2
+#define MIPS_CIDFL_RMI_TYPE __BITS(2,0)
+# define CIDFL_RMI_TYPE_XLR 0
+# define CIDFL_RMI_TYPE_XLS 1
+# define CIDFL_RMI_TYPE_XLP 2
#define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3)
# define MIPS_CIDFL_RMI_THREADS_SHIFT 3
#define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7)
Index: src/sys/arch/mips/mips/db_interface.c
diff -u src/sys/arch/mips/mips/db_interface.c:1.68 src/sys/arch/mips/mips/db_interface.c:1.69
--- src/sys/arch/mips/mips/db_interface.c:1.68 Sun Feb 20 07:45:47 2011
+++ src/sys/arch/mips/mips/db_interface.c Thu Mar 3 18:44:58 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.68 2011/02/20 07:45:47 matt Exp $ */
+/* $NetBSD: db_interface.c,v 1.69 2011/03/03 18:44:58 matt Exp $ */
/*
* Mach Operating System
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.68 2011/02/20 07:45:47 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.69 2011/03/03 18:44:58 matt Exp $");
#include "opt_multiprocessor.h"
#include "opt_cputype.h" /* which mips CPUs do we support? */
@@ -294,25 +294,17 @@
}
#define FLDWIDTH 10
-#define SHOW32(reg, name) \
-do { \
- uint32_t __val; \
- \
- __asm volatile("mfc0 %0,$" ___STRING(reg) : "=r"(__val)); \
- printf(" %s:%*s %#x\n", name, FLDWIDTH - (int) strlen(name), \
- "", __val); \
-} while (0)
+#define SHOW32(reg, name) SHOW32SEL(reg, 0, name)
#define SHOW64(reg, name) MIPS64_SHOW64(reg, 0, name)
-#define MIPS64_SHOW32(num, sel, name) \
+#define SHOW32SEL(num, sel, name) \
do { \
uint32_t __val; \
\
- KASSERT (CPUIS64BITS); \
__asm volatile( \
".set push \n\t" \
- ".set mips64 \n\t" \
+ ".set mips32 \n\t" \
"mfc0 %0,$%1,%2 \n\t" \
".set pop \n\t" \
: "=r"(__val) : "n"(num), "n"(sel)); \
@@ -450,28 +442,30 @@
if ((cp0flags & MIPS_CP0FL_USE) != 0) {
if ((cp0flags & MIPS_CP0FL_EBASE) != 0)
- MIPS64_SHOW32(15, 1, "ebase");
+ SHOW32SEL(15, 1, "ebase");
if ((cp0flags & MIPS_CP0FL_CONFIG) != 0)
SHOW32(MIPS_COP_0_CONFIG, "config");
- if ((cp0flags & MIPS_CP0FL_CONFIGn(0)) != 0)
- MIPS64_SHOW32(16, 0, "config0");
- if ((cp0flags & MIPS_CP0FL_CONFIGn(1)) != 0)
- MIPS64_SHOW32(16, 1, "config1");
- if ((cp0flags & MIPS_CP0FL_CONFIGn(2)) != 0)
- MIPS64_SHOW32(16, 2, "config2");
- if ((cp0flags & MIPS_CP0FL_CONFIGn(3)) != 0)
- MIPS64_SHOW32(16, 3, "config3");
- if ((cp0flags & MIPS_CP0FL_CONFIGn(4)) != 0)
- MIPS64_SHOW32(16, 4, "config4");
- if ((cp0flags & MIPS_CP0FL_CONFIGn(5)) != 0)
- MIPS64_SHOW32(16, 5, "config5");
- if ((cp0flags & MIPS_CP0FL_CONFIGn(6)) != 0)
- MIPS64_SHOW32(16, 6, "config6");
- if ((cp0flags & MIPS_CP0FL_CONFIGn(7)) != 0)
- MIPS64_SHOW32(16, 7, "config7");
+ if ((cp0flags & MIPS_CP0FL_CONFIG1) != 0)
+ SHOW32SEL(16, 1, "config1");
+ if ((cp0flags & MIPS_CP0FL_CONFIG2) != 0)
+ SHOW32SEL(16, 2, "config2");
+ if ((cp0flags & MIPS_CP0FL_CONFIG3) != 0)
+ SHOW32SEL(16, 3, "config3");
+ if ((cp0flags & MIPS_CP0FL_CONFIG4) != 0)
+ SHOW32SEL(16, 4, "config4");
+ if ((cp0flags & MIPS_CP0FL_CONFIG5) != 0)
+ SHOW32SEL(16, 5, "config5");
+ if ((cp0flags & MIPS_CP0FL_CONFIG6) != 0)
+ SHOW32SEL(16, 6, "config6");
+ if ((cp0flags & MIPS_CP0FL_CONFIG7) != 0)
+ SHOW32SEL(16, 7, "config7");
+ if ((cp0flags & MIPS_CP0FL_HWRENA) != 0)
+ SHOW32(7, "hwrena");
+ if ((cp0flags & MIPS_CP0FL_USERLOCAL) != 0)
+ SHOW32SEL(4, 2, "userlocal");
} else {
SHOW32(MIPS_COP_0_CONFIG, "config");
-#if defined(MIPS32) || defined(MIPS64)
+#if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
if (CPUISMIPSNN) {
uint32_t val;
@@ -500,7 +494,7 @@
}
if (CPUISMIPSNN) {
- if (CPUISMIPS64) {
+ if (CPUIS64BITS) {
SHOW64(MIPS_COP_0_PERFCNT, "perfcnt");
} else {
SHOW32(MIPS_COP_0_PERFCNT, "perfcnt");
Index: src/sys/arch/mips/mips/mips_machdep.c
diff -u src/sys/arch/mips/mips/mips_machdep.c:1.234 src/sys/arch/mips/mips/mips_machdep.c:1.235
--- src/sys/arch/mips/mips/mips_machdep.c:1.234 Sun Feb 20 07:45:48 2011
+++ src/sys/arch/mips/mips/mips_machdep.c Thu Mar 3 18:44:58 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.234 2011/02/20 07:45:48 matt Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.235 2011/03/03 18:44:58 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -112,7 +112,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.234 2011/02/20 07:45:48 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.235 2011/03/03 18:44:58 matt Exp $");
#define __INTR_PRIVATE
#include "opt_cputype.h"
@@ -425,13 +425,33 @@
{ MIPS_PRID_CID_MTI, MIPS_20Kc, -1, -1, -1, 0,
MIPS64_FLAGS, 0, 0, "20Kc" },
{ MIPS_PRID_CID_MTI, MIPS_24K, -1, -1, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "24K" },
+ MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
+ MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7,
+ 0, "24K" },
{ MIPS_PRID_CID_MTI, MIPS_24KE, -1, -1, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "24KE" },
+ MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
+ MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7,
+ 0, "24KE" },
{ MIPS_PRID_CID_MTI, MIPS_34K, -1, -1, -1, 0,
- MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "34K" },
+ MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
+ MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7,
+ 0, "34K" },
{ MIPS_PRID_CID_MTI, MIPS_74K, -1, -1, -1, 0,
- MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "74K" },
+ MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
+ MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7,
+ 0, "74K" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1000, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0,
@@ -467,88 +487,99 @@
{ MIPS_PRID_CID_RMI, MIPS_XLR732B, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
- MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
- MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7,
CIDFL_RMI_TYPE_XLR|MIPS_CIDFL_RMI_CPUS(8,4)|MIPS_CIDFL_RMI_L2(2MB),
"XLR732B" },
{ MIPS_PRID_CID_RMI, MIPS_XLR732C, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
- MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
- MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7,
CIDFL_RMI_TYPE_XLR|MIPS_CIDFL_RMI_CPUS(8,4)|MIPS_CIDFL_RMI_L2(2MB),
"XLR732C" },
{ MIPS_PRID_CID_RMI, MIPS_XLS616, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
- MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
- MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7,
CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(4,4)|MIPS_CIDFL_RMI_L2(1MB),
"XLS616" },
{ MIPS_PRID_CID_RMI, MIPS_XLS416, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
- MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
- MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7,
CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(4,4)|MIPS_CIDFL_RMI_L2(1MB),
"XLS416" },
{ MIPS_PRID_CID_RMI, MIPS_XLS408, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
- MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
- MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7,
CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(1MB),
"XLS408" },
{ MIPS_PRID_CID_RMI, MIPS_XLS408LITE, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
- MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
- MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7,
CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(1MB),
"XLS408lite" },
{ MIPS_PRID_CID_RMI, MIPS_XLS404LITE, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
- MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
- MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7,
CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(1,4)|MIPS_CIDFL_RMI_L2(512KB),
"XLS404lite" },
{ MIPS_PRID_CID_RMI, MIPS_XLS208, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
- MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
- MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7,
CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(512KB),
"XLS208" },
{ MIPS_PRID_CID_RMI, MIPS_XLS204, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
- MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
- MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7,
CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(1,4)|MIPS_CIDFL_RMI_L2(256KB),
"XLS204" },
{ MIPS_PRID_CID_RMI, MIPS_XLS108, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
- MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
- MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7,
CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(512KB),
"XLS108" },
{ MIPS_PRID_CID_RMI, MIPS_XLS104, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
- MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
- MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ MIPS_CP0FL_USE |
+ MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7,
CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(1,4)|MIPS_CIDFL_RMI_L2(256KB),
"XLS104" },
