Module Name: src
Committed By: matt
Date: Fri Apr 29 06:34:18 UTC 2011
Modified Files:
src/gnu/dist/binutils/bfd [matt-nb5-mips64]: aoutx.h archures.c
bfd-in2.h cpu-mips.c elfxx-mips.c
src/gnu/dist/binutils/binutils [matt-nb5-mips64]: readelf.c
src/gnu/dist/binutils/gas/config [matt-nb5-mips64]: tc-mips.c
src/gnu/dist/binutils/gas/doc [matt-nb5-mips64]: c-mips.texi
src/gnu/dist/binutils/gas/testsuite/gas/mips [matt-nb5-mips64]:
mips.exp
src/gnu/dist/binutils/include/elf [matt-nb5-mips64]: mips.h
src/gnu/dist/binutils/include/opcode [matt-nb5-mips64]: mips.h
src/gnu/dist/binutils/opcodes [matt-nb5-mips64]: mips-dis.c mips-opc.c
Added Files:
src/gnu/dist/binutils/gas/testsuite/gas/mips [matt-nb5-mips64]:
xlr-ext.d xlr-ext.s
Log Message:
Integrate MIPS XLR support from
http://sourceware.org/ml/binutils/2009-01/msg00383.html
To generate a diff of this commit:
cvs rdiff -u -r1.1.1.3 -r1.1.1.3.32.1 src/gnu/dist/binutils/bfd/aoutx.h \
src/gnu/dist/binutils/bfd/archures.c src/gnu/dist/binutils/bfd/bfd-in2.h \
src/gnu/dist/binutils/bfd/cpu-mips.c
cvs rdiff -u -r1.1.1.3.32.1 -r1.1.1.3.32.2 \
src/gnu/dist/binutils/bfd/elfxx-mips.c
cvs rdiff -u -r1.2 -r1.2.32.1 src/gnu/dist/binutils/binutils/readelf.c
cvs rdiff -u -r1.6 -r1.6.32.1 src/gnu/dist/binutils/gas/config/tc-mips.c
cvs rdiff -u -r1.1.1.3 -r1.1.1.3.32.1 \
src/gnu/dist/binutils/gas/doc/c-mips.texi
cvs rdiff -u -r1.1.1.3 -r1.1.1.3.32.1 \
src/gnu/dist/binutils/gas/testsuite/gas/mips/mips.exp
cvs rdiff -u -r0 -r1.1.2.1 \
src/gnu/dist/binutils/gas/testsuite/gas/mips/xlr-ext.d \
src/gnu/dist/binutils/gas/testsuite/gas/mips/xlr-ext.s
cvs rdiff -u -r1.1.1.3 -r1.1.1.3.32.1 \
src/gnu/dist/binutils/include/elf/mips.h
cvs rdiff -u -r1.1.1.3 -r1.1.1.3.32.1 \
src/gnu/dist/binutils/include/opcode/mips.h
cvs rdiff -u -r1.1.1.3 -r1.1.1.3.32.1 \
src/gnu/dist/binutils/opcodes/mips-dis.c
cvs rdiff -u -r1.1.1.3.32.3 -r1.1.1.3.32.4 \
src/gnu/dist/binutils/opcodes/mips-opc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/gnu/dist/binutils/bfd/aoutx.h
diff -u src/gnu/dist/binutils/bfd/aoutx.h:1.1.1.3 src/gnu/dist/binutils/bfd/aoutx.h:1.1.1.3.32.1
--- src/gnu/dist/binutils/bfd/aoutx.h:1.1.1.3 Thu Feb 2 20:43:24 2006
+++ src/gnu/dist/binutils/bfd/aoutx.h Fri Apr 29 06:34:17 2011
@@ -796,6 +796,7 @@
case bfd_mach_mipsisa64:
case bfd_mach_mipsisa64r2:
case bfd_mach_mips_sb1:
+ case bfd_mach_mips_xlr:
/* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
arch_flags = M_MIPS2;
break;
Index: src/gnu/dist/binutils/bfd/archures.c
diff -u src/gnu/dist/binutils/bfd/archures.c:1.1.1.3 src/gnu/dist/binutils/bfd/archures.c:1.1.1.3.32.1
--- src/gnu/dist/binutils/bfd/archures.c:1.1.1.3 Thu Feb 2 20:43:27 2006
+++ src/gnu/dist/binutils/bfd/archures.c Fri Apr 29 06:34:17 2011
@@ -155,6 +155,7 @@
.#define bfd_mach_mips16 16
.#define bfd_mach_mips5 5
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
+.#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
.#define bfd_mach_mipsisa64 64
Index: src/gnu/dist/binutils/bfd/bfd-in2.h
diff -u src/gnu/dist/binutils/bfd/bfd-in2.h:1.1.1.3 src/gnu/dist/binutils/bfd/bfd-in2.h:1.1.1.3.32.1
--- src/gnu/dist/binutils/bfd/bfd-in2.h:1.1.1.3 Thu Feb 2 20:43:34 2006
+++ src/gnu/dist/binutils/bfd/bfd-in2.h Fri Apr 29 06:34:17 2011
@@ -1600,6 +1600,7 @@
#define bfd_mach_mips16 16
#define bfd_mach_mips5 5
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
+#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mipsisa64 64
Index: src/gnu/dist/binutils/bfd/cpu-mips.c
diff -u src/gnu/dist/binutils/bfd/cpu-mips.c:1.1.1.3 src/gnu/dist/binutils/bfd/cpu-mips.c:1.1.1.3.32.1
--- src/gnu/dist/binutils/bfd/cpu-mips.c:1.1.1.3 Thu Feb 2 20:44:45 2006
+++ src/gnu/dist/binutils/bfd/cpu-mips.c Fri Apr 29 06:34:17 2011
@@ -86,6 +86,7 @@
I_mipsisa64,
I_mipsisa64r2,
I_sb1,
+ I_xlr
};
#define NN(index) (&arch_info_struct[(index) + 1])
@@ -118,7 +119,9 @@
N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
- N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
+ N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
+ N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, 0)
+
};
/* The default architecture is mips:3000, but with a machine number of
Index: src/gnu/dist/binutils/bfd/elfxx-mips.c
diff -u src/gnu/dist/binutils/bfd/elfxx-mips.c:1.1.1.3.32.1 src/gnu/dist/binutils/bfd/elfxx-mips.c:1.1.1.3.32.2
--- src/gnu/dist/binutils/bfd/elfxx-mips.c:1.1.1.3.32.1 Sat Sep 5 03:10:39 2009
+++ src/gnu/dist/binutils/bfd/elfxx-mips.c Fri Apr 29 06:34:17 2011
@@ -4669,6 +4669,9 @@
case E_MIPS_MACH_SB1:
return bfd_mach_mips_sb1;
+ case E_MIPS_MACH_XLR:
+ return bfd_mach_mips_xlr;
+
default:
switch (flags & EF_MIPS_ARCH)
{
@@ -7955,6 +7958,10 @@
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
break;
+ case bfd_mach_mips_xlr:
+ val = E_MIPS_ARCH_64 | E_MIPS_MACH_XLR;
+ break;
+
case bfd_mach_mipsisa32:
val = E_MIPS_ARCH_32;
break;
@@ -9614,6 +9621,7 @@
/* MIPS64 extensions. */
{ bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
{ bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
+ { bfd_mach_mips_xlr, bfd_mach_mipsisa64 },
/* MIPS V extensions. */
{ bfd_mach_mipsisa64, bfd_mach_mips5 },
Index: src/gnu/dist/binutils/binutils/readelf.c
diff -u src/gnu/dist/binutils/binutils/readelf.c:1.2 src/gnu/dist/binutils/binutils/readelf.c:1.2.32.1
--- src/gnu/dist/binutils/binutils/readelf.c:1.2 Fri Feb 17 13:14:25 2006
+++ src/gnu/dist/binutils/binutils/readelf.c Fri Apr 29 06:34:17 2011
@@ -2043,6 +2043,7 @@
case E_MIPS_MACH_5500: strcat (buf, ", 5500"); break;
case E_MIPS_MACH_SB1: strcat (buf, ", sb1"); break;
case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
+ case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
case 0:
/* We simply ignore the field in this case to avoid confusion:
MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
Index: src/gnu/dist/binutils/gas/config/tc-mips.c
diff -u src/gnu/dist/binutils/gas/config/tc-mips.c:1.6 src/gnu/dist/binutils/gas/config/tc-mips.c:1.6.32.1
--- src/gnu/dist/binutils/gas/config/tc-mips.c:1.6 Thu Feb 2 22:03:55 2006
+++ src/gnu/dist/binutils/gas/config/tc-mips.c Fri Apr 29 06:34:17 2011
@@ -5426,6 +5426,43 @@
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
break;
+ case M_MSGSND:
+ {
+ unsigned long temp = (treg << 16) | (0x01);
+ macro_build (NULL, "c2", "C", temp);
+ }
+ /* AT is not used, just return */
+ return;
+
+ case M_MSGLD:
+ {
+ unsigned long temp = (0x02);
+ macro_build (NULL, "c2", "C", temp);
+ }
+ /* AT is not used, just return */
+ return;
+
+ case M_MSGLD_T:
+ {
+ unsigned long temp = (treg << 16) | (0x02);
+ macro_build (NULL, "c2", "C", temp);
+ }
+ /* AT is not used, just return */
+ return;
+
+ case M_MSGWAIT:
+ macro_build (NULL, "c2", "C", 3);
+ /* AT is not used, just return */
+ return;
+
+ case M_MSGWAIT_T:
+ {
+ unsigned long temp = (treg << 16) | 0x03;
+ macro_build (NULL, "c2", "C", temp);
+ }
+ /* AT is not used, just return */
+ return;
+
case M_J_A:
/* The j instruction may not be used in PIC code, since it
requires an absolute address. We convert it to a b
@@ -13785,6 +13822,9 @@
/* Broadcom SB-1 CPU core */
{ "sb1", 0, ISA_MIPS64, CPU_SB1 },
+ /* RMI Xlr */
+ { "xlr", 0, ISA_MIPS64, CPU_XLR },
+
/* End marker */
{ NULL, 0, 0, 0 }
};
Index: src/gnu/dist/binutils/gas/doc/c-mips.texi
diff -u src/gnu/dist/binutils/gas/doc/c-mips.texi:1.1.1.3 src/gnu/dist/binutils/gas/doc/c-mips.texi:1.1.1.3.32.1
--- src/gnu/dist/binutils/gas/doc/c-mips.texi:1.1.1.3 Thu Feb 2 20:59:33 2006
+++ src/gnu/dist/binutils/gas/doc/c-mips.texi Fri Apr 29 06:34:17 2011
@@ -191,7 +191,8 @@
10000,
12000,
mips32-4k,
-sb1
+sb1,
+xlr
@end quotation
@item -mtune=@var{cpu}
Index: src/gnu/dist/binutils/gas/testsuite/gas/mips/mips.exp
diff -u src/gnu/dist/binutils/gas/testsuite/gas/mips/mips.exp:1.1.1.3 src/gnu/dist/binutils/gas/testsuite/gas/mips/mips.exp:1.1.1.3.32.1
--- src/gnu/dist/binutils/gas/testsuite/gas/mips/mips.exp:1.1.1.3 Thu Feb 2 21:05:41 2006
+++ src/gnu/dist/binutils/gas/testsuite/gas/mips/mips.exp Fri Apr 29 06:34:17 2011
@@ -382,7 +382,8 @@
mips_arch_create sb1 64 mips64 { mips3d } \
{ -march=sb1 -mtune=sb1 } { -mmips:sb1 } \
{ mipsisa64sb1-*-* mipsisa64sb1el-*-* }
-
+mips_arch_create xlr 64 mips64 {} \
+ { -march=xlr -mtune=xlr } { -mmips:xlr }
#
# And now begin the actual tests!
@@ -575,6 +576,7 @@
run_dump_test "mips64-mdmx"
run_dump_test "sb1-ext-mdmx"
run_dump_test "sb1-ext-ps"
+ run_dump_test "xlr-ext"
}
run_dump_test "relax"
Index: src/gnu/dist/binutils/include/elf/mips.h
diff -u src/gnu/dist/binutils/include/elf/mips.h:1.1.1.3 src/gnu/dist/binutils/include/elf/mips.h:1.1.1.3.32.1
--- src/gnu/dist/binutils/include/elf/mips.h:1.1.1.3 Thu Feb 2 21:11:53 2006
+++ src/gnu/dist/binutils/include/elf/mips.h Fri Apr 29 06:34:18 2011
@@ -209,6 +209,7 @@
#define E_MIPS_MACH_4120 0x00870000
#define E_MIPS_MACH_4111 0x00880000
#define E_MIPS_MACH_SB1 0x008a0000
+#define E_MIPS_MACH_XLR 0x008c0000
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
#define E_MIPS_MACH_9000 0x00990000
Index: src/gnu/dist/binutils/include/opcode/mips.h
diff -u src/gnu/dist/binutils/include/opcode/mips.h:1.1.1.3 src/gnu/dist/binutils/include/opcode/mips.h:1.1.1.3.32.1
--- src/gnu/dist/binutils/include/opcode/mips.h:1.1.1.3 Thu Feb 2 21:12:25 2006
+++ src/gnu/dist/binutils/include/opcode/mips.h Fri Apr 29 06:34:18 2011
@@ -410,6 +410,9 @@
#define INSN_ISA32R2 0x00000080
#define INSN_ISA64R2 0x00000100
+/* Masks used for Chip specific instructions. */
+#define INSN_CHIP_MASK 0xc3ff0820
+
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x0000f000
@@ -442,6 +445,8 @@
#define INSN_5400 0x01000000
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
+/* RMI Xlr instruction. */
+#define INSN_XLR 0x00000020
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -489,6 +494,8 @@
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
+#define CPU_XLR 887682 /* decimal 'XLR' */
+
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
@@ -510,6 +517,7 @@
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
+ || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
|| 0) /* Please keep this term for easier source merging. */
/* This is a list of macro expanded instructions.
@@ -640,6 +648,11 @@
M_LWR_A,
M_LWR_AB,
M_LWU_AB,
+ M_MSGSND,
+ M_MSGLD,
+ M_MSGLD_T,
+ M_MSGWAIT,
+ M_MSGWAIT_T,
M_MOVE,
M_MUL,
M_MUL_I,
Index: src/gnu/dist/binutils/opcodes/mips-dis.c
diff -u src/gnu/dist/binutils/opcodes/mips-dis.c:1.1.1.3 src/gnu/dist/binutils/opcodes/mips-dis.c:1.1.1.3.32.1
--- src/gnu/dist/binutils/opcodes/mips-dis.c:1.1.1.3 Thu Feb 2 21:16:09 2006
+++ src/gnu/dist/binutils/opcodes/mips-dis.c Fri Apr 29 06:34:18 2011
@@ -185,6 +185,7 @@
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
{ 4, 1, "c0_contextconfig" },
+ { 4, 2, "c0_userlocal" },
{ 5, 1, "c0_pagegrain" },
{ 12, 1, "c0_intctl" },
{ 12, 2, "c0_srsctl" },
@@ -272,6 +273,63 @@
{ 29, 2, "c0_taghi_d" },
{ 29, 3, "c0_datahi_d" },
};
+
+/* Xlr cop0 register names. */
+static const char * const mips_cp0_names_xlr[32] = {
+ "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
+ "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
+ "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
+ "c0_status", "c0_cause", "c0_epc", "c0_prid",
+ "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
+ "c0_xcontext", "$21", "c0_osscratch", "c0_debug",
+ "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
+ "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
+};
+
+/* XLR's CP0 Select Registers. */
+
+static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
+ { 9, 6, "c0_extintreq" },
+ { 9, 7, "c0_extintmask" },
+ { 15, 1, "c0_ebase" },
+ { 16, 1, "c0_config1" },
+ { 16, 2, "c0_config2" },
+ { 16, 3, "c0_config3" },
+ { 16, 7, "c0_procid2" },
+ { 18, 1, "c0_watchlo,1" },
+ { 18, 2, "c0_watchlo,2" },
+ { 18, 3, "c0_watchlo,3" },
+ { 18, 4, "c0_watchlo,4" },
+ { 18, 5, "c0_watchlo,5" },
+ { 18, 6, "c0_watchlo,6" },
+ { 18, 7, "c0_watchlo,7" },
+ { 19, 1, "c0_watchhi,1" },
+ { 19, 2, "c0_watchhi,2" },
+ { 19, 3, "c0_watchhi,3" },
+ { 19, 4, "c0_watchhi,4" },
+ { 19, 5, "c0_watchhi,5" },
+ { 19, 6, "c0_watchhi,6" },
+ { 19, 7, "c0_watchhi,7" },
+ { 22, 1, "c0_osscratch,1" },
+ { 22, 2, "c0_osscratch,2" },
+ { 22, 3, "c0_osscratch,3" },
+ { 22, 4, "c0_osscratch,4" },
+ { 22, 5, "c0_osscratch,5" },
+ { 22, 6, "c0_osscratch,6" },
+ { 22, 7, "c0_osscratch,7" },
+ { 25, 1, "c0_perfcnt,1" },
+ { 25, 2, "c0_perfcnt,2" },
+ { 25, 3, "c0_perfcnt,3" },
+ { 25, 4, "c0_perfcnt,4" },
+ { 25, 5, "c0_perfcnt,5" },
+ { 25, 6, "c0_perfcnt,6" },
+ { 25, 7, "c0_perfcnt,7" },
+ { 27, 1, "c0_cacheerr,1" },
+ { 27, 2, "c0_cacheerr,2" },
+ { 27, 3, "c0_cacheerr,3" },
+ { 28, 1, "c0_datalo" },
+ { 29, 1, "c0_datahi" }
+};
static const char * const mips_hwr_names_numeric[32] = {
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
@@ -285,7 +343,7 @@
"$4", "$5", "$6", "$7",
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
- "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
+ "$24", "$25", "$26", "$27", "$28", "hwr_userlocal", "$30", "$31"
};
struct mips_abi_choice {
@@ -396,6 +454,12 @@
mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
mips_hwr_names_numeric },
+ { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
+ ISA_MIPS64 | INSN_XLR,
+ mips_cp0_names_xlr,
+ mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
+ mips_hwr_names_numeric },
+
/* This entry, mips16, is here only for ISA/processor selection; do
not print its name. */
{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
Index: src/gnu/dist/binutils/opcodes/mips-opc.c
diff -u src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.3 src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.4
--- src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.3 Wed Feb 17 08:41:43 2010
+++ src/gnu/dist/binutils/opcodes/mips-opc.c Fri Apr 29 06:34:18 2011
@@ -109,6 +109,7 @@
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
+#define XLR INSN_XLR
#define G1 (T3 \
)
@@ -471,6 +472,7 @@
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
+{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0, 0, XLR },
{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 },
{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
@@ -639,6 +641,9 @@
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
+{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
+{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
+{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
@@ -742,6 +747,7 @@
{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 },
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR },
{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -782,6 +788,11 @@
{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
/* move is at the top of the table. */
{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
+{"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR },
+{"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR },
+{"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR },
+{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR },
+{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR },
{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4 },
{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4 },
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 },
@@ -802,11 +813,10 @@
/* mthc2 is at the bottom of the table. */
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t|RD_s, 0, I64 },
-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, WR_t|RD_s, 0, I64 },
{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_t, 0, XLR },
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
@@ -1077,6 +1087,9 @@
{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|N55 },
{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
+{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
+{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
+{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
@@ -1200,11 +1213,6 @@
{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
-/* RMI Coprocessor 2 ops */
-{"msgsnd", "t", 0x4a000001, 0xffe0ffff, COD|RD_t|WR_C2, 0, I64 },
-{"msgld", "t", 0x4a000002, 0xffe0ffff, COD|RD_t|WR_C2, 0, I64 },
-{"msgwait", "t", 0x4a000003, 0xffe0ffff, COD|RD_t|WR_C2, 0, I64 },
-
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
Added files:
Index: src/gnu/dist/binutils/gas/testsuite/gas/mips/xlr-ext.d
diff -u /dev/null src/gnu/dist/binutils/gas/testsuite/gas/mips/xlr-ext.d:1.1.2.1
--- /dev/null Fri Apr 29 06:34:18 2011
+++ src/gnu/dist/binutils/gas/testsuite/gas/mips/xlr-ext.d Fri Apr 29 06:34:17 2011
@@ -0,0 +1,20 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:xlr
+#name: XLRs native MIPS64 extensions
+#as: -march=xlr
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 3c000000 lui zero,0x0
+0+0004 <[^>]*> 8c010001 lw at,1\(zero\)
+0+0008 <[^>]*> 8c020002 lw v0,2\(zero\)
+0+000c <[^>]*> 70221838 daddwc v1,at,v0
+0+0010 <[^>]*> 70230010 ldaddw v1,at
+0+0014 <[^>]*> 70230011 ldaddwu v1,at
+0+0018 <[^>]*> 70230012 ldaddd v1,at
+0+001c <[^>]*> 70230014 swapw v1,at
+0+0020 <[^>]*> 70230015 swapwu v1,at
+0+0024 <[^>]*> 4a000003 c2 0x3
+0+0028 <[^>]*> 4a000002 c2 0x2
+0+002c <[^>]*> 4a000001 c2 0x1
+ \.\.\.
Index: src/gnu/dist/binutils/gas/testsuite/gas/mips/xlr-ext.s
diff -u /dev/null src/gnu/dist/binutils/gas/testsuite/gas/mips/xlr-ext.s:1.1.2.1
--- /dev/null Fri Apr 29 06:34:18 2011
+++ src/gnu/dist/binutils/gas/testsuite/gas/mips/xlr-ext.s Fri Apr 29 06:34:17 2011
@@ -0,0 +1,27 @@
+# Source file used to test XLR's assembler instructions
+
+ .set noreorder
+ .set noat
+
+ .globl text_label .text
+text_label:
+
+ lui $0, 0x00
+ lw $1, 0x01
+ lw $2, 0x02
+
+ daddwc $3, $1, $2
+
+ ldaddw $3, $1
+ ldaddwu $3, $1
+ ldaddd $3, $1
+
+ swapw $3, $1
+ swapwu $3, $1
+
+ msgwait
+ msgld $0
+ msgsnd $0
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
