Module Name: src
Committed By: macallan
Date: Wed May 4 04:33:37 UTC 2011
Modified Files:
src/sys/arch/powerpc/include: cpu.h
Log Message:
add access functions for the Instruction Cache Throttling Control register
found in 750 and newer CPUs
To generate a diff of this commit:
cvs rdiff -u -r1.75 -r1.76 src/sys/arch/powerpc/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/include/cpu.h
diff -u src/sys/arch/powerpc/include/cpu.h:1.75 src/sys/arch/powerpc/include/cpu.h:1.76
--- src/sys/arch/powerpc/include/cpu.h:1.75 Wed Feb 16 18:42:33 2011
+++ src/sys/arch/powerpc/include/cpu.h Wed May 4 04:33:37 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.75 2011/02/16 18:42:33 matt Exp $ */
+/* $NetBSD: cpu.h,v 1.76 2011/05/04 04:33:37 macallan Exp $ */
/*
* Copyright (C) 1999 Wolfgang Solfrank.
@@ -322,6 +322,28 @@
return (cnt);
}
+/*
+ * functions to access the G3's cache throttling register
+ * bits 1 - 9 specify additional waits on cache acess
+ * bit 0 enables cache throttling
+ */
+
+static __inline int
+mfictc(void)
+{
+ int reg;
+
+ __asm ("mfspr %0,1019" : "=r"(reg));
+ return reg;
+}
+
+static __inline void
+mtictc(uint32_t reg)
+{
+
+ __asm ("mtspr 1019,%0" :: "r"(reg));
+}
+
#define CLKF_USERMODE(frame) (((frame)->cf_srr1 & PSL_PR) != 0)
#define CLKF_PC(frame) ((frame)->cf_srr0)
#define CLKF_INTR(frame) ((frame)->cf_idepth > 0)
