Module Name: src
Committed By: tsutsui
Date: Sat May 7 17:52:43 UTC 2011
Modified Files:
src/sys/arch/mips/mips: locore_mips1.S mipsX_subr.S
Log Message:
Remove trailing spaces and tabs.
To generate a diff of this commit:
cvs rdiff -u -r1.79 -r1.80 src/sys/arch/mips/mips/locore_mips1.S
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/locore_mips1.S
diff -u src/sys/arch/mips/mips/locore_mips1.S:1.79 src/sys/arch/mips/mips/locore_mips1.S:1.80
--- src/sys/arch/mips/mips/locore_mips1.S:1.79 Sat May 7 17:47:34 2011
+++ src/sys/arch/mips/mips/locore_mips1.S Sat May 7 17:52:43 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips1.S,v 1.79 2011/05/07 17:47:34 tsutsui Exp $ */
+/* $NetBSD: locore_mips1.S,v 1.80 2011/05/07 17:52:43 tsutsui Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -94,7 +94,7 @@
lui k1, %hi(CPUVAR(PMAP_SEG0TAB)) #01: k1=hi of seg0tab
bltz k0, 1f # R3000 chip bug
PTR_SRL k0, 1*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2)#03: k0=seg offset (almost)
- PTR_L k1, %lo(CPUVAR(PMAP_SEG0TAB))(k1) #04: k1=seg0tab
+ PTR_L k1, %lo(CPUVAR(PMAP_SEG0TAB))(k1) #04: k1=seg0tab
andi k0, (NBPG-(1<<PTR_SCALESHIFT)) #07: k0=seg offset (mask 0x3)
PTR_ADDU k1, k0 #08: k1=seg entry address
PTR_L k1, 0(k1) #09: k1=seg entry
@@ -979,9 +979,9 @@
END(MIPSX(systemcall))
/*----------------------------------------------------------------------------
- *
+ *
* R3000 TLB exception handlers
- *
+ *
*----------------------------------------------------------------------------
*/
@@ -1198,9 +1198,9 @@
sll a0, MIPS1_TLB_INDEX_SHIFT
mtc0 a0, MIPS_COP_0_TLB_INDEX # Set the index register
nop
- mtc0 t2, MIPS_COP_0_TLB_HI
- mtc0 t3, MIPS_COP_0_TLB_LOW
-
+ mtc0 t2, MIPS_COP_0_TLB_HI
+ mtc0 t3, MIPS_COP_0_TLB_LOW
+
tlbwi # Write to the TLB entry
mtc0 t0, MIPS_COP_0_TLB_HI # restore PID
@@ -1370,7 +1370,7 @@
3:
and t1, t2, t0 # see if this asid was recorded
sltu t1, t1, ta3 # t1 = t1 < 1 (aka t1 == 0)
- addu v0, t1 # v0 += t1
+ addu v0, t1 # v0 += t1
or t2, t0 # or in the new ASID bit
4:
@@ -1393,7 +1393,7 @@
*
* mipsN_tlb_enter --
*
- * Entr the
+ * Entr the
*
* mipsN_tlb_enter(size_t tlb_index, vaddr_t va_asid, uint32_t tlb_lo)
*
@@ -1467,7 +1467,7 @@
move a1, MIPS_CURLWP
# Call the routine specified by cpu_setfunc()
- jalr s0
+ jalr s0
move a0, s1
# Return to user (won't happen if a kernel thread)
@@ -1526,7 +1526,7 @@
# Call the routine specified by cpu_setfunc()
PTR_LA ra, MIPSX(user_return)
- jr s0
+ jr s0
move a0, s1
END(MIPSX(setfunc_trampoline))
@@ -1627,20 +1627,20 @@
#else /* !ENABLE_MIPS_TX3900 */
/*
* The differences between R3900 and R3000.
- * 1. Cache system
- * Physical-index physical-tag
+ * 1. Cache system
+ * Physical-index physical-tag
* fixed line-size
* refil-size 4/8/16/32 words (set in config register)
- * TX3912
+ * TX3912
* Write-through
* I-cache 4KB/16B direct mapped (256line)
* D-cache 1KB/4B 2-way sa (128line)
- * Cache snoop
+ * Cache snoop
* TX3922
* Write-through/write-back (set in config register)
- * I-cache 16KB/16B 2-way sa
+ * I-cache 16KB/16B 2-way sa
* D-cache 8KB/16B 2-way sa
- * Cache snoop
+ * Cache snoop
*
* 2. Coprocessor1
* 2.1 cache operation.
@@ -1669,7 +1669,7 @@
LEAF(MIPSX(wbflush))
.set push
.set mips2
- sync
+ sync
.set pop
j ra
nop
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.46 src/sys/arch/mips/mips/mipsX_subr.S:1.47
--- src/sys/arch/mips/mips/mipsX_subr.S:1.46 Fri Apr 29 22:16:49 2011
+++ src/sys/arch/mips/mips/mipsX_subr.S Sat May 7 17:52:43 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.46 2011/04/29 22:16:49 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.47 2011/05/07 17:52:43 tsutsui Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -935,7 +935,7 @@
* Interrupts handled, restore registers and return from the interrupt.
* First, clear interrupt enable
*/
- mfc0 v0, MIPS_COP_0_STATUS # read it
+ mfc0 v0, MIPS_COP_0_STATUS # read it
xor v0, MIPS_SR_INT_IE # disable interrupts
mtc0 v0, MIPS_COP_0_STATUS # write it
COP0_SYNC
@@ -1225,7 +1225,7 @@
#else
lui v0, %hi(~(MIPS_SR_COP_1_BIT|MIPS_SR_EXL|MIPS_SR_KSU_MASK))
addiu v0, %lo(~(MIPS_SR_COP_1_BIT|MIPS_SR_EXL|MIPS_SR_KSU_MASK))
- and v0, v1
+ and v0, v1
#endif
mtc0 v0, MIPS_COP_0_STATUS # write new status
COP0_SYNC
@@ -1307,7 +1307,7 @@
REG_S s6, CALLFRAME_SIZ+TF_REG_S6(sp) # $22
REG_S s7, CALLFRAME_SIZ+TF_REG_S7(sp) # $23
REG_S s8, CALLFRAME_SIZ+TF_REG_S8(sp) # $30
- mfc0 t0, MIPS_COP_0_STATUS #
+ mfc0 t0, MIPS_COP_0_STATUS #
or t0, MIPS_SR_INT_IE # enable interrupts
DYNAMIC_STATUS_MASK(t0, t1) # machine dependent masking
mtc0 t0, MIPS_COP_0_STATUS # enable interrupts (spl0)
@@ -2095,7 +2095,7 @@
sll a2, LONG_SCALESHIFT # make an index for the bitmap
_SLLV t0, ta3, t0 # t0 is mask (ta3 == 1)
- PTR_ADDU a2, a0 # index into the bitmap
+ PTR_ADDU a2, a0 # index into the bitmap
beq a2, ta2, 3f # is the desired cell loaded?
nop # yes, don't reload it
beqz ta2, 2f # have we ever loaded it?
@@ -2159,7 +2159,7 @@
* If it's already where we want, no reason to invalidate it.
*/
beq v0, a0, 2f # already where we want it?
- nop
+ nop
/*
* Make an
@@ -2225,7 +2225,7 @@
move a1, MIPS_CURLWP
# Call the routine specified by cpu_setfunc()
- jalr s0
+ jalr s0
move a0, s1
#
@@ -2303,7 +2303,7 @@
# Call the routine specified by cpu_setfunc()
# and return directly to user_return
PTR_LA ra, MIPSX(user_return)
- jr s0
+ jr s0
move a0, s1
END(MIPSX(setfunc_trampoline))
