Module Name:    src
Committed By:   phx
Date:           Sun May 29 18:06:45 UTC 2011

Modified Files:
        src/sys/arch/sandpoint/stand/altboot: brdsetup.c skg.c

Log Message:
When PPCBoot supports the SKnet interface it will configure it to automatically
byte-reverse all descriptors by setting a vendor-specific bit in PCI config
space. We have to clear that bit to make sure our driver can send and
receive.


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/sandpoint/stand/altboot/brdsetup.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/sandpoint/stand/altboot/skg.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/sandpoint/stand/altboot/brdsetup.c
diff -u src/sys/arch/sandpoint/stand/altboot/brdsetup.c:1.17 src/sys/arch/sandpoint/stand/altboot/brdsetup.c:1.18
--- src/sys/arch/sandpoint/stand/altboot/brdsetup.c:1.17	Tue Apr 26 08:08:39 2011
+++ src/sys/arch/sandpoint/stand/altboot/brdsetup.c	Sun May 29 18:06:45 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: brdsetup.c,v 1.17 2011/04/26 08:08:39 phx Exp $ */
+/* $NetBSD: brdsetup.c,v 1.18 2011/05/29 18:06:45 phx Exp $ */
 
 /*-
  * Copyright (c) 2008 The NetBSD Foundation, Inc.
@@ -125,11 +125,23 @@
 	NULL, NULL, NULL, NULL }, /* must be the last */
 };
 
+/* Iomega StorCenter MC68HC908 microcontroller data packet */
+#define IOMEGA_POWER		0
+#define IOMEGA_LED		1
+#define IOMEGA_FLASH_RATE	2
+#define IOMEGA_FAN		3
+#define IOMEGA_HIGH_TEMP	4
+#define IOMEGA_LOW_TEMP		5
+#define IOMEGA_ID		6
+#define IOMEGA_CHECKSUM		7
+#define IOMEGA_PACKETSIZE	8
+
 static struct brdprop *brdprop;
 static uint32_t ticks_per_sec, ns_per_tick;
 
 static void brdfixup(void);
 static void setup(void);
+static int send_iomega(int, int, int, int, int, int, uint8_t *);
 static inline uint32_t mfmsr(void);
 static inline void mtmsr(uint32_t);
 static inline uint32_t cputype(void);
@@ -693,6 +705,7 @@
 
 	init_uart(uart2base, 9600, LCR_8BITS | LCR_PNONE);
 	/* illuminate LEDs */
+	(void)send_iomega('b', 'd', 2, 'a', 60, 50, NULL);
 }
 
 void
@@ -877,6 +890,46 @@
 	uart1base = savedbase;
 }
 
+static int
+send_iomega(int power, int led, int rate, int fan, int high, int low,
+    uint8_t *st)
+{
+	unsigned i, savedbase;
+	static uint8_t cur_state[IOMEGA_PACKETSIZE];
+	uint8_t buf[IOMEGA_PACKETSIZE];
+
+	buf[IOMEGA_POWER] =
+	    power >= 0 ? power : cur_state[IOMEGA_POWER];
+	buf[IOMEGA_LED] =
+	    led >= 0 ? led : cur_state[IOMEGA_LED];
+	buf[IOMEGA_FLASH_RATE] =
+	    rate >= 0 ? rate : cur_state[IOMEGA_FLASH_RATE];
+	buf[IOMEGA_FAN] =
+	    fan >= 0 ? fan : cur_state[IOMEGA_FAN];
+	buf[IOMEGA_HIGH_TEMP] =
+	    high >= 0 ? high : cur_state[IOMEGA_HIGH_TEMP];
+	buf[IOMEGA_LOW_TEMP] =
+	    low >= 0 ? low : cur_state[IOMEGA_LOW_TEMP];
+	buf[IOMEGA_ID] = 7;	/* host id */
+	buf[IOMEGA_CHECKSUM] = (buf[IOMEGA_POWER] + buf[IOMEGA_LED] +
+	    buf[IOMEGA_FLASH_RATE] + buf[IOMEGA_FAN] +
+	    buf[IOMEGA_HIGH_TEMP] + buf[IOMEGA_LOW_TEMP] +
+	    buf[IOMEGA_ID]) & 0x7f;
+
+	savedbase = uart1base;
+	uart1base = uart2base;
+	for (i = 0; i < IOMEGA_PACKETSIZE; i++)
+		putchar(buf[i]);
+	for (i = 0; i < IOMEGA_PACKETSIZE; i++)
+		buf[i] = getchar();
+	uart1base = savedbase;
+	for (i = 0; i < IOMEGA_PACKETSIZE; i++)
+		printf("%02x", buf[i]);
+	printf("\n");
+
+	return 0;
+}
+
 void
 putchar(int c)
 {

Index: src/sys/arch/sandpoint/stand/altboot/skg.c
diff -u src/sys/arch/sandpoint/stand/altboot/skg.c:1.2 src/sys/arch/sandpoint/stand/altboot/skg.c:1.3
--- src/sys/arch/sandpoint/stand/altboot/skg.c:1.2	Thu Jan 27 17:38:04 2011
+++ src/sys/arch/sandpoint/stand/altboot/skg.c	Sun May 29 18:06:45 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: skg.c,v 1.2 2011/01/27 17:38:04 phx Exp $ */
+/* $NetBSD: skg.c,v 1.3 2011/05/29 18:06:45 phx Exp $ */
 
 /*-
  * Copyright (c) 2010 Frank Wille.
@@ -212,6 +212,10 @@
 	memset(l, 0, sizeof(struct local));
 	l->csr = DEVTOV(pcicfgread(tag, 0x10)); /* use mem space */
 
+	/* make sure the descriptor bytes are not reversed */
+	i = pcicfgread(tag, 0x44);
+	pcicfgwrite(tag, 0x44, i & ~4);
+
 	/* reset the chip */
 	CSR_WRITE_2(l, SK_CSR, CSR_SW_RESET);
 	CSR_WRITE_2(l, SK_CSR, CSR_MASTER_RESET);

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