Module Name: src
Committed By: matt
Date: Tue Jun 21 04:21:17 UTC 2011
Modified Files:
src/sys/arch/powerpc/booke: booke_machdep.c
src/sys/arch/powerpc/ibm4xx: cpu.c
src/sys/arch/powerpc/include: cpu.h
src/sys/arch/powerpc/oea: cpu_subr.c
Log Message:
Reap the ci_ev_soft* evcnts since every variant implements __HAVE_FAST_SOFTINTS
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/powerpc/booke/booke_machdep.c
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/powerpc/ibm4xx/cpu.c
cvs rdiff -u -r1.84 -r1.85 src/sys/arch/powerpc/include/cpu.h
cvs rdiff -u -r1.68 -r1.69 src/sys/arch/powerpc/oea/cpu_subr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/booke/booke_machdep.c
diff -u src/sys/arch/powerpc/booke/booke_machdep.c:1.9 src/sys/arch/powerpc/booke/booke_machdep.c:1.10
--- src/sys/arch/powerpc/booke/booke_machdep.c:1.9 Mon Jun 20 07:23:36 2011
+++ src/sys/arch/powerpc/booke/booke_machdep.c Tue Jun 21 04:21:16 2011
@@ -341,14 +341,6 @@
NULL, xname, "late clock");
evcnt_attach_dynamic_nozero(&cpu->cpu_ev_exec_trap_sync, EVCNT_TYPE_TRAP,
NULL, xname, "exec pages synced (trap)");
-#ifndef __HAVE_FAST_SOFTINTS
- evcnt_attach_dynamic_nozero(&ci->ci_ev_softclock, EVCNT_TYPE_INTR,
- NULL, xname, "soft clock");
- evcnt_attach_dynamic_nozero(&ci->ci_ev_softnet, EVCNT_TYPE_INTR,
- NULL, xname, "soft net");
- evcnt_attach_dynamic_nozero(&ci->ci_ev_softserial, EVCNT_TYPE_INTR,
- NULL, xname, "soft serial");
-#endif
evcnt_attach_dynamic_nozero(&ci->ci_ev_traps, EVCNT_TYPE_TRAP,
NULL, xname, "traps");
evcnt_attach_dynamic_nozero(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP,
Index: src/sys/arch/powerpc/ibm4xx/cpu.c
diff -u src/sys/arch/powerpc/ibm4xx/cpu.c:1.31 src/sys/arch/powerpc/ibm4xx/cpu.c:1.32
--- src/sys/arch/powerpc/ibm4xx/cpu.c:1.31 Sat Jun 18 08:21:20 2011
+++ src/sys/arch/powerpc/ibm4xx/cpu.c Tue Jun 21 04:21:16 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.31 2011/06/18 08:21:20 matt Exp $ */
+/* $NetBSD: cpu.c,v 1.32 2011/06/21 04:21:16 matt Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.31 2011/06/18 08:21:20 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.32 2011/06/21 04:21:16 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -55,29 +55,160 @@
u_int version;
u_int mask;
const char *name;
+ struct cache_info ci;
};
+
static const struct cputab models[] = {
- { PVR_401A1, 0xffff0000, "401A1" },
- { PVR_401B2, 0xffff0000, "401B21" },
- { PVR_401C2, 0xffff0000, "401C2" },
- { PVR_401D2, 0xffff0000, "401D2" },
- { PVR_401E2, 0xffff0000, "401E2" },
- { PVR_401F2, 0xffff0000, "401F2" },
- { PVR_401G2, 0xffff0000, "401G2" },
- { PVR_403, 0xffff0000, "403" },
- { PVR_405GP, 0xffff0000, "405GP" },
- { PVR_405GPR, 0xffff0000, "405GPr" },
- { PVR_405D5X1, 0xfffff000, "Xilinx Virtex II Pro" },
- { PVR_405D5X2, 0xfffff000, "Xilinx Virtex 4 FX" },
- { PVR_405EX, 0xffff0000, "405EX" },
- { 0, 0, NULL }
+ {
+ .version = PVR_401A1,
+ .mask = 0xffff0000,
+ .name = "401A1",
+ .ci = {
+ .dcache_size = 1024,
+ .dcache_line_size = 16,
+ .icache_size = 2848,
+ .icache_line_size = 16,
+ }
+ }, {
+ .version = PVR_401B2,
+ .mask = 0xffff0000,
+ .name = "401B21",
+ .ci = {
+ .dcache_size = 8192,
+ .dcache_line_size = 16,
+ .icache_size = 16384,
+ .icache_line_size = 16,
+ }
+ }, {
+ .version = PVR_401C2,
+ .mask = 0xffff0000,
+ .name = "401C2",
+ .ci = {
+ .dcache_size = 8192,
+ .dcache_line_size = 16,
+ .icache_size = 0,
+ .icache_line_size = 16,
+ }
+ }, {
+ .version = PVR_401D2,
+ .mask = 0xffff0000,
+ .name = "401D2",
+ .ci = {
+ .dcache_size = 2848,
+ .dcache_line_size = 16,
+ .icache_size = 4096,
+ .icache_line_size = 16,
+ }
+ }, {
+ .version = PVR_401E2,
+ .mask = 0xffff0000,
+ .name = "401E2",
+ .ci = {
+ .dcache_size = 0,
+ .dcache_line_size = 16,
+ .icache_size = 0,
+ .icache_line_size = 16,
+ }
+ }, {
+ .version = PVR_401F2,
+ .mask = 0xffff0000,
+ .name = "401F2",
+ .ci = {
+ .dcache_size = 2048,
+ .dcache_line_size = 16,
+ .icache_size = 2848,
+ .icache_line_size = 16,
+ }
+ }, {
+ .version = PVR_401G2,
+ .mask = 0xffff0000,
+ .name = "401G2",
+ .ci = {
+ .dcache_size = 2848,
+ .dcache_line_size = 16,
+ .icache_size = 8192,
+ .icache_line_size = 16,
+ }
+ }, {
+ .version = PVR_403,
+ .mask = 0xffff0000,
+ .name = "403",
+ .ci = {
+ .dcache_size = 8192,
+ .dcache_line_size = 16,
+ .icache_size = 16384,
+ .icache_line_size = 16,
+ }
+ }, {
+ .version = PVR_405GP,
+ .mask = 0xffff0000,
+ .name = "405GP",
+ .ci = {
+ .dcache_size = 8192,
+ .dcache_line_size = 32,
+ .icache_size = 8192,
+ .icache_line_size = 32,
+ }
+ }, {
+ .version = PVR_405GPR,
+ .mask = 0xffff0000,
+ .name = "405GPr",
+ .ci = {
+ .dcache_size = 16384,
+ .dcache_line_size = 32,
+ .icache_size = 16384,
+ .icache_line_size = 32,
+ }
+ }, {
+ .version = PVR_405D5X1,
+ .mask = 0xfffff000,
+ .name = "Xilinx Virtex II Pro",
+ .ci = {
+ .dcache_size = 16384,
+ .dcache_line_size = 32,
+ .icache_size = 16384,
+ .icache_line_size = 32,
+ }
+ }, {
+ .version = PVR_405D5X2,
+ .mask = 0xfffff000,
+ .name = "Xilinx Virtex 4 FX",
+ .ci = {
+ .dcache_size = 16384,
+ .dcache_line_size = 32,
+ .icache_size = 16384,
+ .icache_line_size = 32,
+ }
+ }, {
+ .version = PVR_405EX,
+ .mask = 0xffff0000,
+ .name = "405EX",
+ .ci = {
+ .dcache_size = 16384,
+ .dcache_line_size = 32,
+ .icache_size = 16384,
+ .icache_line_size = 32,
+ }
+ }, {
+ .version = 0,
+ .mask = 0,
+ .name = NULL,
+ .ci = {
+ /*
+ * Unknown CPU type. For safety we'll specify a
+ * cache with a 4-byte line size. That way cache
+ * flush routines won't miss any lines.
+ */
+ .dcache_line_size = 4,
+ .icache_line_size = 4,
+ },
+ },
};
static int cpumatch(device_t, cfdata_t, void *);
static void cpuattach(device_t, device_t, void *);
-CFATTACH_DECL_NEW(cpu, 0,
- cpumatch, cpuattach, NULL, NULL);
+CFATTACH_DECL_NEW(cpu, 0, cpumatch, cpuattach, NULL, NULL);
int ncpus;
@@ -88,19 +219,13 @@
NULL, "cpu0", "clock"),
.ci_ev_statclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,
NULL, "cpu0", "stat clock"),
- .ci_ev_softclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,
- NULL, "cpu0", "soft clock"),
- .ci_ev_softnet = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,
- NULL, "cpu0", "soft net"),
- .ci_ev_softserial = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,
- NULL, "cpu0", "soft serial"),
.ci_curlwp = &lwp0,
}
};
char cpu_model[80];
-int cpufound = 0;
+bool cpufound;
static int
cpumatch(device_t parent, cfdata_t cf, void *aux)
@@ -117,8 +242,8 @@
static void
cpuattach(device_t parent, device_t self, void *aux)
{
- const struct cputab *cp = models;
- u_int pvr;
+ struct cpu_info * const ci = curcpu();
+ const struct cputab *cp;
u_int processor_freq;
prop_number_t freq;
@@ -126,36 +251,35 @@
KASSERT(freq != NULL);
processor_freq = (unsigned int) prop_number_integer_value(freq);
- cpufound++;
+ cpufound = true;
ncpus++;
- pvr = mfpvr();
- while (cp->name) {
- if ((pvr & cp->mask) == cp->version)
+ const u_int pvr = mfpvr();
+ for (cp = models; cp->name != NULL; cp++) {
+ if ((pvr & cp->mask) == cp->version) {
+ strcpy(cpu_model, cp->name);
break;
- cp++;
+ }
}
- if (cp->name)
- strcpy(cpu_model, cp->name);
- else
+ if (__predict_false(cp->name == NULL))
sprintf(cpu_model, "Version 0x%x", pvr);
- printf(": %dMHz %s (PVR 0x%x)\n", processor_freq / 1000 / 1000,
- cp->name ? cp->name : "unknown model", pvr);
+ aprint_normal(": %uMHz %s (PVR 0x%x)\n",
+ (processor_freq + 500000) / 1000000,
+ (cp->name != NULL ? cpu_model : "unknown model"),
+ pvr);
cpu_probe_cache();
/* We would crash later on anyway so just make the reason obvious */
- if (curcpu()->ci_ci.icache_size == 0 &&
- curcpu()->ci_ci.dcache_size == 0)
- panic("%s could not detect cache size", device_xname(self));
-
- printf("%s: Instruction cache size %d line size %d\n",
- device_xname(self),
- curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size);
- printf("%s: Data cache size %d line size %d\n",
- device_xname(self),
- curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size);
+ if (ci->ci_ci.icache_size == 0 && ci->ci_ci.dcache_size == 0)
+ panic("%s: %s: could not detect cache size",
+ __func__, device_xname(self));
+
+ aprint_normal_dev(self, "%uKB/%uB L1 instruction cache\n",
+ ci->ci_ci.icache_size / 1024, ci->ci_ci.icache_line_size);
+ aprint_normal_dev(self, "%uKB/%uB L1 data cache\n",
+ ci->ci_ci.dcache_size / 1024, ci->ci_ci.dcache_line_size);
}
/*
@@ -166,95 +290,19 @@
void
cpu_probe_cache(void)
{
+ struct cpu_info * const ci = curcpu();
const struct cputab *cp = models;
- u_int pvr;
- pvr = mfpvr();
- while (cp->name) {
+ const u_int pvr = mfpvr();
+ for (cp = models; cp->name != NULL; cp++) {
if ((pvr & cp->mask) == cp->version)
break;
- cp++;
}
/*
- * First we need to identify the CPU and determine the
- * cache line size, or things like memset/memcpy may lose
- * badly.
+ * Copy the cache from the cputab into cpu_info.
*/
- switch (cp->version) {
- case PVR_401A1:
- curcpu()->ci_ci.dcache_size = 1024;
- curcpu()->ci_ci.dcache_line_size = 16;
- curcpu()->ci_ci.icache_size = 2848;
- curcpu()->ci_ci.icache_line_size = 16;
- break;
- case PVR_401B2:
- curcpu()->ci_ci.dcache_size = 8192;
- curcpu()->ci_ci.dcache_line_size = 16;
- curcpu()->ci_ci.icache_size = 16384;
- curcpu()->ci_ci.icache_line_size = 16;
- break;
- case PVR_401C2:
- curcpu()->ci_ci.dcache_size = 8192;
- curcpu()->ci_ci.dcache_line_size = 16;
- curcpu()->ci_ci.icache_size = 0;
- curcpu()->ci_ci.icache_line_size = 16;
- break;
- case PVR_401D2:
- curcpu()->ci_ci.dcache_size = 2848;
- curcpu()->ci_ci.dcache_line_size = 16;
- curcpu()->ci_ci.icache_size = 4096;
- curcpu()->ci_ci.icache_line_size = 16;
- break;
- case PVR_401E2:
- curcpu()->ci_ci.dcache_size = 0;
- curcpu()->ci_ci.dcache_line_size = 16;
- curcpu()->ci_ci.icache_size = 0;
- curcpu()->ci_ci.icache_line_size = 16;
- break;
- case PVR_401F2:
- curcpu()->ci_ci.dcache_size = 2048;
- curcpu()->ci_ci.dcache_line_size = 16;
- curcpu()->ci_ci.icache_size = 2848;
- curcpu()->ci_ci.icache_line_size = 16;
- break;
- case PVR_401G2:
- curcpu()->ci_ci.dcache_size = 2848;
- curcpu()->ci_ci.dcache_line_size = 16;
- curcpu()->ci_ci.icache_size = 8192;
- curcpu()->ci_ci.icache_line_size = 16;
- break;
- case PVR_403:
- curcpu()->ci_ci.dcache_size = 8192;
- curcpu()->ci_ci.dcache_line_size = 16;
- curcpu()->ci_ci.icache_size = 16384;
- curcpu()->ci_ci.icache_line_size = 16;
- break;
- case PVR_405GP:
- curcpu()->ci_ci.dcache_size = 8192;
- curcpu()->ci_ci.dcache_line_size = 32;
- curcpu()->ci_ci.icache_size = 8192;
- curcpu()->ci_ci.icache_line_size = 32;
- break;
- case PVR_405GPR:
- case PVR_405D5X1:
- case PVR_405D5X2:
- case PVR_405EX:
- curcpu()->ci_ci.dcache_size = 16384;
- curcpu()->ci_ci.dcache_line_size = 32;
- curcpu()->ci_ci.icache_size = 16384;
- curcpu()->ci_ci.icache_line_size = 32;
- break;
- default:
- /*
- * Unknown CPU type. For safety we'll specify a
- * cache with a 4-byte line size. That way cache
- * flush routines won't miss any lines.
- */
- curcpu()->ci_ci.dcache_line_size = 4;
- curcpu()->ci_ci.icache_line_size = 4;
- break;
- }
+ ci->ci_ci = cp->ci;
}
/*
@@ -263,57 +311,14 @@
*/
void
-dcache_flush_page(vaddr_t va)
-{
- int i;
-
- if (curcpu()->ci_ci.dcache_line_size)
- for (i = 0; i < PAGE_SIZE;
- i += curcpu()->ci_ci.dcache_line_size)
- __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i));
- __asm volatile("sync;isync" : : );
-}
-
-void
-icache_flush_page(vaddr_t va)
+dcache_wbinv_page(vaddr_t va)
{
- int i;
-
- if (curcpu()->ci_ci.icache_line_size)
- for (i = 0; i < PAGE_SIZE;
- i += curcpu()->ci_ci.icache_line_size)
- __asm volatile("icbi %0,%1" : : "r" (va), "r" (i));
- __asm volatile("sync;isync" : : );
-}
+ const size_t dcache_line_size = curcpu()->ci_ci.dcache_line_size;
-void
-dcache_flush(vaddr_t va, vsize_t len)
-{
- int i;
-
- if (len == 0)
- return;
-
- /* Make sure we flush all cache lines */
- len += va & (curcpu()->ci_ci.dcache_line_size-1);
- if (curcpu()->ci_ci.dcache_line_size)
- for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size)
- __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i));
- __asm volatile("sync;isync" : : );
-}
-
-void
-icache_flush(vaddr_t va, vsize_t len)
-{
- int i;
-
- if (len == 0)
- return;
-
- /* Make sure we flush all cache lines */
- len += va & (curcpu()->ci_ci.icache_line_size-1);
- if (curcpu()->ci_ci.icache_line_size)
- for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size)
- __asm volatile("icbi %0,%1" : : "r" (va), "r" (i));
- __asm volatile("sync;isync" : : );
+ if (dcache_line_size) {
+ for (size_t i = 0; i < PAGE_SIZE; i += dcache_line_size) {
+ __asm volatile("dcbf %0,%1" : : "b" (va), "r" (i));
+ }
+ __asm volatile("sync;isync" : : );
+ }
}
Index: src/sys/arch/powerpc/include/cpu.h
diff -u src/sys/arch/powerpc/include/cpu.h:1.84 src/sys/arch/powerpc/include/cpu.h:1.85
--- src/sys/arch/powerpc/include/cpu.h:1.84 Mon Jun 20 17:15:38 2011
+++ src/sys/arch/powerpc/include/cpu.h Tue Jun 21 04:21:17 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.84 2011/06/20 17:15:38 matt Exp $ */
+/* $NetBSD: cpu.h,v 1.85 2011/06/21 04:21:17 matt Exp $ */
/*
* Copyright (C) 1999 Wolfgang Solfrank.
@@ -124,9 +124,6 @@
uint32_t ci_khz;
struct evcnt ci_ev_clock; /* clock intrs */
struct evcnt ci_ev_statclock; /* stat clock */
- struct evcnt ci_ev_softclock; /* softclock intrs */
- struct evcnt ci_ev_softnet; /* softnet intrs */
- struct evcnt ci_ev_softserial; /* softserial intrs */
struct evcnt ci_ev_traps; /* calls to trap() */
struct evcnt ci_ev_kdsi; /* kernel DSI traps */
struct evcnt ci_ev_udsi; /* user DSI traps */
@@ -326,15 +323,8 @@
cpu_attach_common(device_t, int);
void cpu_setup(device_t, struct cpu_info *);
void cpu_identify(char *, size_t);
-int cpu_get_dfs(void);
-void cpu_set_dfs(int);
void cpu_probe_cache(void);
-#ifndef PPC_BOOKE
-void dcache_flush_page(vaddr_t);
-void icache_flush_page(vaddr_t);
-void dcache_flush(vaddr_t, vsize_t);
-void icache_flush(vaddr_t, vsize_t);
-#else
+
void dcache_wb_page(vaddr_t);
void dcache_wbinv_page(vaddr_t);
void dcache_inv_page(vaddr_t);
@@ -344,7 +334,7 @@
void dcache_wbinv(vaddr_t, vsize_t);
void dcache_inv(vaddr_t, vsize_t);
void icache_inv(vaddr_t, vsize_t);
-#endif
+
void * mapiodev(paddr_t, psize_t);
void unmapiodev(vaddr_t, vsize_t);
@@ -390,6 +380,9 @@
void cpu_fixup_stubs(void);
#if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE)
+int cpu_get_dfs(void);
+void cpu_set_dfs(int);
+
void oea_init(void (*)(void));
void oea_startup(const char *);
void oea_dumpsys(void);
Index: src/sys/arch/powerpc/oea/cpu_subr.c
diff -u src/sys/arch/powerpc/oea/cpu_subr.c:1.68 src/sys/arch/powerpc/oea/cpu_subr.c:1.69
--- src/sys/arch/powerpc/oea/cpu_subr.c:1.68 Mon Jun 20 16:31:28 2011
+++ src/sys/arch/powerpc/oea/cpu_subr.c Tue Jun 21 04:21:17 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_subr.c,v 1.68 2011/06/20 16:31:28 pgoyette Exp $ */
+/* $NetBSD: cpu_subr.c,v 1.69 2011/06/21 04:21:17 matt Exp $ */
/*-
* Copyright (c) 2001 Matt Thomas.
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.68 2011/06/20 16:31:28 pgoyette Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.69 2011/06/21 04:21:17 matt Exp $");
#include "opt_ppcparam.h"
#include "opt_multiprocessor.h"
@@ -658,12 +658,6 @@
evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR,
NULL, xname, "clock");
- evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR,
- NULL, xname, "soft clock");
- evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR,
- NULL, xname, "soft net");
- evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR,
- NULL, xname, "soft serial");
evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP,
NULL, xname, "traps");
evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP,
