Module Name: src
Committed By: jakllsch
Date: Thu Aug 4 14:43:55 UTC 2011
Modified Files:
src/sys/dev/pci: files.pci
Added Files:
src/sys/dev/pci: coram.c coramvar.h cx23885reg.h
Log Message:
Add coram(4).
A driver for CX23885-based TV cards, such as the
Hauppauge WinTV HVR-1250 "Coram" board.
Currently only supports ATSC 8VSB reception.
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/dev/pci/coram.c src/sys/dev/pci/coramvar.h \
src/sys/dev/pci/cx23885reg.h
cvs rdiff -u -r1.342 -r1.343 src/sys/dev/pci/files.pci
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/files.pci
diff -u src/sys/dev/pci/files.pci:1.342 src/sys/dev/pci/files.pci:1.343
--- src/sys/dev/pci/files.pci:1.342 Thu Jul 14 23:47:45 2011
+++ src/sys/dev/pci/files.pci Thu Aug 4 14:43:55 2011
@@ -1,4 +1,4 @@
-# $NetBSD: files.pci,v 1.342 2011/07/14 23:47:45 jmcneill Exp $
+# $NetBSD: files.pci,v 1.343 2011/08/04 14:43:55 jakllsch Exp $
#
# Config file and device description for machine-independent PCI code.
# Included by ports that need it. Requires that the SCSI files be
@@ -1053,3 +1053,8 @@
attach cxdtv at pci
file dev/pci/cxdtv.c cxdtv
file dev/pci/cxdtv_boards.c cxdtv
+
+# Conexant CX23885-series DTV interface
+device coram: dtvbus, i2cbus, i2cexec, mt2131, cx24227
+attach coram at pci
+file dev/pci/coram.c coram
Added files:
Index: src/sys/dev/pci/coram.c
diff -u /dev/null src/sys/dev/pci/coram.c:1.1
--- /dev/null Thu Aug 4 14:43:55 2011
+++ src/sys/dev/pci/coram.c Thu Aug 4 14:43:55 2011
@@ -0,0 +1,962 @@
+/* $NetBSD: coram.c,v 1.1 2011/08/04 14:43:55 jakllsch Exp $ */
+
+/*
+ * Copyright (c) 2008, 2011 Jonathan A. Kollasch
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: coram.c,v 1.1 2011/08/04 14:43:55 jakllsch Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kmem.h>
+#include <sys/mutex.h>
+
+#include <sys/bus.h>
+
+#include <dev/dtv/dtvif.h>
+
+#include <dev/pci/cx23885reg.h>
+#include <dev/pci/coramvar.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcidevs.h>
+#include <dev/i2c/i2cvar.h>
+#include <dev/i2c/at24cxxvar.h>
+
+#include <dev/i2c/cx24227var.h>
+#include <dev/i2c/mt2131var.h>
+
+static int coram_match(device_t, cfdata_t, void *);
+static void coram_attach(device_t, device_t, void *);
+static bool coram_resume(device_t, const pmf_qual_t *);
+static int coram_intr(void *);
+
+static int coram_iic_exec(void *, i2c_op_t, i2c_addr_t,
+ const void *, size_t, void *, size_t, int);
+static int coram_iic_acquire_bus(void *, int);
+static void coram_iic_release_bus(void *, int);
+static int coram_iic_read(struct coram_iic_softc *, i2c_op_t, i2c_addr_t,
+ const void *, size_t, void *, size_t, int);
+static int coram_iic_write(struct coram_iic_softc *, i2c_op_t, i2c_addr_t,
+ const void *, size_t, void *, size_t, int);
+
+static void coram_dtv_get_devinfo(void *, struct dvb_frontend_info *);
+static int coram_dtv_open(void *, int);
+static void coram_dtv_close(void *);
+static int coram_dtv_set_tuner(void *, const struct dvb_frontend_parameters *);
+static fe_status_t coram_dtv_get_status(void *);
+static uint16_t coram_dtv_get_signal_strength(void *);
+static uint16_t coram_dtv_get_snr(void *);
+static int coram_dtv_start_transfer(void *);
+static int coram_dtv_stop_transfer(void *);
+
+static int coram_mpeg_attach(struct coram_softc *);
+static int coram_mpeg_reset(struct coram_softc *);
+static void * coram_mpeg_malloc(struct coram_softc *, size_t);
+static int coram_allocmem(struct coram_softc *, size_t, size_t, struct coram_dma *);
+static void coram_mpeg_free(struct coram_softc *, void *);
+static int coram_mpeg_halt(struct coram_softc *);
+static int coram_freemem(struct coram_softc *, struct coram_dma *);
+static int coram_mpeg_trigger(struct coram_softc *, void *);
+static int coram_risc_buffer(struct coram_softc *, uint32_t, uint32_t);
+static int coram_risc_field(struct coram_softc *, uint32_t *, uint32_t);
+static int coram_sram_ch_setup(struct coram_softc *, struct coram_sram_ch *, uint32_t);
+static int coram_mpeg_intr(struct coram_softc *);
+
+CFATTACH_DECL_NEW(coram, sizeof(struct coram_softc),
+ coram_match, coram_attach, NULL, NULL);
+
+#define CORAM_SRAM_CH6 0
+
+#define CORAM_TS_PKTSIZE (188 * 8)
+
+static struct coram_sram_ch coram_sram_chs[] = {
+ [CORAM_SRAM_CH6] = {
+ .csc_cmds= 0x10140,
+ .csc_iq = 0x10500,
+ .csc_iqsz = 0x40,
+ .csc_cdt = 0x10600,
+ .csc_cdtsz = 0x10,
+ .csc_fifo = 0x6000,
+ .csc_fifosz = 0x1000,
+ .csc_risc = 0x10800,
+ .csc_riscsz = 0x800,
+ .csc_ptr1 = DMA5_PTR1,
+ .csc_ptr2 = DMA5_PTR2,
+ .csc_cnt1 = DMA5_CNT1,
+ .csc_cnt2 = DMA5_CNT2,
+ },
+};
+
+//#define PCI_PRODUCT_CONEXANT_CX23885 0x8852
+
+static const struct dtv_hw_if coram_dtv_if = {
+ .get_devinfo = coram_dtv_get_devinfo,
+ .open = coram_dtv_open,
+ .close = coram_dtv_close,
+ .set_tuner = coram_dtv_set_tuner,
+ .get_status = coram_dtv_get_status,
+ .get_signal_strength = coram_dtv_get_signal_strength,
+ .get_snr = coram_dtv_get_snr,
+ .start_transfer = coram_dtv_start_transfer,
+ .stop_transfer = coram_dtv_stop_transfer,
+};
+
+static int
+coram_match(device_t parent, cfdata_t match, void *v)
+{
+ const struct pci_attach_args *pa = v;
+
+ if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT)
+ return 0;
+
+ switch (PCI_PRODUCT(pa->pa_id)) {
+ case PCI_PRODUCT_CONEXANT_CX23885:
+ return 1;
+ }
+
+ /* XXX only match supported boards */
+
+ return 0;
+}
+
+static void
+coram_attach(device_t parent, device_t self, void *v)
+{
+ struct coram_softc *sc;
+ const struct pci_attach_args *pa = v;
+ pci_intr_handle_t ih;
+ pcireg_t reg;
+ const char *intrstr;
+ char devinfo[76];
+ struct coram_iic_softc *cic;
+ struct i2cbus_attach_args iba;
+ uint32_t value;
+
+ sc = device_private(self);
+
+ sc->sc_dev = self;
+
+ aprint_naive("\n");
+
+ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
+
+ sc->sc_vendor = PCI_VENDOR(reg);
+ sc->sc_product = PCI_PRODUCT(reg);
+
+ pci_devinfo(reg, pa->pa_class, 0, devinfo, sizeof(devinfo));
+ aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class));
+
+ if (pci_mapreg_map(pa, CX23885_MMBASE, PCI_MAPREG_TYPE_MEM, 0,
+ &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) {
+ aprint_error_dev(self, "couldn't map memory space\n");
+ return;
+ }
+
+ sc->sc_dmat = pa->pa_dmat;
+
+ if (pci_intr_map(pa, &ih)) {
+ aprint_error_dev(self, "couldn't map interrupt\n");
+ return;
+ }
+ intrstr = pci_intr_string(pa->pa_pc, ih);
+ sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_VM,
+ coram_intr, (void *)self);
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "couldn't establish interrupt");
+ if (intrstr != NULL)
+ aprint_error(" at %s", intrstr);
+ aprint_error("\n");
+ return;
+ }
+ aprint_normal_dev(self, "interrupting at %s\n", intrstr);
+
+ /* set master */
+ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
+ reg |= PCI_COMMAND_MASTER_ENABLE;
+ pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);
+
+ int i;
+
+ /* I2C */
+ for(i = 0; i < I2C_NUM; i++) {
+ cic = &sc->sc_iic[i];
+
+ cic->cic_sc = sc;
+ if(bus_space_subregion(sc->sc_memt, sc->sc_memh, I2C_BASE + (I2C_SIZE * i), I2C_SIZE, &cic->cic_regh))
+ panic("failed to subregion i2c");
+
+ mutex_init(&cic->cic_busmutex, MUTEX_DRIVER, IPL_NONE);
+ cic->cic_i2c.ic_cookie = cic;
+ cic->cic_i2c.ic_acquire_bus = coram_iic_acquire_bus;
+ cic->cic_i2c.ic_release_bus = coram_iic_release_bus;
+ cic->cic_i2c.ic_exec = coram_iic_exec;
+
+#if 1
+ /* attach iic(4) */
+ memset(&iba, 0, sizeof(iba));
+ iba.iba_tag = &cic->cic_i2c;
+ iba.iba_type = I2C_TYPE_SMBUS;
+ config_found_ia(self, "i2cbus", &iba, iicbus_print);
+#endif
+ }
+
+ /* HVR1250 GPIO */
+ value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x110010);
+#if 1
+ value &= ~0x00010001;
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value);
+ delay(5000);
+#endif
+ value |= 0x00010001;
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value);
+
+#if 0
+ int i;
+ uint8_t foo[256];
+ uint8_t bar;
+ bar = 0;
+// seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0, 256, foo, 256);
+
+ iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL);
+ iic_exec(&sc->sc_i2c, I2C_OP_READ_WITH_STOP, 0x50, &bar, 1, foo, 256, I2C_F_POLL);
+ iic_release_bus(&sc->sc_i2c, I2C_F_POLL);
+
+ printf("\n");
+ for ( i = 0; i < 256; i++) {
+ if ( (i % 8) == 0 )
+ printf("%02x: ", i);
+
+ printf("%02x", foo[i]);
+
+ if ( (i % 8) == 7 )
+ printf("\n");
+ else
+ printf(" ");
+ }
+ printf("\n");
+#endif
+
+ sc->sc_demod = cx24227_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x19);
+ if ( sc->sc_demod == NULL )
+ panic("no demod");
+
+ sc->sc_tuner = mt2131_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x61);
+ if ( sc->sc_tuner == NULL )
+ panic("no tuner");
+
+ coram_mpeg_attach(sc);
+
+ if (!pmf_device_register(self, NULL, coram_resume))
+ aprint_error_dev(self, "couldn't establish power handler\n");
+
+ return;
+}
+
+static int
+coram_intr(void *v)
+{
+ device_t self = v;
+ struct coram_softc *sc;
+ uint32_t val;
+
+ sc = device_private(self);
+
+ val = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSTAT );
+ if (val == 0)
+ return 0; /* not ours */
+
+ /* vid c */
+ if (val & __BIT(2))
+ coram_mpeg_intr(sc);
+
+ if (val & ~__BIT(2))
+ printf("%s %08x\n", __func__, val);
+
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, val);
+
+ return 1;
+}
+
+#define CXDTV_TS_RISCI2 (1 << 4)
+#define CXDTV_TS_RISCI1 (1 << 0)
+
+#define CXDTV_TS_RISCI (CXDTV_TS_RISCI1|CXDTV_TS_RISCI2)
+
+static int
+coram_mpeg_intr(struct coram_softc *sc)
+{
+ struct dtv_payload payload;
+ uint32_t s, m, v;
+ int i;
+
+ s = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT);
+ m = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK);
+
+ if ((s & m) == 0)
+ return 0;
+
+ if ( (s & ~CXDTV_TS_RISCI) != 0 ) {
+ printf("%s: unexpected TS IS %08x\n",
+ device_xname(sc->sc_dev), s);
+
+ printf("cmds:\n");
+ for(i = 0; i < 20; i++)
+ {
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x10140 +(i*4));
+ printf("%06x %08x\n", 0x10140+(i*4), v);
+ }
+ }
+
+ if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) {
+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map,
+ 0, CORAM_TS_PKTSIZE,
+ BUS_DMASYNC_POSTREAD);
+ payload.data = KERNADDR(sc->sc_dma);
+ payload.size = CORAM_TS_PKTSIZE;
+ dtv_submit_payload(sc->sc_dtvdev, &payload);
+ }
+
+ if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) {
+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map,
+ CORAM_TS_PKTSIZE, CORAM_TS_PKTSIZE,
+ BUS_DMASYNC_POSTREAD);
+ payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CORAM_TS_PKTSIZE;
+ payload.size = CORAM_TS_PKTSIZE;
+ dtv_submit_payload(sc->sc_dtvdev, &payload);
+ }
+
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, s);
+
+ return 1;
+}
+
+static bool
+coram_resume(device_t dv, const pmf_qual_t *qual)
+{
+ struct coram_softc *sc;
+ sc = device_private(dv);
+
+ device_printf(sc->sc_dev, "%s\n", __func__);
+
+ return true;
+}
+
+static int
+coram_iic_acquire_bus(void *cookie, int flags)
+{
+ struct coram_iic_softc *cic;
+
+ cic = cookie;
+
+ if (flags & I2C_F_POLL) {
+ while (mutex_tryenter(&cic->cic_busmutex) == 0)
+ delay(50);
+ return 0;
+ }
+
+ mutex_enter(&cic->cic_busmutex);
+
+ return 0;
+}
+
+static void
+coram_iic_release_bus(void *cookie, int flags)
+{
+ struct coram_iic_softc *cic;
+
+ cic = cookie;
+
+ mutex_exit(&cic->cic_busmutex);
+
+ return;
+}
+
+/* I2C Bus */
+
+#define I2C_ADDR 0x0000
+#define I2C_WDATA 0x0004
+#define I2C_CTRL 0x0008
+#define I2C_RDATA 0x000c
+#define I2C_STAT 0x0010
+
+#define I2C_EXTEND (1 << 3)
+#define I2C_NOSTOP (1 << 4)
+
+static int
+coram_iic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr,
+ const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
+{
+ struct coram_iic_softc *cic;
+ int ret;
+
+ cic = cookie;
+
+ if(cmdlen) {
+ ret = coram_iic_write(cic, op, addr, cmdbuf, cmdlen, buf, len, flags);
+ if(ret)
+ return ret;
+ }
+
+ if(len) {
+ ret = coram_iic_read(cic, op, addr, cmdbuf, cmdlen, buf, len, flags);
+ if(ret)
+ return ret;
+ }
+
+
+ return 0;
+
+}
+
+static int
+coram_iic_read(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr,
+ const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
+{
+ uint8_t *rb;
+ uint32_t ctrl;
+ int bn;
+
+ rb = buf;
+
+ for ( bn = 0; bn < len; bn++) {
+ ctrl = (0x9d << 24) | (1 << 12) | (1 << 2) | 1;
+ if ( bn < len - 1 )
+ ctrl |= I2C_NOSTOP | I2C_EXTEND;
+
+ bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addr<<25);
+ bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl);
+
+ while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh,
+ I2C_STAT) & 0x02)) {
+ delay(25);
+ }
+ if((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh,
+ I2C_STAT) & 0x01) == 0x00) {
+// printf("%s %d no ack\n", __func__, bn);
+ return EIO;
+ }
+
+ rb[bn] = bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_RDATA);
+
+ }
+
+ return 0;
+}
+
+static int
+coram_iic_write(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr,
+ const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
+{
+ const uint8_t *wb;
+ uint32_t wdata, addrreg, ctrl;
+ int bn;
+
+ wb = cmdbuf;
+
+ addrreg = (addr << 25) | wb[0];
+ wdata = wb[0];
+ ctrl = (0x9d << 24) | (1 << 12) | (1 << 2);
+
+ if ( cmdlen > 1 )
+ ctrl |= I2C_NOSTOP | I2C_EXTEND;
+ else if (len)
+ ctrl |= I2C_NOSTOP;
+
+ bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg);
+ bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata);
+ bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl);
+
+ while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) {
+ delay(25); }
+
+ for ( bn = 1; bn < cmdlen; bn++) {
+ ctrl = (0x9d << 24) | (1 << 12) | (1 << 2);
+ wdata = wb[bn];
+
+ if ( bn < cmdlen - 1 )
+ ctrl |= I2C_NOSTOP | I2C_EXTEND;
+ else if (len)
+ ctrl |= I2C_NOSTOP;
+
+ bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg);
+ bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata);
+ bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl);
+
+ while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) {
+ delay(25); }
+ }
+
+ return 0;
+}
+
+static int
+coram_mpeg_attach(struct coram_softc *sc)
+{
+ struct dtv_attach_args daa;
+ struct coram_sram_ch *ch;
+
+ ch = &coram_sram_chs[CORAM_SRAM_CH6];
+
+ sc->sc_riscbufsz = ch->csc_riscsz;
+ sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP);
+
+ if ( sc->sc_riscbuf == NULL )
+ panic("riscbuf null");
+
+ coram_mpeg_reset(sc);
+
+ daa.hw = &coram_dtv_if;
+ daa.priv = sc;
+
+ sc->sc_tsbuf = NULL;
+
+ sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", &daa, dtv_print);
+
+ return (sc->sc_dtvdev != NULL);
+}
+
+
+static void
+coram_dtv_get_devinfo(void *cookie, struct dvb_frontend_info *info)
+{
+ memset(info, 0, sizeof(*info));
+ strlcpy(info->name, "CX23885", sizeof(info->name));
+ info->type = FE_ATSC;
+ info->frequency_min = 54000000;
+ info->frequency_max = 858000000;
+ info->frequency_stepsize = 62500;
+ info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB;
+}
+
+static int
+coram_dtv_open(void *cookie, int flags)
+{
+ struct coram_softc *sc = cookie;
+
+ device_printf(sc->sc_dev, "%s\n", __func__);
+
+ //KASSERT(sc->sc_tsbuf == NULL);
+
+ coram_mpeg_reset(sc);
+
+ /* allocate two alternating DMA areas for MPEG TS packets */
+ sc->sc_tsbuf = coram_mpeg_malloc(sc, CORAM_TS_PKTSIZE * 2);
+
+ if (sc->sc_tsbuf == NULL)
+ return ENOMEM;
+
+ return 0;
+}
+
+static void
+coram_dtv_close(void *cookie)
+{
+ struct coram_softc *sc = cookie;
+
+ device_printf(sc->sc_dev, "%s\n", __func__);
+
+ coram_mpeg_halt(sc);
+
+ if (sc->sc_tsbuf != NULL) {
+ coram_mpeg_free(sc, sc->sc_tsbuf);
+ sc->sc_tsbuf = NULL;
+ }
+}
+
+static int
+coram_dtv_set_tuner(void *cookie, const struct dvb_frontend_parameters *params)
+{
+ struct coram_softc *sc = cookie;
+
+ KASSERT(sc->sc_tuner != NULL);
+ mt2131_tune_dtv(sc->sc_tuner, params);
+ KASSERT(sc->sc_demod != NULL);
+ cx24227_set_modulation(sc->sc_demod, params->u.vsb.modulation);
+
+ return 0; /* XXX */
+}
+
+static fe_status_t
+coram_dtv_get_status(void *cookie)
+{
+ return 0;
+}
+
+static uint16_t
+coram_dtv_get_signal_strength(void *cookie)
+{
+ return 0;
+}
+
+static uint16_t
+coram_dtv_get_snr(void *cookie)
+{
+ return 0;
+}
+
+static int
+coram_dtv_start_transfer(void *cookie)
+{
+ struct coram_softc *sc = cookie;
+
+ device_printf(sc->sc_dev, "%s\n", __func__);
+
+ coram_mpeg_trigger(sc, sc->sc_tsbuf);
+
+ return 0;
+}
+
+static int
+coram_dtv_stop_transfer(void *cookie)
+{
+ struct coram_softc *sc = cookie;
+
+ device_printf(sc->sc_dev, "%s\n", __func__);
+
+ coram_mpeg_halt(sc);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0);
+
+ return 0;
+}
+
+
+static int
+coram_mpeg_reset(struct coram_softc *sc)
+{
+ uint32_t v;
+
+ v = (uint32_t)-1;
+
+ /* hold RISC in reset */
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, 0);
+
+ /* disable fifo + risc */
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0);
+
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 0);
+
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, 0);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, 0);
+
+ memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz);
+
+ return 0;
+}
+
+static void *
+coram_mpeg_malloc(struct coram_softc *sc, size_t size)
+{
+ struct coram_dma *p;
+ int err;
+
+ p = kmem_alloc(sizeof(struct coram_dma), KM_SLEEP);
+ if ( p == NULL )
+ return NULL;
+ err = coram_allocmem(sc, size, 16, p);
+ if (err) {
+ kmem_free(p, sizeof(struct coram_dma));
+ return NULL;
+ }
+
+ p->next = sc->sc_dma;
+ sc->sc_dma = p;
+
+ return KERNADDR(p);
+}
+
+static int
+coram_allocmem(struct coram_softc *sc, size_t size, size_t align,
+ struct coram_dma *p)
+{
+ int err;
+
+ p->size = size;
+ err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0,
+ p->segs, sizeof(p->segs) / sizeof(p->segs[0]),
+ &p->nsegs, BUS_DMA_NOWAIT);
+ if (err)
+ return err;
+ err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size,
+ &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
+ if (err)
+ goto free;
+ err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0,
+ BUS_DMA_NOWAIT, &p->map);
+ if (err)
+ goto unmap;
+ err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL,
+ BUS_DMA_NOWAIT);
+ if (err)
+ goto destroy;
+
+ return 0;
+destroy:
+ bus_dmamap_destroy(sc->sc_dmat, p->map);
+unmap:
+ bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size);
+free:
+ bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs);
+
+ return err;
+}
+
+static int
+coram_mpeg_halt(struct coram_softc *sc)
+{
+ uint32_t v;
+
+ device_printf(sc->sc_dev, "%s\n", __func__);
+
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0);
+
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK,
+ v & __BIT(2));
+
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK,
+ v & 0);
+
+ return 0;
+}
+
+static void
+coram_mpeg_free(struct coram_softc *sc, void *addr)
+{
+ struct coram_dma *p;
+ struct coram_dma **pp;
+
+ for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next)
+ if (KERNADDR(p) == addr) {
+ coram_freemem(sc, p);
+ *pp = p->next;
+ kmem_free(p, sizeof(struct coram_dma));
+ return;
+ }
+
+ printf("%s: %p is already free\n", device_xname(sc->sc_dev), addr);
+ return;
+}
+
+static int
+coram_freemem(struct coram_softc *sc, struct coram_dma *p)
+{
+ bus_dmamap_unload(sc->sc_dmat, p->map);
+ bus_dmamap_destroy(sc->sc_dmat, p->map);
+ bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size);
+ bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs);
+
+ return 0;
+}
+
+static int
+coram_mpeg_trigger(struct coram_softc *sc, void *buf)
+{
+ struct coram_dma *p;
+ struct coram_sram_ch *ch;
+ uint32_t v;
+
+ ch = &coram_sram_chs[CORAM_SRAM_CH6];
+
+ for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next)
+ continue;
+ if (p == NULL) {
+ printf("%s: coram_mpeg_trigger: bad addr %p\n",
+ device_xname(sc->sc_dev), buf);
+ return ENOENT;
+ }
+
+ /* disable fifo + risc */
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0);
+
+ coram_risc_buffer(sc, CORAM_TS_PKTSIZE, 1);
+ coram_sram_ch_setup(sc, ch, CORAM_TS_PKTSIZE);
+
+ /* let me hope this bit is the same as on the 2388[0-3] */
+ /* software reset */
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 0x0040);
+ delay (100*1000);
+
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_LNGTH, CORAM_TS_PKTSIZE);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_HW_SOP_CTL, 0x47 << 16 | 188 << 4);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_TS_CLK_EN, 1);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_VLD_MISC, 0);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 12);
+ delay (100*1000);
+
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PAD_CTRL);
+ v &= ~0x4; /* Clear TS2_SOP_OE */
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, PAD_CTRL, v);
+
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK);
+ v |= 0x111111;
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, v);
+
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL);
+ v |= 0x11; /* Enable RISC controller and FIFO */
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, v);
+
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2);
+ v |= __BIT(5); /* Enable RISC controller */
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, v);
+
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK);
+ v |= 0x001f00;
+ v |= 0x04;
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, v);
+
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL);
+ printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v);
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS);
+ printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v);
+ delay(100*1000);
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL);
+ printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v);
+ v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS);
+ printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v);
+
+ return 0;
+}
+
+static int
+coram_risc_buffer(struct coram_softc *sc, uint32_t bpl, uint32_t lines)
+{
+ uint32_t *rm;
+ uint32_t size;
+
+ size = 1 + (bpl * lines) / PAGE_SIZE + lines;
+ size += 2;
+
+ if (sc->sc_riscbuf == NULL) {
+ return ENOMEM;
+ }
+
+ rm = (uint32_t *)sc->sc_riscbuf;
+ coram_risc_field(sc, rm, bpl);
+
+ return 0;
+}
+
+static int
+coram_risc_field(struct coram_softc *sc, uint32_t *rm, uint32_t bpl)
+{
+ struct coram_dma *p;
+
+ for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next)
+ continue;
+ if (p == NULL) {
+ printf("%s: coram_risc_field: bad addr %p\n",
+ device_xname(sc->sc_dev), sc->sc_tsbuf);
+ return ENOENT;
+ }
+
+ memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz);
+
+ rm = sc->sc_riscbuf;
+
+ /* htole32 will be done when program is copied to chip sram */
+
+ /* XXX */
+ *(rm++) = (CX_RISC_SYNC|0);
+
+ *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl);
+ *(rm++) = (DMAADDR(p) + 0 * bpl);
+ *(rm++) = 0; /* high dword */
+
+ *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl);
+ *(rm++) = (DMAADDR(p) + 1 * bpl);
+ *(rm++) = 0;
+
+ *(rm++) = (CX_RISC_JUMP|1);
+ *(rm++) = (coram_sram_chs[CORAM_SRAM_CH6].csc_risc + 4);
+ *(rm++) = 0;
+
+ return 0;
+}
+
+static int
+coram_sram_ch_setup(struct coram_softc *sc, struct coram_sram_ch *csc,
+ uint32_t bpl)
+{
+ unsigned int i, lines;
+ uint32_t cdt;
+
+ /* XXX why round? */
+ bpl = (bpl + 7) & ~7;
+ cdt = csc->csc_cdt;
+ lines = csc->csc_fifosz / bpl;
+ printf("%s %d lines\n", __func__, lines);
+
+ /* fill in CDT */
+ for (i = 0; i < lines; i++) {
+#if 1
+ printf("CDT ent %08x, %08x\n", cdt + (16 * i),
+ csc->csc_fifo + (bpl * i));
+#endif
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+ cdt + (16 * i), csc->csc_fifo + (bpl * i));
+ }
+
+ /* copy program */
+ /* converts program to little endian as it goes into sram */
+ bus_space_write_region_4(sc->sc_memt, sc->sc_memh,
+ csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2);
+
+ /* fill in CMDS */
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+ csc->csc_cmds + CMDS_O_IRPC, csc->csc_risc);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+ csc->csc_cmds + CMDS_O_IRPC + 4, 0);
+
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+ csc->csc_cmds + CMDS_O_CDTB, csc->csc_cdt);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+ csc->csc_cmds + CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */
+
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+ csc->csc_cmds + CMDS_O_IQB, csc->csc_iq);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+ csc->csc_cmds + CMDS_O_IQS,
+ CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) );
+
+ /* zero rest of CMDS */
+ bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x18, 0, 20);
+
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+ csc->csc_ptr1, csc->csc_fifo);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+ csc->csc_ptr2, cdt);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+ csc->csc_cnt2, (lines * 16) >> 3);
+ bus_space_write_4(sc->sc_memt, sc->sc_memh,
+ csc->csc_cnt1, (bpl >> 3) - 1);
+
+ return 0;
+}
Index: src/sys/dev/pci/coramvar.h
diff -u /dev/null src/sys/dev/pci/coramvar.h:1.1
--- /dev/null Thu Aug 4 14:43:55 2011
+++ src/sys/dev/pci/coramvar.h Thu Aug 4 14:43:55 2011
@@ -0,0 +1,99 @@
+/* $NetBSD: coramvar.h,v 1.1 2011/08/04 14:43:55 jakllsch Exp $ */
+
+/*
+ * Copyright (c) 2008, 2011 Jonathan A. Kollasch
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_PCI_CORAMVAR_H
+#define _DEV_PCI_CORAMVAR_H
+
+#include <sys/bus.h>
+#include <sys/mutex.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/i2c/i2cvar.h>
+
+#define KERNADDR(p) ((void *)((p)->addr))
+#define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr)
+
+struct coram_sram_ch {
+ uint32_t csc_cmds;
+ uint32_t csc_iq;
+ uint32_t csc_iqsz;
+ uint32_t csc_cdt;
+ uint32_t csc_cdtsz;
+ uint32_t csc_fifo;
+ uint32_t csc_fifosz;
+ uint32_t csc_risc;
+ uint32_t csc_riscsz;
+ uint32_t csc_ptr1;
+ uint32_t csc_ptr2;
+ uint32_t csc_cnt1;
+ uint32_t csc_cnt2;
+};
+
+struct coram_dma {
+ bus_dmamap_t map;
+ void * addr;
+ bus_dma_segment_t segs[1];
+ int nsegs;
+ size_t size;
+ struct coram_dma * next;
+};
+
+struct coram_softc {
+ device_t sc_dev;
+ device_t sc_dtvdev;
+
+ bus_space_tag_t sc_memt;
+ bus_space_handle_t sc_memh;
+ bus_size_t sc_mems;
+ bus_dma_tag_t sc_dmat;
+
+ void * sc_ih;
+
+ struct coram_iic_softc {
+ struct coram_softc * cic_sc;
+ bus_space_handle_t cic_regh;
+ struct i2c_controller cic_i2c;
+ kmutex_t cic_busmutex;
+ } sc_iic[3];
+
+ struct coram_sram_ch sc_vidc_sch;
+
+ struct coram_dma * sc_dma;
+ struct coram_dma * sc_tsbuf;
+
+ uint32_t * sc_riscbuf;
+ uint32_t sc_riscbufsz;
+
+ void *sc_tuner;
+ void *sc_demod;
+
+ pci_vendor_id_t sc_vendor;
+ pci_product_id_t sc_product;
+};
+
+#endif /* !_DEV_PCI_CORAMVAR_H */
Index: src/sys/dev/pci/cx23885reg.h
diff -u /dev/null src/sys/dev/pci/cx23885reg.h:1.1
--- /dev/null Thu Aug 4 14:43:55 2011
+++ src/sys/dev/pci/cx23885reg.h Thu Aug 4 14:43:55 2011
@@ -0,0 +1,117 @@
+/* $NetBSD: cx23885reg.h,v 1.1 2011/08/04 14:43:55 jakllsch Exp $ */
+
+/*
+ * Copyright (c) 2008, 2011 Jonathan A. Kollasch
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_PCI_CX23885REG_H
+#define _DEV_PCI_CX23885REG_H
+
+#include <dev/pci/pcireg.h>
+
+#define CX23885_MMBASE PCI_BAR(0)
+
+/* misc. registers */
+
+#define DEV_CNTRL2 0x040000
+#define PCI_INT_MSK 0x040010
+#define PCI_INT_STAT 0x040014
+#define PCI_INT_MSTAT 0x040018
+
+#define VID_C_INT_MSK 0x040040
+#define VID_C_INT_STAT 0x040044
+#define VID_C_INT_MSTAT 0x040048
+#define VID_C_INT_SSTAT 0x04004c
+
+#define DMA5_PTR1 0x100010
+#define DMA5_PTR2 0x100050
+#define DMA5_CNT1 0x100090
+#define DMA5_CNT2 0x1000d0
+
+/* GPIO */
+#define GP0_IO 0x110010
+#define GPIO_ISM 0x110014
+#define SOFT_RESET 0x11001c
+
+#define PAD_CTRL 0x11004c
+
+/* Video C Interface */
+#define VID_C_GPCNT 0x130220
+#define VID_C_GPCNT_CTL 0x130230
+#define VBI_C_GPCNT_CTL 0x130234
+#define VID_C_DMA_CTL 0x130240
+#define VID_C_LNGTH 0x130250
+#define VID_C_HW_SOP_CTL 0x130254
+#define VID_C_GEN_CTL 0x130258
+#define VID_C_BD_PKT_STATUS 0x13025c
+#define VID_C_SOP_STATUS 0x130260
+#define VID_C_FIFO_OVFL_STAT 0x130264
+#define VID_C_VLD_MISC 0x130268
+#define VID_C_TS_CLK_EN 0x13026c
+
+/* serial controllers */
+#define I2C_BASE 0x180000
+#define I2C_SIZE 0x010000
+#define I2C_NUM 3
+
+/* RISC instructions */
+
+#define CX_RISC_WRITECR 0xd0000000
+#define CX_RISC_WRITECM 0xc0000000
+#define CX_RISC_WRITERM 0xb0000000
+#define CX_RISC_READC 0xa0000000
+#define CX_RISC_READ 0x90000000
+#define CX_RISC_SYNC 0x80000000
+#define CX_RISC_JUMP 0x70000000
+#define CX_RISC_WRITEC 0x50000000
+#define CX_RISC_SKIP 0x20000000
+#define CX_RISC_WRITE 0x10000000
+#define CX_RISC_SOL 0x08000000
+#define CX_RISC_EOL 0x04000000
+#define CX_RISC_IRQ2 0x02000000
+#define CX_RISC_IRQ1 0x01000000
+#define CX_RISC_IMM 0x00000001
+#define CX_RISC_SRP 0x00000001
+
+#define CX_CNT_CTL_NOOP 0x0
+#define CX_CNT_CTL_INCR 0x1
+#define CX_CNT_CTL_ZERO 0x3
+#define CX_RISC_CNT_CTL __BITS(17,16)
+#define CX_RISC_CNT_CTL_NOOP __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_NOOP)
+#define CX_RISC_CNT_CTL_INCR __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_INCR)
+#define CX_RISC_CNT_CTL_ZERO __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_ZERO)
+
+/* Channel Management Data Structure */
+/* offsets */
+#define CMDS_O_IRPC 0x00
+#define CMDS_O_CDTB 0x08
+#define CMDS_O_CDTS 0x0c
+#define CMDS_O_IQB 0x10
+#define CMDS_O_IQS 0x14
+
+/* bits */
+#define CMDS_IQS_ISRP __BIT(31)
+
+#endif /* !_DEV_PCI_CX23885REG_H */
