Module Name: src
Committed By: matt
Date: Tue Aug 16 06:55:12 UTC 2011
Modified Files:
src/sys/arch/mips/mips: bds_emul.S copy.S fp.S locore.S locore_mips3.S
mipsX_subr.S
Log Message:
Only jump through t9/ra (or k0) to help avoid hitting
the Loongson2 jump problem.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/mips/bds_emul.S
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/mips/mips/copy.S
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/mips/mips/fp.S
cvs rdiff -u -r1.187 -r1.188 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r1.101 -r1.102 src/sys/arch/mips/mips/locore_mips3.S
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/bds_emul.S
diff -u src/sys/arch/mips/mips/bds_emul.S:1.4 src/sys/arch/mips/mips/bds_emul.S:1.5
--- src/sys/arch/mips/mips/bds_emul.S:1.4 Sat Feb 26 11:27:59 2011
+++ src/sys/arch/mips/mips/bds_emul.S Tue Aug 16 06:55:11 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: bds_emul.S,v 1.4 2011/02/26 11:27:59 tsutsui Exp $ */
+/* $NetBSD: bds_emul.S,v 1.5 2011/08/16 06:55:11 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -66,8 +66,8 @@
srl t0, a0, 26-PTR_SCALESHIFT
andi t0, 0x3F << PTR_SCALESHIFT
- PTR_L t0, bcemul_optbl(t0)
- j t0
+ PTR_L t9, bcemul_optbl(t0)
+ jr t9
.rdata
bcemul_optbl:
@@ -173,7 +173,7 @@
REG_PROLOGUE
REG_L v0, TF_REG_ZERO(t1) # load source
REG_EPILOGUE
- j ra # execute the instruction
+ jr ra # execute the instruction
bcemul_uimmed_prologue:
srl t1, a0, 21-REG_SCALESHIFT # rs (source)
@@ -186,7 +186,7 @@
REG_PROLOGUE
REG_L v0, TF_REG_ZERO(t1) # load source
REG_EPILOGUE
- j ra
+ jr ra
#ifndef __mips_o32
bcemul_daddi:
@@ -441,11 +441,12 @@
andi t0, a0, 0x3f # get special code
sll t1, t0, 3 # calculate index in specialop
sll t0, PTR_SCALESHIFT
- PTR_LA t9, bcemul_special_op(t1)
- PTR_L t0, bcemul_specialtbl(t0)
- j t0
+ PTR_LA t0, bcemul_special_op(t1)
+ PTR_L t9, bcemul_specialtbl(t0)
+ jr t9
bcemul_special_3op_prologue:
+ move t9, t0
srl t0, a0, 21-REG_SCALESHIFT # rs (source1)
srl t1, a0, 16-REG_SCALESHIFT # rt (source2)
srl t2, a0, 11-REG_SCALESHIFT # rd (dest)
@@ -459,9 +460,10 @@
REG_L v0, TF_REG_ZERO(t0) # load source1
REG_L v1, TF_REG_ZERO(t1) # load source2
REG_EPILOGUE
- j t9
+ jr t9
bcemul_special_2src_prologue:
+ move t9, t0
srl t0, a0, 21-REG_SCALESHIFT # rs (source1)
srl t1, a0, 16-REG_SCALESHIFT # rt (source2)
andi t0, REG_REGMASK
@@ -472,9 +474,10 @@
REG_L v0, TF_REG_ZERO(t0) # load source1
REG_L v1, TF_REG_ZERO(t1) # load source2
REG_EPILOGUE
- j t9
+ jr t9
bcemul_special_genshift:
+ move t9, t0
srl t1, a0, 16-REG_SCALESHIFT # rt (source)
srl t2, a0, 11-REG_SCALESHIFT # rd (dest)
srl v1, a0, 6 # sa
@@ -606,7 +609,7 @@
REG_L ra, CALLFRAME_RA(sp)
REG_L s0, CALLFRAME_S0(sp)
PTR_ADDU sp, CALLFRAME_SIZ
- j ra
+ jr ra
/*
* Send SIGILL, SIGFPE.
Index: src/sys/arch/mips/mips/copy.S
diff -u src/sys/arch/mips/mips/copy.S:1.14 src/sys/arch/mips/mips/copy.S:1.15
--- src/sys/arch/mips/mips/copy.S:1.14 Wed Jul 6 09:27:35 2011
+++ src/sys/arch/mips/mips/copy.S Tue Aug 16 06:55:11 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: copy.S,v 1.14 2011/07/06 09:27:35 matt Exp $ */
+/* $NetBSD: copy.S,v 1.15 2011/08/16 06:55:11 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -499,9 +499,9 @@
PTR_S v0, PCB_ONFAULT(v1)
INT_S a1, 0(a0) # store word
PTR_S zero, PCB_ONFAULT(v1)
- PTR_L v1, _C_LABEL(mips_cache_ops) + MIPSX_FLUSHICACHE
+ PTR_L t9, _C_LABEL(mips_cache_ops) + MIPSX_FLUSHICACHE
move v0, zero
- j v1 # NOTE: must not clobber v0!
+ j t9 # NOTE: must not clobber v0!
li a1, 4 # size of word
END(ustore_uint32_isync)
Index: src/sys/arch/mips/mips/fp.S
diff -u src/sys/arch/mips/mips/fp.S:1.43 src/sys/arch/mips/mips/fp.S:1.44
--- src/sys/arch/mips/mips/fp.S:1.43 Sat Feb 26 15:41:32 2011
+++ src/sys/arch/mips/mips/fp.S Tue Aug 16 06:55:11 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: fp.S,v 1.43 2011/02/26 15:41:32 tsutsui Exp $ */
+/* $NetBSD: fp.S,v 1.44 2011/08/16 06:55:11 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -151,29 +151,29 @@
single_op:
andi v0, a0, 0x3F # get FUNC field
sll v0, v0, PTR_SCALESHIFT
- PTR_L v0, func_single_tbl(v0)
- j v0
+ PTR_L t9, func_single_tbl(v0)
+ j t9
double_op:
andi v0, a0, 0x3F # get FUNC field
sll v0, v0, PTR_SCALESHIFT
- PTR_L v0, func_double_tbl(v0)
- j v0
+ PTR_L t9, func_double_tbl(v0)
+ j t9
single_fixed_op:
andi v0, a0, 0x3F # get FUNC field
sll v0, v0, PTR_SCALESHIFT
- PTR_L v0, func_single_fixed_tbl(v0)
- j v0
+ PTR_L t9, func_single_fixed_tbl(v0)
+ j t9
long_fixed_op:
andi v0, a0, 0x3F # get FUNC field
sll v0, v0, PTR_SCALESHIFT
- PTR_L v0, func_long_fixed_tbl(v0)
- j v0
+ PTR_L t9, func_long_fixed_tbl(v0)
+ j t9
#if (defined(__mips_n32) || defined(__mips_n64)) && 0
paired_single_op:
andi v0, a0, 0x3F # get FUNC field
sll v0, v0, PTR_SCALESHIFT
- PTR_L v0, func_paired_single_tbl(v0)
- j v0
+ PTR_L t9, func_paired_single_tbl(v0)
+ j t9
#else
#define paired_single_op ill
#endif
@@ -766,8 +766,8 @@
branchc1:
srl v0, a0, 16 - PTR_SCALESHIFT
andi v0, v0, 0x1f << PTR_SCALESHIFT
- PTR_L v0, branchc1_tbl(v0)
- j v0
+ PTR_L t9, branchc1_tbl(v0)
+ j t9
.rdata
branchc1_tbl:
Index: src/sys/arch/mips/mips/locore.S
diff -u src/sys/arch/mips/mips/locore.S:1.187 src/sys/arch/mips/mips/locore.S:1.188
--- src/sys/arch/mips/mips/locore.S:1.187 Wed Apr 6 13:30:33 2011
+++ src/sys/arch/mips/mips/locore.S Tue Aug 16 06:55:12 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.187 2011/04/06 13:30:33 tsutsui Exp $ */
+/* $NetBSD: locore.S,v 1.188 2011/08/16 06:55:12 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -332,7 +332,7 @@
#if IPL_SCHED != IPL_HIGH
j _C_LABEL(splhigh_noprof)
#else
- j ra
+ jr ra
#endif
PTR_ADDU sp, CALLFRAME_SIZ
@@ -412,7 +412,7 @@
/*
* Almost everything (all except sp) is restored so we can return.
*/
- j ra
+ jr ra
PTR_ADDU sp, CALLFRAME_SIZ
END(softint_fast_dispatch)
#endif /* __HAVE_FAST_SOFTINTS */
@@ -435,7 +435,7 @@
li v0, 0 # load success
1:
PTR_S zero, PCB_ONFAULT(t0) # reset fault handler
- j ra # and return.
+ jr ra # and return.
nop
END(lwp_oncpu)
@@ -468,7 +468,7 @@
REG_S ra, PCB_CONTEXT+SF_REG_RA(a0)
REG_S v0, PCB_CONTEXT+SF_REG_SR(a0)
REG_EPILOGUE
- j ra
+ jr ra
move v0, zero
END(savectx)
@@ -497,7 +497,7 @@
REG_S ra, SF_REG_RA(a0)
REG_S v0, SF_REG_SR(a0)
REG_EPILOGUE
- j ra
+ jr ra
move v0, zero
END(setjmp)
@@ -523,7 +523,7 @@
REG_EPILOGUE
mtc0 v0, MIPS_COP_0_STATUS
COP0_SYNC
- j ra
+ jr ra
li v0, 1
END(longjmp)
#endif
@@ -538,7 +538,7 @@
*/
LEAF_NOPROFILE(mips_cp0_cause_read)
mfc0 v0, MIPS_COP_0_CAUSE
- j ra
+ jr ra
nop
END(mips_cp0_cause_read)
@@ -560,7 +560,7 @@
*/
LEAF(mips_cp0_status_read)
mfc0 v0, MIPS_COP_0_STATUS
- j ra
+ jr ra
nop
END(mips_cp0_status_read)
@@ -731,7 +731,7 @@
bgtz a2, 1b
PTR_ADDU a0, 8*SZREG
.set pop
- j ra
+ jr ra
nop
END(mips_pagecopy)
@@ -755,7 +755,7 @@
bgtz a1,1b
PTR_ADDU a0, 8*SZREG
.set pop
- j ra
+ jr ra
nop
END(mips_pagezero)
@@ -813,7 +813,7 @@
REG_L ra, XCALLFRAME_RA(sp)
PTR_ADDU sp, XCALLFRAME_SIZ
- j ra
+ jr ra
nop
#undef XCALLFRAME_RA
#undef XCALLFRAME_SIZ
Index: src/sys/arch/mips/mips/locore_mips3.S
diff -u src/sys/arch/mips/mips/locore_mips3.S:1.101 src/sys/arch/mips/mips/locore_mips3.S:1.102
--- src/sys/arch/mips/mips/locore_mips3.S:1.101 Sun Jul 31 15:39:29 2011
+++ src/sys/arch/mips/mips/locore_mips3.S Tue Aug 16 06:55:11 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips3.S,v 1.101 2011/07/31 15:39:29 matt Exp $ */
+/* $NetBSD: locore_mips3.S,v 1.102 2011/08/16 06:55:11 matt Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -158,7 +158,7 @@
XLEAF(mips64r2_wbflush)
nop
sync
- j ra
+ jr ra
nop
END(mips3_wbflush)
@@ -185,7 +185,7 @@
nop
nop
nop
- j ra
+ jr ra
nop
END(mips_wait_idle)
@@ -196,7 +196,7 @@
*/
LEAF(mips3_cp0_compare_read)
mfc0 v0, MIPS_COP_0_COMPARE
- j ra
+ jr ra
nop
END(mips3_cp0_compare_read)
@@ -217,7 +217,7 @@
*/
LEAF(mips3_cp0_config_read)
mfc0 v0, MIPS_COP_0_CONFIG
- j ra
+ jr ra
nop
END(mips3_cp0_config_read)
@@ -245,7 +245,7 @@
*/
LEAF(mipsNN_cp0_config1_read)
mfc0 v0, MIPS_COP_0_CONFIG, 1
- j ra
+ jr ra
nop
END(mipsNN_cp0_config1_read)
@@ -266,7 +266,7 @@
*/
LEAF(mipsNN_cp0_config2_read)
mfc0 v0, MIPS_COP_0_CONFIG, 2
- j ra
+ jr ra
nop
END(mipsNN_cp0_config2_read)
@@ -277,7 +277,7 @@
*/
LEAF(mipsNN_cp0_config3_read)
mfc0 v0, MIPS_COP_0_CONFIG, 3
- j ra
+ jr ra
nop
END(mipsNN_cp0_config3_read)
@@ -407,7 +407,7 @@
* Set the value of the CP0 USERLOCAL (TLB_CONTEXT, select 2) register.
*/
LEAF(mipsNN_cp0_hwrena_write)
- j ra
+ jr ra
mtc0 a0, MIPS_COP_0_HWRENA
END(mipsNN_cp0_hwrena_write)
@@ -416,7 +416,7 @@
* Set the value of the CP0 USERLOCAL (TLB_CONTEXT, select 2) register.
*/
LEAF(mipsNN_cp0_userlocal_write)
- j ra
+ jr ra
_MTC0 a0, MIPS_COP_0_TLB_CONTEXT, 2
END(mipsNN_cp0_userlocal_write)
#endif /* (MIPS32R2 + MIPS64R2) > 0 */
@@ -430,7 +430,7 @@
*/
LEAF(mips3_cp0_count_read)
mfc0 v0, MIPS_COP_0_COUNT
- j ra
+ jr ra
nop
END(mips3_cp0_count_read)
WEAK_ALIAS(cpu_counter32, mips3_cp0_count_read)
@@ -452,7 +452,7 @@
*/
LEAF(mips3_cp0_wired_read)
mfc0 v0, MIPS_COP_0_TLB_WIRED
- j ra
+ jr ra
nop
END(mips3_cp0_wired_read)
@@ -598,7 +598,7 @@
mtc0 t0, MIPS_COP_0_STATUS # Restore KX
COP0_SYNC
PTR_S zero, PCB_ONFAULT(v1)
- j ra
+ jr ra
move v0, zero # made it w/o errors
END(badaddr64)
@@ -606,7 +606,7 @@
mtc0 t0, MIPS_COP_0_STATUS # Restore KX
COP0_SYNC
PTR_S zero, PCB_ONFAULT(v1)
- j ra
+ jr ra
li v0, -1
END(baderr64)
@@ -638,7 +638,7 @@
srl v0, v0, 0
#endif
#endif /* __mips_o32 */
- j ra
+ jr ra
nop
END(mips3_cp0_tlb_entry_hi_probe)
@@ -666,7 +666,7 @@
srl v0, v0, 0
#endif
#endif /* __mips_o32 */
- j ra
+ jr ra
nop
END(mips3_cp0_tlb_entry_lo_probe)
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.52 src/sys/arch/mips/mips/mipsX_subr.S:1.53
--- src/sys/arch/mips/mips/mipsX_subr.S:1.52 Tue Aug 2 05:13:21 2011
+++ src/sys/arch/mips/mips/mipsX_subr.S Tue Aug 16 06:55:12 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.52 2011/08/02 05:13:21 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.53 2011/08/16 06:55:12 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -334,6 +334,10 @@
*/
VECTOR(MIPSX(tlb_miss), unknown)
.set noat
+#ifdef MIPS3_LOONGSON2
+ li k0, MIPS_DIAG_BTB_CLEAR
+ mtc0 k0, MIPS_COP_0_DIAG
+#endif
_MFC0 k0, MIPS_COP_0_BAD_VADDR #00: k0=bad address
lui k1, %hi(CPUVAR(PMAP_SEG0TAB)) #01: k1=hi of seg0tab
bltz k0, MIPSX(kernelfault) #02: k0<0 -> 4f (kernel fault)
@@ -360,10 +364,12 @@
_SLL k1, WIRED_SHIFT #14: chop top 2 bits (part 2a)
_SRL k1, WIRED_SHIFT #15: chop top 2 bits (part 2b)
_MTC0 k1, MIPS_COP_0_TLB_LO1 #16: lo1 is loaded
+#ifndef MIPS3_LOONGSON2
sll $0, $0, 3 #17: standard nop (ehb)
#ifdef MIPS3
nop #18: extra nop for QED5230
#endif
+#endif
tlbwr #19: write to tlb
sll $0, $0, 3 #1a: standard nop (ehb)
#if (MIPS3 + MIPS64 + MIPS64R2) > 0
@@ -434,7 +440,7 @@
li k1, MIPS_KSEG1_START #04
or k0, k1 #05
lui k1, %hi(CPUVAR(CURLWP)) #06: k1=hi of curlwp
- j k0 #07
+ jr k0 #07
PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #08: k1=lo of curlwp
_VECTOR_END(MIPSX(cache))
@@ -475,7 +481,7 @@
# we dont have to shift.
PTR_L k0, 0(k0) #09: get the function address
lui k1, %hi(CPUVAR(CURLWP)) #0a: k1=hi of curlwp
- j k0 #0b: jump to the function
+ jr k0 #0b: jump to the function
PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #0c: k1=lo of curlwp
nop #0d
nop #0e
@@ -510,7 +516,7 @@
PTR_LA k0, MIPSX(kern_intr) #07: nope, kernel intr
1:
lui k1, %hi(CPUVAR(CURLWP)) #09: k1=hi of curlwp
- j k0 #0a: jump to the function
+ jr k0 #0a: jump to the function
PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #0b: k1=lo of curlwp
.set at
_VECTOR_END(MIPSX(intr))
@@ -995,6 +1001,10 @@
/*
* Save a minimum of registers to see if this is rdhwr $3,$29
*/
+#ifdef MIPS3_LOONGSON2
+ li k0, MIPS_DIAG_BTB_CLEAR
+ mtc0 k0, MIPS_COP_0_DIAG
+#endif
/* K1 already has CURLWP */
PTR_L k0, L_PCB(k1) # XXXuvm_lwp_getuarea
PTR_ADDU k0, USPACE - TF_SIZ - CALLFRAME_SIZ
@@ -1091,13 +1101,13 @@
_MFC0 a3, MIPS_COP_0_EXC_PC # 4th arg is exception PC
REG_S t8, CALLFRAME_SIZ+TF_REG_T8(k0) # will be MIPS_CURLWP
REG_S t9, CALLFRAME_SIZ+TF_REG_T9(k0)
+ REG_S v0, CALLFRAME_SIZ+TF_REG_MULLO(k0)
+ REG_S v1, CALLFRAME_SIZ+TF_REG_MULHI(k0)
REG_S gp, CALLFRAME_SIZ+TF_REG_GP(k0)
REG_S sp, CALLFRAME_SIZ+TF_REG_SP(k0)
REG_S s8, CALLFRAME_SIZ+TF_REG_S8(k0)
REG_S ra, CALLFRAME_SIZ+TF_REG_RA(k0)
REG_S a0, CALLFRAME_SIZ+TF_REG_SR(k0)
- REG_S v0, CALLFRAME_SIZ+TF_REG_MULLO(k0)
- REG_S v1, CALLFRAME_SIZ+TF_REG_MULHI(k0)
REG_S a3, CALLFRAME_SIZ+TF_REG_EPC(k0)
#ifdef __GP_SUPPORT__
PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
@@ -1873,7 +1883,7 @@
PTR_S t3, TLBMASK_HI(a1)
INT_S ta0, TLBMASK_LO0(a1)
INT_S ta1, TLBMASK_LO1(a1)
- j ra
+ jr ra
INT_S t2, TLBMASK_MASK(a1)
END(MIPSX(tlb_read_indexed))
@@ -2299,6 +2309,10 @@
REG_L s6, CALLFRAME_SIZ+TF_REG_S6(sp) # $22
REG_L s7, CALLFRAME_SIZ+TF_REG_S7(sp) # $23
REG_L s8, CALLFRAME_SIZ+TF_REG_S8(sp) # $30
+#ifdef MIPS3_LOONGSON2
+ li t0, (MIPS_DIAG_BTB_CLEAR|MIPS_DIAG_ITLB_CLEAR)
+ mtc0 t0, MIPS_COP_0_DIAG
+#endif
MIPSX(user_intr_return):
#ifdef PARANOIA
PTR_L t0, L_CPU(MIPS_CURLWP)
@@ -2355,7 +2369,8 @@
# Call the routine specified by cpu_setfunc()
# and return directly to user_return
PTR_LA ra, MIPSX(user_return)
- jr s0
+ move t9, s0
+ jr t9
move a0, s1
END(MIPSX(setfunc_trampoline))
@@ -2437,7 +2452,7 @@
PTR_L v0, L_PRIVATE(a0) # get lwp private
_MTC0 v0, MIPS_COP_0_TLB_CONTEXT, 4 # make available for rdhwr
#endif
- j ra
+ jr ra
nop
END(MIPSX(cpu_switch_resume))
@@ -2604,7 +2619,7 @@
bgtz a1, 1b
addu a0, 64
- j ra
+ jr ra
nop
END(MIPSX(pagezero))
#endif /* USE_64BIT_INSTRUCTIONS */
