Module Name: src
Committed By: macallan
Date: Thu Sep 22 05:08:52 UTC 2011
Modified Files:
src/sys/arch/mips/include: cpu.h cpuregs.h mips3_pte.h pmap.h
src/sys/arch/mips/mips: bus_space_alignstride_chipdep.c mips_machdep.c
pmap.c
Log Message:
support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs
To generate a diff of this commit:
cvs rdiff -u -r1.105 -r1.106 src/sys/arch/mips/include/cpu.h
cvs rdiff -u -r1.86 -r1.87 src/sys/arch/mips/include/cpuregs.h
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/mips/include/mips3_pte.h
cvs rdiff -u -r1.60 -r1.61 src/sys/arch/mips/include/pmap.h
cvs rdiff -u -r1.15 -r1.16 \
src/sys/arch/mips/mips/bus_space_alignstride_chipdep.c
cvs rdiff -u -r1.248 -r1.249 src/sys/arch/mips/mips/mips_machdep.c
cvs rdiff -u -r1.203 -r1.204 src/sys/arch/mips/mips/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cpu.h
diff -u src/sys/arch/mips/include/cpu.h:1.105 src/sys/arch/mips/include/cpu.h:1.106
--- src/sys/arch/mips/include/cpu.h:1.105 Tue Aug 16 06:58:15 2011
+++ src/sys/arch/mips/include/cpu.h Thu Sep 22 05:08:52 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.105 2011/08/16 06:58:15 matt Exp $ */
+/* $NetBSD: cpu.h,v 1.106 2011/09/22 05:08:52 macallan Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -258,6 +258,7 @@
bool mips_has_llsc;
u_int mips3_pg_shift;
u_int mips3_pg_cached;
+ u_int mips3_cca_devmem;
#ifdef MIPS3_PLUS
#ifdef _LP64
uint64_t mips3_xkphys_cached;
Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.86 src/sys/arch/mips/include/cpuregs.h:1.87
--- src/sys/arch/mips/include/cpuregs.h:1.86 Sat Aug 27 13:23:52 2011
+++ src/sys/arch/mips/include/cpuregs.h Thu Sep 22 05:08:52 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.86 2011/08/27 13:23:52 bouyer Exp $ */
+/* $NetBSD: cpuregs.h,v 1.87 2011/09/22 05:08:52 macallan Exp $ */
/*
* Copyright (c) 2009 Miodrag Vallat.
@@ -135,6 +135,8 @@
#define MIPS_XKPHYS_START (0x2ULL << 62)
#define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
(MIPS_XKPHYS_START | ((uint64_t)(CCA_UNCACHED) << 59) | (x))
+#define MIPS_PHYS_TO_XKPHYS_ACC(x) \
+ (MIPS_XKPHYS_START | ((uint64_t)(mips_options.mips3_cca_devmem) << 59) | (x))
#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
(mips_options.mips3_xkphys_cached | (x))
#define MIPS_PHYS_TO_XKPHYS(cca,x) \
@@ -146,6 +148,7 @@
#define CCA_UNCACHED 2
#define CCA_CACHEABLE 3 /* cacheable non-coherent */
+#define CCA_ACCEL 7 /* non-cached, write combining */
/* CPU dependent mtc0 hazard hook */
#if (MIPS32R2 + MIPS64R2) > 0
Index: src/sys/arch/mips/include/mips3_pte.h
diff -u src/sys/arch/mips/include/mips3_pte.h:1.27 src/sys/arch/mips/include/mips3_pte.h:1.28
--- src/sys/arch/mips/include/mips3_pte.h:1.27 Sun Feb 20 07:45:47 2011
+++ src/sys/arch/mips/include/mips3_pte.h Thu Sep 22 05:08:52 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: mips3_pte.h,v 1.27 2011/02/20 07:45:47 matt Exp $ */
+/* $NetBSD: mips3_pte.h,v 1.28 2011/09/22 05:08:52 macallan Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -88,7 +88,11 @@
#define MIPS3_PG_TO_CCA(cca) (((cca) >> 3) & 7)
#define MIPS3_XPHYS_UNCACHED MIPS_PHYS_TO_XKPHYS(2, 0)
+#define MIPS3_XPHYS_ACC MIPS_PHYS_TO_XKPHYS(mips_options.mips3_cca_devmem, 0)
+
#define MIPS3_PG_UNCACHED MIPS3_CCA_TO_PG(2)
+#define MIPS3_PG_WT MIPS3_CCA_TO_PG(5)
+#define MIPS3_PG_ACC MIPS3_CCA_TO_PG(mips_options.mips3_cca_devmem)
#ifdef HPCMIPS_L1CACHE_DISABLE /* MIPS3_L1CACHE_DISABLE */
#define MIPS3_DEFAULT_XKPHYS_CACHED MIPS3_DEFAULT_XKPHYS_UNCACHED
#define MIPS3_PG_CACHED MIPS3_PG_UNCACHED /* XXX: brain damaged!!! */
@@ -108,12 +112,18 @@
/* Not wr-prot not clean not cached */
#define MIPS3_PG_RWNCPAGE (MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_UNCACHED)
+/* Not wr-prot not clean not cached, accel */
+#define MIPS3_PG_RWAPAGE (MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_ACC)
+
/* Not wr-prot but clean */
#define MIPS3_PG_CWPAGE (MIPS3_PG_V | MIPS3_PG_CACHED)
/* Not wr-prot but clean not cached*/
#define MIPS3_PG_CWNCPAGE (MIPS3_PG_V | MIPS3_PG_UNCACHED)
+/* Not wr-prot but clean not cached, accel*/
+#define MIPS3_PG_CWAPAGE (MIPS3_PG_V | MIPS3_PG_ACC)
+
#define MIPS3_PG_IOPAGE(cca) \
(MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_D | MIPS3_CCA_TO_PG(cca))
#define MIPS3_PG_FRAME 0x3fffffc0
Index: src/sys/arch/mips/include/pmap.h
diff -u src/sys/arch/mips/include/pmap.h:1.60 src/sys/arch/mips/include/pmap.h:1.61
--- src/sys/arch/mips/include/pmap.h:1.60 Sun Feb 20 07:45:47 2011
+++ src/sys/arch/mips/include/pmap.h Thu Sep 22 05:08:52 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.60 2011/02/20 07:45:47 matt Exp $ */
+/* $NetBSD: pmap.h,v 1.61 2011/09/22 05:08:52 macallan Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -311,6 +311,7 @@
#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
#define PGC_NOCACHE 0x4000000000000000ULL
+#define PGC_PREFETCH 0x2000000000000000ULL
#endif
#define __HAVE_VM_PAGE_MD
Index: src/sys/arch/mips/mips/bus_space_alignstride_chipdep.c
diff -u src/sys/arch/mips/mips/bus_space_alignstride_chipdep.c:1.15 src/sys/arch/mips/mips/bus_space_alignstride_chipdep.c:1.16
--- src/sys/arch/mips/mips/bus_space_alignstride_chipdep.c:1.15 Sun Jul 10 23:13:22 2011
+++ src/sys/arch/mips/mips/bus_space_alignstride_chipdep.c Thu Sep 22 05:08:52 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space_alignstride_chipdep.c,v 1.15 2011/07/10 23:13:22 matt Exp $ */
+/* $NetBSD: bus_space_alignstride_chipdep.c,v 1.16 2011/09/22 05:08:52 macallan Exp $ */
/*-
* Copyright (c) 1998, 2000, 2001 The NetBSD Foundation, Inc.
@@ -81,7 +81,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_space_alignstride_chipdep.c,v 1.15 2011/07/10 23:13:22 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_space_alignstride_chipdep.c,v 1.16 2011/09/22 05:08:52 macallan Exp $");
#ifdef CHIP_EXTENT
#include <sys/extent.h>
@@ -354,6 +354,8 @@
#ifdef _LP64
if (flags & BUS_SPACE_MAP_CACHEABLE)
*hp = MIPS_PHYS_TO_XKPHYS_CACHED(addr);
+ else if (flags & BUS_SPACE_MAP_PREFETCHABLE)
+ *hp = MIPS_PHYS_TO_XKPHYS_ACC(addr);
else
*hp = MIPS_PHYS_TO_XKPHYS_UNCACHED(addr);
#else
@@ -615,6 +617,7 @@
/* Not supported for I/O space. */
return (-1);
#elif defined(CHIP_MEM)
+ paddr_t ret;
struct mips_bus_space_translation mbst;
int error;
@@ -625,9 +628,13 @@
&mbst);
if (error)
return (-1);
-
- return (mips_btop(mbst.mbst_sys_start +
- (addr - mbst.mbst_bus_start) + off));
+ ret = mbst.mbst_sys_start + (addr - mbst.mbst_bus_start) + off;
+ if (flags & BUS_SPACE_MAP_PREFETCHABLE) {
+ printf("!");
+ ret |= PGC_PREFETCH;
+ }
+
+ return (mips_btop(ret));
#else
# error must define one of CHIP_IO or CHIP_MEM
#endif
Index: src/sys/arch/mips/mips/mips_machdep.c
diff -u src/sys/arch/mips/mips/mips_machdep.c:1.248 src/sys/arch/mips/mips/mips_machdep.c:1.249
--- src/sys/arch/mips/mips/mips_machdep.c:1.248 Sat Aug 27 16:54:14 2011
+++ src/sys/arch/mips/mips/mips_machdep.c Thu Sep 22 05:08:52 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.248 2011/08/27 16:54:14 bouyer Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.249 2011/09/22 05:08:52 macallan Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -112,7 +112,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.248 2011/08/27 16:54:14 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.249 2011/09/22 05:08:52 macallan Exp $");
#define __INTR_PRIVATE
#include "opt_cputype.h"
@@ -719,7 +719,6 @@
/* Cache error handler */
extern char mips3_cache[];
-
/*
* Copy down exception vector code.
*/
@@ -1186,6 +1185,7 @@
#endif
opts->mips3_pg_shift = MIPS3_DEFAULT_PG_SHIFT;
+ opts->mips3_cca_devmem = CCA_UNCACHED;
if (opts->mips_cpu_flags & CPU_MIPS_HAVE_SPECIAL_CCA) {
uint32_t cca;
@@ -1265,6 +1265,7 @@
mips3_cp0_wired_write(pmap_tlb0_info.ti_wired);
loongson2_vector_init(splsw);
mips_locoresw = loongson2_locoresw;
+ opts->mips3_cca_devmem = CCA_ACCEL;
break;
}
#endif /* MIPS3_LOONGSON2 */
@@ -1273,6 +1274,7 @@
mips3_vector_init(splsw);
mips_locoresw = mips3_locoresw;
break;
+
#endif /* MIPS3 */
#if defined(MIPS32)
case CPU_ARCH_MIPS32:
Index: src/sys/arch/mips/mips/pmap.c
diff -u src/sys/arch/mips/mips/pmap.c:1.203 src/sys/arch/mips/mips/pmap.c:1.204
--- src/sys/arch/mips/mips/pmap.c:1.203 Wed Sep 21 16:37:54 2011
+++ src/sys/arch/mips/mips/pmap.c Thu Sep 22 05:08:52 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.203 2011/09/21 16:37:54 macallan Exp $ */
+/* $NetBSD: pmap.c,v 1.204 2011/09/22 05:08:52 macallan Exp $ */
/*-
* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
@@ -67,7 +67,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.203 2011/09/21 16:37:54 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.204 2011/09/22 05:08:52 macallan Exp $");
/*
* Manages physical address maps.
@@ -1374,6 +1374,9 @@
struct vm_page *pg;
bool cached = true;
bool wired = (flags & PMAP_WIRED) != 0;
+#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
+ bool prefetch = false;
+#endif
#ifdef DEBUG
if (pmapdebug & (PDB_FOLLOW|PDB_ENTER))
@@ -1416,6 +1419,10 @@
cached = false;
pa &= ~PGC_NOCACHE;
}
+ if (pa & PGC_PREFETCH) {
+ prefetch = true;
+ pa &= ~PGC_PREFETCH;
+ }
#endif
pg = PHYS_TO_VM_PAGE(pa);
@@ -1459,12 +1466,15 @@
* then it must be device memory which may be volatile.
*/
if (MIPS_HAS_R4K_MMU) {
+#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
+ u_int cca = PMAP_CCA_FOR_PA(pa);
+ if (prefetch) cca = mips_options.mips3_cca_devmem;
+ npte = MIPS3_PG_IOPAGE(cca) &
+ ~MIPS3_PG_G;
+#else
npte = MIPS3_PG_IOPAGE(PMAP_CCA_FOR_PA(pa)) &
~MIPS3_PG_G;
- if ((prot & VM_PROT_WRITE) == 0) {
- npte |= MIPS3_PG_RO;
- npte &= ~MIPS3_PG_D;
- }
+#endif
} else {
npte = (prot & VM_PROT_WRITE) ?
(MIPS1_PG_D | MIPS1_PG_N) :
