Module Name: src
Committed By: macallan
Date: Wed Dec 7 08:49:29 UTC 2011
Modified Files:
src/sys/dev/ic: sm502reg.h
Log Message:
add a bunch of register definitions
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/dev/ic/sm502reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/sm502reg.h
diff -u src/sys/dev/ic/sm502reg.h:1.4 src/sys/dev/ic/sm502reg.h:1.5
--- src/sys/dev/ic/sm502reg.h:1.4 Tue Nov 8 06:56:36 2011
+++ src/sys/dev/ic/sm502reg.h Wed Dec 7 08:49:29 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: sm502reg.h,v 1.4 2011/11/08 06:56:36 macallan Exp $ */
+/* $NetBSD: sm502reg.h,v 1.5 2011/12/07 08:49:29 macallan Exp $ */
/*
* Copyright (c) 2009 Michael Lorenz
@@ -59,6 +59,7 @@
#define SM502_SYSCTL_DISABLE_VSYNC 0x80000000
#define SM502_MISC_CONTROL 0x00000004
+#define SM502_DAC_POWER_DOWN 0x00001000
/* each bit: 0 - GPIO, 1 - other stuff */
#define SM502_GPIO0_CONTROL 0x00000008
#define SM502_GPIO1_CONTROL 0x0000000c
@@ -112,6 +113,20 @@
#define SM502_DEBUG_CONTROL 0x00000034
#define SM502_CURRENT_GATE 0x00000038
+#define SM502_GATE_AUDIO_ENABLE 0x00040000
+#define SM502_GATE_8051_ENABLE 0x00020000
+#define SM502_GATE_USB_SLAVE_ENABLE 0x00001000
+#define SM502_GATE_USB_HOST_ENABLE 0x00000800
+#define SM502_GATE_SSP_ENABLE 0x00000400
+#define SM502_GATE_UART1_ENABLE 0x00000100
+#define SM502_GATE_UART0_ENABLE 0x00000080
+#define SM502_GATE_GPIO_ENABLE 0x00000040
+#define SM502_GATE_ZV_ENABLE 0x00000020
+#define SM502_GATE_CSC_ENABLE 0x00000010
+#define SM502_GATE_2D_ENGINE_ENABLE 0x00000008
+#define SM502_GATE_DISPLAY_ENABLE 0x00000004
+#define SM502_GATE_MEMORY_ENABLE 0x00000002
+#define SM502_GATE_HOST_ENABLE 0x00000001
#define SM502_CURRENT_CLOCK 0x0000003c
#define SM502_POWER_MODE0_GATE 0x00000040
#define SM502_POWER_MODE0_CLOCK 0x00000044
@@ -364,4 +379,63 @@
#define SM502_DATAPORT 0x110000
+/* AC97 Link */
+#define SM502_AC97_TX_TAG 0x0A0100
+#define SM502_AC97_FRAME_VALID 0x8000
+#define SM502_AC97_S1_VALID 0x4000
+#define SM502_AC97_S2_VALID 0x2000
+#define SM502_AC97_S3_VALID 0x1000
+#define SM502_AC97_S4_VALID 0x0800
+#define SM502_AC97_TX_ADDR 0x0A0104
+#define SM502_AC97_READ 0x00100000 /* write otherwise */
+#define SM502_AC97_ADDR_MASK 0x000fe000
+#define SM502_AC97_TX_DATA 0x0A0108
+#define SM502_AC97_DATA_MASK 0x000ffff0
+#define SM502_AC97_TX_LEFT 0x0A010C
+#define SM502_AC97_TX_RIGHT 0x0A0110
+#define SM502_AC97_RX_TAG 0x0A0140
+#define SM502_AC97_RX_ADDR 0x0A0144
+#define SM502_AC97_RX_DATA 0x0A0148
+#define SM502_AC97_RX_LEFT 0x0A014C
+#define SM502_AC97_RX_RIGHT 0x0A0150
+#define SM502_AC97_CONTROL 0x0A0180
+#define SM502_AC97_DROP_COUNT 0x0000fc00
+#define SM502_AC97_STOP_SYNC 0x00000200
+#define SM502_AC97_BCLK_RUNNING 0x00000100
+#define SM502_AC97_WAKEUP_REQ 0x00000080
+#define SM502_AC97_STATUS_MASK 0x00000030
+#define SM502_AC97_STATUS_OFF 0x00000000
+#define SM502_AC97_STATUS_RESET 0x00000010
+#define SM502_AC97_STATUS_WAIT 0x00000020
+#define SM502_AC97_STATUS_ON 0x00000030
+#define SM502_AC97_WI_ENABLE 0x00000008 /* wakeup interrupt */
+#define SM502_AC97_WARM_RESET 0x00000004 /* 1uS at least */
+#define SM502_AC97_COLD_RESET 0x00000002 /* 1uS at least */
+#define SM502_AC97_ENABLE 0x00000001
+
+#define SM502_AUDIO_GPIO_MASK 0x1f000000 /* pins used */
+
+/* 8051 Microcontroller */
+#define SM502_uC_RESET 0x000b0000
+#define SM502_uC_ENABLE 0x00000001 /* reset otherwise */
+#define SM502_uC_MODE_SELECT 0x000b0004
+#define SM502_uC_CLOCK_MASK 0x00000003
+#define SM502_uC_CLOCK_DIV2 0x00000000
+#define SM502_uC_CLOCK_DIV3 0x00000001
+#define SM502_uC_CLOCK_DIV4 0x00000002
+#define SM502_uC_CLOCK_DIV5 0x00000003
+#define SM502_uC_CODEC_I2S 0x00000004 /* AC97 otherwise */
+#define SM502_uC_AUDIO_TEST 0x00000008 /* test mode */
+#define SM502_uC_IO_8BIT 0x00000010 /* 12 bit otherwise */
+#define SM502_uC_SRAM_DISABLE 0x00000020
+#define SM502_uC_USB_WAIT_MASK 0x000000c0
+#define SM502_uC_USB_NO_WAIT 0x00000000
+#define SM502_uC_USB_1_WAIT 0x00000040
+#define SM502_uC_USB_2_WAIT 0x00000080
+#define SM502_uC_8051_INTR 0x000b0008
+#define SM502_uC_CPU_INTR 0x000b000c
+
+#define SM502_uC_SRAM_PROG 0x00dc0000 /* only readable in RESET */
+#define SM502_uC_SRAM_DATA 0x00dc3000
+
#endif /* SM502REG_H */
