Module Name: src
Committed By: matt
Date: Fri Dec 23 08:06:09 UTC 2011
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: mipsNN.h
Log Message:
Add CFG6/7 definitions for MIPS 24K/74K/34K/1004K/1074K and RMI XLP.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.4.84.1 src/sys/arch/mips/include/mipsNN.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/mipsNN.h
diff -u src/sys/arch/mips/include/mipsNN.h:1.4 src/sys/arch/mips/include/mipsNN.h:1.4.84.1
--- src/sys/arch/mips/include/mipsNN.h:1.4 Mon Mar 20 18:31:29 2006
+++ src/sys/arch/mips/include/mipsNN.h Fri Dec 23 08:06:09 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsNN.h,v 1.4 2006/03/20 18:31:29 gdamore Exp $ */
+/* $NetBSD: mipsNN.h,v 1.4.84.1 2011/12/23 08:06:09 matt Exp $ */
/*
* Copyright 2000, 2001
@@ -233,6 +233,45 @@
/* "M" (R): Configuration Register 4 present. */
#define MIPSNN_CFG3_M 0x80000000
+/* "BPG" (R): Big Pages feature is implemented (PageMask is 64-bits wide). */
+#define MIPSNN_CFG3_BPG 0x40000000
+
+/* "CMGCR" (R): Coherency Manager memory-mapped Global Configuration Register Space is implemented. */
+#define MIPSNN_CFG3_CMGCR 0x20000000
+
+/* "ULRI" (R): User Local Register Implemented. */
+#define MIPSNN_CFG3_ULRI 0x00000800
+
+/* "IPLW" (R): Width of Status[IPL] and Cause[RIPL] fields. */
+#define MIPSNN_CFG3_IPLW_MASK 0x00600000
+#define MIPSNN_CFG3_IPLW_SHIFT 21
+
+#define MIPSNN_CFG3_IPLW_6BITS 0 /* IPL and RIPL fields are 6-bits in width. */
+#define MIPSNN_CFG3_IPLW_8BITS 1 /* IPL and RIPL fields are 8-bits in width. */
+// reserved other values
+
+/* "MMAR" (R): microMIPS64 Architecture revision level. */
+#define MIPSNN_CFG3_MMAR_MASK 0x001c0000
+#define MIPSNN_CFG3_MMAR_SHIFT 18
+
+#define MIPSNN_CFG3_MMAR_REV1 0 /* Revision 1 */
+// reserved other values
+
+/* "MCU" (R): MCU ASE extension present. */
+#define MIPSNN_CFG3_MCU 0x00020000
+
+/* "ISAOnExc" (R): ISA used on exception. */
+#define MIPSNN_CFG3_ISAOnExc 0x00010000 /* microMIPS used on entrance to exception vector */
+
+/* "ISA" (R): Instruction Set Availability. */
+#define MIPSNN_CFG3_ISA_MASK 0x0000c000
+#define MIPSNN_CFG3_ISA_SHIFT 14
+
+#define MIPSNN_CFG3_ISA_MIPS64 0 /* only MIPS64 */
+#define MIPSNN_CFG3_ISA_microMIPS64 1 /* only microMIPS64 */
+#define MIPSNN_CFG3_ISA_MIPS64_OOR 2 /* both, MIPS64 out of reset */
+#define MIPSNN_CFG3_ISA_microMIPS64_OOR 3 /* both, microMIPS64 OOR */
+
/* "DSPP" (R): DSPP ASE extension present. */
#define MIPSNN_CFG3_DSPP 0x00000400
@@ -256,3 +295,205 @@
/* "TL" (R): Trace Logic implemented. */
#define MIPSNN_CFG3_TL 0x00000001
+
+/*
+ * Values in Configuration Register 6 (CP0 Register 16, Select 6)
+ * for RMI XLP processors
+ */
+
+/* "CTLB_SIZE" (R): Number of Combined TLB entries - 1. */
+#define MIPSNN_RMIXLP_CFG6_CTLB_SIZE_MASK 0xffff0000
+#define MIPSNN_RMIXLP_CFG6_CTLB_SIZE_SHIFT 16
+
+/* "VTLB_SIZE" (R): Number of Variable TLB entries - 1. */
+#define MIPSNN_RMIXLP_CFG6_VTLB_SIZE_MASK 0x0000ffc0
+#define MIPSNN_RMIXLP_CFG6_VTLB_SIZE_SHIFT 6
+
+/* "ELVT" (RW): Enable Large Variable TLB. */
+#define MIPSNN_RMIXLP_CFG6_ELVT 0x00000020
+
+/* "EPW" (RW): Enable PageWalker. */
+#define MIPSNN_RMIXLP_CFG6_EPW 0x00000008
+
+/* "EFT" (RW): Enable Fixed TLB. */
+#define MIPSNN_RMIXLP_CFG6_EFT 0x00000004
+
+/* "PWI" (R): PageWalker implemented. */
+#define MIPSNN_RMIXLP_CFG6_PWI 0x00000001
+
+/* "FTI" (R): Fixed TLB implemented. */
+#define MIPSNN_RMIXLP_CFG6_FTI 0x00000001
+
+/*
+ * Values in Configuration Register 7 (CP0 Register 16, Select 7)
+ * for RMI XLP processors
+ */
+
+/* "LG" (RW): Small or Large Page. */
+#define MIPSNN_RMIXLP_CFG7_LG_MASK __BIT(61)
+
+/* "MASKLG" (RW): large page size supported in CAM only. */
+#define MIPSNN_RMIXLP_CFG7_MASKLG_MASK 0x0000ff00
+#define MIPSNN_RMIXLP_CFG7_MASKLG_SHIFT 8
+
+#define MIPSNN_RMIXLP_CFG7_MASKLG_4KB (0xff >> 8)
+#define MIPSNN_RMIXLP_CFG7_MASKLG_16KB (0xff >> 7)
+#define MIPSNN_RMIXLP_CFG7_MASKLG_64KB (0xff >> 6)
+#define MIPSNN_RMIXLP_CFG7_MASKLG_256KB (0xff >> 5)
+#define MIPSNN_RMIXLP_CFG7_MASKLG_1MB (0xff >> 4)
+#define MIPSNN_RMIXLP_CFG7_MASKLG_4MB (0xff >> 3)
+#define MIPSNN_RMIXLP_CFG7_MASKLG_16MB (0xff >> 2)
+#define MIPSNN_RMIXLP_CFG7_MASKLG_64MB (0xff >> 1)
+#define MIPSNN_RMIXLP_CFG7_MASKLG_256MB (0xff >> 0)
+
+/* "MASKSM" (RW): small page size supported in CAM/RAM. */
+#define MIPSNN_RMIXLP_CFG7_MASKSM_MASK 0x000000ff
+#define MIPSNN_RMIXLP_CFG7_MASKSM_SHIFT 0
+
+#define MIPSNN_RMIXLP_CFG7_MASKSM_4KB (0xff >> 8)
+#define MIPSNN_RMIXLP_CFG7_MASKSM_16KB (0xff >> 7)
+#define MIPSNN_RMIXLP_CFG7_MASKSM_64KB (0xff >> 6)
+#define MIPSNN_RMIXLP_CFG7_MASKSM_256KB (0xff >> 5)
+#define MIPSNN_RMIXLP_CFG7_MASKSM_1MB (0xff >> 4)
+#define MIPSNN_RMIXLP_CFG7_MASKSM_4MB (0xff >> 3)
+#define MIPSNN_RMIXLP_CFG7_MASKSM_16MB (0xff >> 2)
+#define MIPSNN_RMIXLP_CFG7_MASKSM_64MB (0xff >> 1)
+#define MIPSNN_RMIXLP_CFG7_MASKSM_256MB (0xff >> 0)
+
+/*
+ * Values in Configuration Register 6 (CP0 Register 16, Select 6)
+ * for the MTI 74K and 1074K cores.
+ */
+/* "SPCD" (R/W): Sleep state Perforance Counter Disable. */
+#define MIPSNN_MTI_CFG6_SPCD __BIT(14)
+
+/* "SYND" (R/W): SYNonym tag update Disable. */
+#define MIPSNN_MTI_CFG6_SYND __BIT(13)
+
+/* "IFUPerfCtl" (R/W): IFU Performance Control. */
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_MASK __BIT(12:10)
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_STALL 0
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_JUMP 1
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_STALLED_INSN 2
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CACHE_MISPREDICTION 3
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CACHE_PREDICTION 4
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_BAD_JR_CACHE_ENTRY 5
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_UNIMPL 6
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CBRACH_TAKEN 7
+
+/* "NMRUP" (R): Most Recently Used JTLB Replacement scheme Present. */
+#define MIPSNN_MTI_CFG6_NMRUP __BIT(9) /* 1: implemented */
+
+/* "NMRUD" (R/W): NMRU Disable. */
+#define MIPSNN_MTI_CFG6_NMRUD __BIT(8) /* 1: TLBWR is random */
+
+/* "JRCP" (R): JR Cache Present. */
+#define MIPSNN_MTI_CFG6_JRCP __BIT(1) /* 1: implemented */
+
+/* "JRCD" (R/W): JR Cache prediction Disable. */
+#define MIPSNN_MTI_CFG6_JRCD __BIT(0) /* 1: disabled */
+
+
+/*
+ * Values in Configuration Register 7 (CP0 Register 16, Select 7)
+ * for the MTI 24K, 34K, 74K, 1004K, and 1074K cores
+ */
+
+/* "WII" (R): Wait IE Ignore. */
+#define MIPSNN_MTI_CFG7_WII __BIT(31)
+
+/* "FPFS" (R/W): Fast Prepare For Store (74K, 1074K) */
+#define MIPSNN_MTI_CFG7_FPFS __BIT(30)
+
+/* "IHB" (R/W): Implicit HB (74K, 1074K) */
+#define MIPSNN_MTI_CFG7_IHB __BIT(29)
+
+/* "FPR1" (R): Float Point Ratio 1 (74K, 1074K). */
+#define MIPSNN_MTI_CFG7_FPR1 __BIT(28) /* 1: 3:2 */
+
+/* "SEHB" (R/W): slow EHB (74K, 1074K) */
+#define MIPSNN_MTI_CFG7_SEHB __BIT(27)
+
+/* "CP2IO" (R/W): Force COP2 data to be in-order (74K, 1074K) */
+#define MIPSNN_MTI_CFG7_CP2IO __BIT(26)
+
+/* "IAGN" (R/W): Issue LSU-side instructions in program order (74K, 1074K) */
+#define MIPSNN_MTI_CFG7_IAGN __BIT(25)
+
+/* "IAGN" (R/W): Issue LSU-side instructions in program order (74K, 1074K) */
+#define MIPSNN_MTI_CFG7_IAGN __BIT(25)
+
+/* "IALU" (R/W): Issue ALU-side instructions in program order (74K, 1074K) */
+#define MIPSNN_MTI_CFG7_IALU __BIT(24)
+
+/* "DGHR" (R/W): disable global history in branch prediction (74K, 1074K). */
+#define MIPSNN_MTI_CFG7_DGHR __BIT(23) /* 1: disable */
+
+/* "SG" (R/W): Single Graduation per cycle (74K, 1074K). */
+#define MIPSNN_MTI_CFG7_SG __BIT(22) /* 1: no superscalar */
+
+/* "SUI" (R/W): Strict Uncached Instruction (SUI) policy control (74K, 1074K). */
+#define MIPSNN_MTI_CFG7_SUI __BIT(21)
+
+/* "NCWB" (R/W): Non-Choerent WriteBack (1004K). */
+#define MIPSNN_MTI_CFG7_NCWB __BIT(20)
+
+/* "PCT" (R): Performance Counters per TC (34K, 1004K). */
+#define MIPSNN_MTI_CFG7_PCT __BIT(19)
+
+/* "HCI" (R): Hardware Cache Initialization. */
+#define MIPSNN_MTI_CFG7_HCI __BIT(18)
+
+/* "FPR" (R): Float Point Ratio. */
+#define MIPSNN_MTI_CFG7_FPR0 __BIT(17) /* 1: half speed */
+
+#define MIPSNN_MTI_CFG7_FPR_MASK (MIPSNN_MTI_CFG7_FPR1|MIPSNN_MTI_CFG7_FPR0)
+#define MIPSNN_MTI_CFG7_FPR_SHIFT 0
+#define MIPSNN_MTI_CFG7_FPR_1to1 0
+#define MIPSNN_MTI_CFG7_FPR_2to1 MIPSNN_MTI_CFG7_FPR0
+#define MIPSNN_MTI_CFG7_FPR_3to2 MIPSNN_MTI_CFG7_FPR1
+#define MIPSNN_MTI_CFG7_FPR_RESERVED MIPSNN_MTI_CFG7_FPR_MASK
+
+/* "AR" (R): Alias Removal. */
+#define MIPSNN_MTI_CFG7_AR __BIT(16) /* 1: no virt aliases */
+
+/* "PREF" (R/W): Instruction Prefetching (74K, 1074K). */
+#define MIPSNN_MTI_CFG7_PREF_MASK __BITS(12:11)
+#define MIPSNN_MTI_CFG7_PREF_SHIFT 11
+#define MIPSNN_MTI_CFG7_PREF_DISABLE 0
+#define MIPSNN_MTI_CFG7_PREF_ONELINE 1
+#define MIPSNN_MTI_CFG7_PREF_RESERVED 2
+#define MIPSNN_MTI_CFG7_PREF_TWOLINES 3
+
+/* "IAR" (R): Instruction Alias Removal. */
+#define MIPSNN_MTI_CFG7_IAR __BIT(10) /* 1: no virt aliases */
+
+/* "IVA" (R or RW): Instruction Virtual Alias fix disable. */
+#define MIPSNN_MTI_CFG7_IVA __BIT(9) /* 1: fix disable */
+
+/* "ES" (RW): External Sync. */
+#define MIPSNN_MTI_CFG7_ES __BIT(8)
+
+/* "BTLM" (RW): Block TC on Load Miss. */
+#define MIPSNN_MTI_CFG7_BTLM __BIT(7)
+
+/* "CPOOO" (RW): Out-Of-Order on Coprocessor interfaces (COP0/COP1). */
+#define MIPSNN_MTI_CFG7_CPOOO __BIT(6) /* 1: disable OOO */
+
+/* "NBLSU" (RW): Non-Blocking LSU. (24K, 34K) */
+#define MIPSNN_MTI_CFG7_NBLSU __BIT(5) /* 1: stalls pipeline */
+
+/* "UBL" (RW): Uncached Loads Blocking. */
+#define MIPSNN_MTI_CFG7_UBL __BIT(4) /* 1: blocking loads */
+
+/* "BP" (RW): Branch Prediction. */
+#define MIPSNN_MTI_CFG7_BP __BIT(3) /* 1: disabled */
+
+/* "RPS" (RW): Return Prediction Stack. */
+#define MIPSNN_MTI_CFG7_RPS __BIT(2) /* 1: disabled */
+
+/* "BHT" (RW): Branch History Table. */
+#define MIPSNN_MTI_CFG7_BHT __BIT(1) /* 1: disabled */
+
+/* "SL" (RW): Scheduled Loads. */
+#define MIPSNN_MTI_CFG7_SL __BIT(0) /* 1: load misses block */
