CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips

[Matt Thomas]

Module Name:    src
Committed By:   matt
Date:           Fri Dec 23 22:33:21 UTC 2011

Modified Files:
        src/sys/arch/mips/mips [matt-nb5-mips64]: trap.c

Log Message:
Cleanup AST processing.


To generate a diff of this commit:
cvs rdiff -u -r1.217.12.38 -r1.217.12.39 src/sys/arch/mips/mips/trap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/mips/mips/trap.c
diff -u src/sys/arch/mips/mips/trap.c:1.217.12.38 src/sys/arch/mips/mips/trap.c:1.217.12.39
--- src/sys/arch/mips/mips/trap.c:1.217.12.38	Fri Dec 23 06:49:03 2011
+++ src/sys/arch/mips/mips/trap.c	Fri Dec 23 22:33:20 2011
@@ -655,21 +655,25 @@ trap(uint32_t status, uint32_t cause, va
 
 /*
  * Handle asynchronous software traps.
- * This is called from MachUserIntr() either to deliver signals or
- * to make involuntary context switch (preemption).
+ * This is called on the return to userspace to flush icache, deliver signals,
+ * or to make involuntary context switch (preemption).  If astpending wasn't
+ * set, we wouldn't have been called so make at least pass through the
+ * function.
  */
 void
 ast(void)
 {
 	struct lwp * const l = curlwp;
-	u_int astpending;
 
-	while ((astpending = l->l_md.md_astpending) != 0) {
-		//uvmexp.softs++;
+	do {
 		l->l_md.md_astpending = 0;
 
 #ifdef MULTIPROCESSOR
-		{
+		/*
+		 * Before returning to userland, if some icache page indicies
+		 * have been marked bad then flush them from the icache.
+		 */
+		if (MIPS_HAS_R4K_MMU) {
 			kpreempt_disable();
 			struct cpu_info * const ci = l->l_cpu;
 			if (ci->ci_tlb_info->ti_synci_page_bitmap != 0)
@@ -691,7 +695,7 @@ ast(void)
 			 */
 			preempt();
 		}
-	}
+	} while (l->l_md.md_astpending != 0);
 }