Module Name: src
Committed By: matt
Date: Tue Jan 3 03:32:23 UTC 2012
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: mipsX_subr.S
Log Message:
If MIPS64R2_XLP, just let MIPSX(exception) do the work on cache exceptions.
(this might be generalized to all mipsNN with more testing).
To generate a diff of this commit:
cvs rdiff -u -r1.26.36.1.2.52 -r1.26.36.1.2.53 \
src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.52 src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.53
--- src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.52 Fri Dec 23 23:40:00 2011
+++ src/sys/arch/mips/mips/mipsX_subr.S Tue Jan 3 03:32:23 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.52 2011/12/23 23:40:00 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.53 2012/01/03 03:32:23 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -1535,6 +1535,11 @@ NESTED_NOPROFILE(MIPSX(cache_exception),
eret
nop
#endif
+#if (MIPS64R2_RMIXL) > 0
+ PTR_LA k0, MIPSX(exception) # switches to KSEG0
+ jr k0 # let common exception handle it
+ nop
+#else
PTR_LA k0, panic # return to panic
PTR_LA a0, 9f # panicstr
_MFC0 a1, MIPS_COP_0_ERROR_PC
@@ -1548,16 +1553,6 @@ NESTED_NOPROFILE(MIPSX(cache_exception),
#endif
mfc0 a4, MIPS_COP_0_STATUS
mfc0 a5, MIPS_COP_0_CAUSE
-#elif (MIPS64R2_RMIXL) > 0
- li k1, 0x308 /* LSU_CERR_LOG0 */
- mfcr a3, k1
- li k1, 0x309 /* LSU_CERR_LOG1 */
- mfcr a2, k1
-#if defined(__mips_o32)
-#error O32 not supported.
-#endif
- mfc0 a4, MIPS_COP_0_STATUS
- mfc0 a5, MIPS_COP_0_CAUSE
#else
mfc0 a2, MIPS_COP_0_ECC
mfc0 a3, MIPS_COP_0_CACHE_ERR
@@ -1574,11 +1569,12 @@ NESTED_NOPROFILE(MIPSX(cache_exception),
eret
-#if (MIPS64_RMIXL + MIPS64R2_RMIXL) > 0
+#if (MIPS64_RMIXL) > 0
MSG("cache error @ EPC %#llx\nL1D_CACHE_ERROR_LOG %#llx\nL1D_CACHE_INTERRUPT %#lx\nstatus %#x, cause %#x");
#else
MSG("cache error @ EPC 0x%x ErrCtl 0x%x CacheErr 0x%x");
#endif
+#endif
.set at
END(MIPSX(cache_exception))
