Module Name: xsrc
Committed By: rjs
Date: Sun Jun 3 16:42:23 UTC 2012
Modified Files:
xsrc/external/mit/xf86-video-ati/dist/src: r600_exa.c r6xx_accel.c
radeon_dri.c radeon_driver.c radeon_exa_funcs.c
radeon_textured_video.c
Log Message:
merge xf86-video-ati 6.14.4
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 xsrc/external/mit/xf86-video-ati/dist/src/r600_exa.c
cvs rdiff -u -r1.5 -r1.6 \
xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c
cvs rdiff -u -r1.7 -r1.8 \
xsrc/external/mit/xf86-video-ati/dist/src/radeon_dri.c \
xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c
cvs rdiff -u -r1.10 -r1.11 \
xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c
cvs rdiff -u -r1.2 -r1.3 \
xsrc/external/mit/xf86-video-ati/dist/src/radeon_textured_video.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: xsrc/external/mit/xf86-video-ati/dist/src/r600_exa.c
diff -u xsrc/external/mit/xf86-video-ati/dist/src/r600_exa.c:1.3 xsrc/external/mit/xf86-video-ati/dist/src/r600_exa.c:1.4
--- xsrc/external/mit/xf86-video-ati/dist/src/r600_exa.c:1.3 Sat Jul 23 08:27:24 2011
+++ xsrc/external/mit/xf86-video-ati/dist/src/r600_exa.c Sun Jun 3 16:42:22 2012
@@ -62,15 +62,11 @@ R600SetAccelState(ScrnInfoPtr pScrn,
memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object));
accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8);
#if defined(XF86DRM_MODE)
- if (info->cs) {
- pitch_align = drmmode_get_pitch_align(pScrn,
- accel_state->src_obj[0].bpp / 8,
- accel_state->src_obj[0].tiling_flags) - 1;
- base_align = drmmode_get_base_align(pScrn,
- accel_state->src_obj[0].bpp / 8,
- accel_state->src_obj[0].tiling_flags) - 1;
+ if (info->cs && src0->surface) {
+ accel_state->src_size[0] = src0->surface->bo_size;
}
#endif
+
/* bad pitch */
if (accel_state->src_obj[0].pitch & pitch_align)
RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[0].pitch));
@@ -88,15 +84,11 @@ R600SetAccelState(ScrnInfoPtr pScrn,
memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object));
accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8);
#if defined(XF86DRM_MODE)
- if (info->cs) {
- pitch_align = drmmode_get_pitch_align(pScrn,
- accel_state->src_obj[1].bpp / 8,
- accel_state->src_obj[1].tiling_flags) - 1;
- base_align = drmmode_get_base_align(pScrn,
- accel_state->src_obj[1].bpp / 8,
- accel_state->src_obj[1].tiling_flags) - 1;
+ if (info->cs && src1->surface) {
+ accel_state->src_size[1] = src1->surface->bo_size;
}
#endif
+
/* bad pitch */
if (accel_state->src_obj[1].pitch & pitch_align)
RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[1].pitch));
@@ -113,15 +105,13 @@ R600SetAccelState(ScrnInfoPtr pScrn,
memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object));
accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8);
#if defined(XF86DRM_MODE)
- if (info->cs) {
- pitch_align = drmmode_get_pitch_align(pScrn,
- accel_state->dst_obj.bpp / 8,
- accel_state->dst_obj.tiling_flags) - 1;
- base_align = drmmode_get_base_align(pScrn,
- accel_state->dst_obj.bpp / 8,
- accel_state->dst_obj.tiling_flags) - 1;
- }
+ if (info->cs && dst->surface) {
+ accel_state->dst_size = dst->surface->bo_size;
+ } else
#endif
+ {
+ accel_state->dst_obj.tiling_flags = 0;
+ }
if (accel_state->dst_obj.pitch & pitch_align)
RADEON_FALLBACK(("Bad dst pitch 0x%08x\n", accel_state->dst_obj.pitch));
@@ -132,6 +122,11 @@ R600SetAccelState(ScrnInfoPtr pScrn,
accel_state->dst_size = 0;
}
+#ifdef XF86DRM_MODE
+ if (info->cs && CS_FULL(info->cs))
+ radeon_cs_flush_indirect(pScrn);
+#endif
+
accel_state->rop = rop;
accel_state->planemask = planemask;
@@ -170,9 +165,6 @@ R600SetAccelState(ScrnInfoPtr pScrn,
return TRUE;
}
-static void
-R600DoneSolid(PixmapPtr pPix);
-
static Bool
R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
{
@@ -195,6 +187,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu
dst.offset = 0;
dst.bo = radeon_get_pixmap_bo(pPix);
dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
+ dst.surface = radeon_get_pixmap_surface(pPix);
} else
#endif
{
@@ -252,6 +245,9 @@ R600PrepareSolid(PixmapPtr pPix, int alu
cb_conf.h = accel_state->dst_obj.height;
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.bo = accel_state->dst_obj.bo;
+#ifdef XF86DRM_MODE
+ cb_conf.surface = accel_state->dst_obj.surface;
+#endif
if (accel_state->dst_obj.bpp == 8) {
cb_conf.format = COLOR_8;
@@ -282,7 +278,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
if (accel_state->dst_obj.tiling_flags == 0)
- cb_conf.array_mode = 1;
+ cb_conf.array_mode = 0;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_spi(pScrn, accel_state->ib, 0, 0);
@@ -318,9 +314,27 @@ R600PrepareSolid(PixmapPtr pPix, int alu
if (accel_state->vsync)
RADEONVlineHelperClear(pScrn);
+ accel_state->dst_pix = pPix;
+ accel_state->fg = fg;
+
return TRUE;
}
+static void
+R600DoneSolid(PixmapPtr pPix)
+{
+ ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+ if (accel_state->vsync)
+ r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix,
+ accel_state->vline_crtc,
+ accel_state->vline_y1,
+ accel_state->vline_y2);
+
+ r600_finish_op(pScrn, 8);
+}
static void
R600Solid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
@@ -330,6 +344,17 @@ R600Solid(PixmapPtr pPix, int x1, int y1
struct radeon_accel_state *accel_state = info->accel_state;
float *vb;
+#ifdef XF86DRM_MODE
+ if (info->cs && CS_FULL(info->cs)) {
+ R600DoneSolid(info->accel_state->dst_pix);
+ radeon_cs_flush_indirect(pScrn);
+ R600PrepareSolid(accel_state->dst_pix,
+ accel_state->rop,
+ accel_state->planemask,
+ accel_state->fg);
+ }
+#endif
+
if (accel_state->vsync)
RADEONVlineHelperSet(pScrn, x1, y1, x2, y2);
@@ -348,22 +373,6 @@ R600Solid(PixmapPtr pPix, int x1, int y1
}
static void
-R600DoneSolid(PixmapPtr pPix)
-{
- ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
- if (accel_state->vsync)
- r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix,
- accel_state->vline_crtc,
- accel_state->vline_y1,
- accel_state->vline_y2);
-
- r600_finish_op(pScrn, 8);
-}
-
-static void
R600DoPrepareCopy(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -418,6 +427,9 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
+#ifdef XF86DRM_MODE
+ tex_res.surface = accel_state->src_obj[0].surface;
+#endif
if (accel_state->src_obj[0].bpp == 8) {
tex_res.format = FMT_8;
tex_res.dst_sel_x = SQ_SEL_1; /* R */
@@ -462,6 +474,9 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
cb_conf.h = accel_state->dst_obj.height;
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.bo = accel_state->dst_obj.bo;
+#ifdef XF86DRM_MODE
+ cb_conf.surface = accel_state->dst_obj.surface;
+#endif
if (accel_state->dst_obj.bpp == 8) {
cb_conf.format = COLOR_8;
cb_conf.comp_swap = 3; /* A */
@@ -486,7 +501,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
if (accel_state->dst_obj.tiling_flags == 0)
- cb_conf.array_mode = 1;
+ cb_conf.array_mode = 0;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
@@ -576,6 +591,8 @@ R600PrepareCopy(PixmapPtr pSrc, Pixmap
dst_obj.bo = radeon_get_pixmap_bo(pDst);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
+ src_obj.surface = radeon_get_pixmap_surface(pSrc);
+ dst_obj.surface = radeon_get_pixmap_surface(pDst);
if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst))
accel_state->same_surface = TRUE;
} else
@@ -609,12 +626,12 @@ R600PrepareCopy(PixmapPtr pSrc, Pixmap
if (accel_state->same_surface == TRUE) {
#if defined(XF86DRM_MODE)
- unsigned height = RADEON_ALIGN(pDst->drawable.height,
- drmmode_get_height_align(pScrn, accel_state->dst_obj.tiling_flags));
+ unsigned long size = accel_state->dst_obj.surface->bo_size;
+ unsigned long align = accel_state->dst_obj.surface->bo_alignment;
#else
unsigned height = pDst->drawable.height;
-#endif
unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
+#endif
#if defined(XF86DRM_MODE)
if (info->cs) {
@@ -622,14 +639,14 @@ R600PrepareCopy(PixmapPtr pSrc, Pixmap
radeon_bo_unref(accel_state->copy_area_bo);
accel_state->copy_area_bo = NULL;
}
- accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
+ accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, align,
RADEON_GEM_DOMAIN_VRAM,
0);
if (accel_state->copy_area_bo == NULL)
RADEON_FALLBACK(("temp copy surface alloc failed\n"));
radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo,
- RADEON_GEM_DOMAIN_VRAM, RADEON_GEM_DOMAIN_VRAM);
+ 0, RADEON_GEM_DOMAIN_VRAM);
if (radeon_cs_space_check(info->cs)) {
radeon_bo_unref(accel_state->copy_area_bo);
accel_state->copy_area_bo = NULL;
@@ -653,10 +670,33 @@ R600PrepareCopy(PixmapPtr pSrc, Pixmap
if (accel_state->vsync)
RADEONVlineHelperClear(pScrn);
+ accel_state->dst_pix = pDst;
+ accel_state->src_pix = pSrc;
+ accel_state->xdir = xdir;
+ accel_state->ydir = ydir;
+
return TRUE;
}
static void
+R600DoneCopy(PixmapPtr pDst)
+{
+ ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+ if (!accel_state->same_surface)
+ R600DoCopyVline(pDst);
+
+ if (accel_state->copy_area) {
+ if (!info->cs)
+ exaOffscreenFree(pDst->drawable.pScreen, accel_state->copy_area);
+ accel_state->copy_area = NULL;
+ }
+
+}
+
+static void
R600Copy(PixmapPtr pDst,
int srcX, int srcY,
int dstX, int dstY,
@@ -669,6 +709,19 @@ R600Copy(PixmapPtr pDst,
if (accel_state->same_surface && (srcX == dstX) && (srcY == dstY))
return;
+#ifdef XF86DRM_MODE
+ if (info->cs && CS_FULL(info->cs)) {
+ R600DoneCopy(info->accel_state->dst_pix);
+ radeon_cs_flush_indirect(pScrn);
+ R600PrepareCopy(accel_state->src_pix,
+ accel_state->dst_pix,
+ accel_state->xdir,
+ accel_state->ydir,
+ accel_state->rop,
+ accel_state->planemask);
+ }
+#endif
+
if (accel_state->vsync)
RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
@@ -679,6 +732,7 @@ R600Copy(PixmapPtr pDst,
uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
+ int orig_rop = accel_state->rop;
#if defined(XF86DRM_MODE)
if (info->cs) {
@@ -696,6 +750,7 @@ R600Copy(PixmapPtr pDst,
accel_state->dst_obj.bo = accel_state->copy_area_bo;
accel_state->dst_obj.offset = tmp_offset;
accel_state->dst_obj.tiling_flags = 0;
+ accel_state->rop = 3;
R600DoPrepareCopy(pScrn);
R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h);
R600DoCopy(pScrn);
@@ -709,6 +764,7 @@ R600Copy(PixmapPtr pDst,
accel_state->dst_obj.bo = orig_bo;
accel_state->dst_obj.offset = orig_offset;
accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
+ accel_state->rop = orig_rop;
R600DoPrepareCopy(pScrn);
R600AppendCopyVertex(pScrn, dstX, dstY, dstX, dstY, w, h);
R600DoCopyVline(pDst);
@@ -723,24 +779,6 @@ R600Copy(PixmapPtr pDst,
}
-static void
-R600DoneCopy(PixmapPtr pDst)
-{
- ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
- if (!accel_state->same_surface)
- R600DoCopyVline(pDst);
-
- if (accel_state->copy_area) {
- if (!info->cs)
- exaOffscreenFree(pDst->drawable.pScreen, accel_state->copy_area);
- accel_state->copy_area = NULL;
- }
-
-}
-
struct blendinfo {
Bool dst_alpha;
Bool src_alpha;
@@ -943,6 +981,9 @@ static Bool R600TextureSetup(PicturePtr
tex_res.format = R600TexFormats[i].card_fmt;
tex_res.bo = accel_state->src_obj[unit].bo;
tex_res.mip_bo = accel_state->src_obj[unit].bo;
+#ifdef XF86DRM_MODE
+ tex_res.surface = accel_state->src_obj[unit].surface;
+#endif
tex_res.request_size = 1;
#if X_BYTE_ORDER == X_BIG_ENDIAN
@@ -1258,6 +1299,8 @@ static Bool R600PrepareComposite(int op,
dst_obj.bo = radeon_get_pixmap_bo(pDst);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
+ dst_obj.surface = radeon_get_pixmap_surface(pDst);
+ src_obj.surface = radeon_get_pixmap_surface(pSrc);
} else
#endif
{
@@ -1285,6 +1328,7 @@ static Bool R600PrepareComposite(int op,
mask_obj.offset = 0;
mask_obj.bo = radeon_get_pixmap_bo(pMask);
mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
+ mask_obj.surface = radeon_get_pixmap_surface(pMask);
} else
#endif
{
@@ -1396,6 +1440,9 @@ static Bool R600PrepareComposite(int op,
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.format = dst_format;
cb_conf.bo = accel_state->dst_obj.bo;
+#ifdef XF86DRM_MODE
+ cb_conf.surface = accel_state->dst_obj.surface;
+#endif
switch (pDstPicture->format) {
case PICT_a8r8g8b8:
@@ -1429,7 +1476,7 @@ static Bool R600PrepareComposite(int op,
cb_conf.pmask = 0xf;
cb_conf.rop = 3;
if (accel_state->dst_obj.tiling_flags == 0)
- cb_conf.array_mode = 1;
+ cb_conf.array_mode = 0;
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (dst_obj.bpp) {
case 16:
@@ -1452,9 +1499,34 @@ static Bool R600PrepareComposite(int op,
if (accel_state->vsync)
RADEONVlineHelperClear(pScrn);
+ accel_state->composite_op = op;
+ accel_state->dst_pic = pDstPicture;
+ accel_state->src_pic = pSrcPicture;
+ accel_state->dst_pix = pDst;
+ accel_state->msk_pix = pMask;
+ accel_state->src_pix = pSrc;
+
return TRUE;
}
+static void R600DoneComposite(PixmapPtr pDst)
+{
+ ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+ int vtx_size;
+
+ if (accel_state->vsync)
+ r600_cp_wait_vline_sync(pScrn, accel_state->ib, pDst,
+ accel_state->vline_crtc,
+ accel_state->vline_y1,
+ accel_state->vline_y2);
+
+ vtx_size = accel_state->msk_pic ? 24 : 16;
+
+ r600_finish_op(pScrn, vtx_size);
+}
+
static void R600Composite(PixmapPtr pDst,
int srcX, int srcY,
int maskX, int maskY,
@@ -1469,6 +1541,20 @@ static void R600Composite(PixmapPtr pDst
/* ErrorF("R600Composite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
+#ifdef XF86DRM_MODE
+ if (info->cs && CS_FULL(info->cs)) {
+ R600DoneComposite(info->accel_state->dst_pix);
+ radeon_cs_flush_indirect(pScrn);
+ R600PrepareComposite(info->accel_state->composite_op,
+ info->accel_state->src_pic,
+ info->accel_state->msk_pic,
+ info->accel_state->dst_pic,
+ info->accel_state->src_pix,
+ info->accel_state->msk_pix,
+ info->accel_state->dst_pix);
+ }
+#endif
+
if (accel_state->vsync)
RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
@@ -1524,24 +1610,6 @@ static void R600Composite(PixmapPtr pDst
}
-static void R600DoneComposite(PixmapPtr pDst)
-{
- ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
- int vtx_size;
-
- if (accel_state->vsync)
- r600_cp_wait_vline_sync(pScrn, accel_state->ib, pDst,
- accel_state->vline_crtc,
- accel_state->vline_y1,
- accel_state->vline_y2);
-
- vtx_size = accel_state->msk_pic ? 24 : 16;
-
- r600_finish_op(pScrn, vtx_size);
-}
-
Bool
R600CopyToVRAM(ScrnInfoPtr pScrn,
char *src, int src_pitch,
@@ -1811,6 +1879,9 @@ R600UploadToScreenCS(PixmapPtr pDst, int
src_obj.domain = RADEON_GEM_DOMAIN_GTT;
src_obj.bo = scratch;
src_obj.tiling_flags = 0;
+#ifdef XF86DRM_MODE
+ src_obj.surface = NULL;
+#endif
dst_obj.pitch = dst_pitch_hw;
dst_obj.width = pDst->drawable.width;
@@ -1820,6 +1891,9 @@ R600UploadToScreenCS(PixmapPtr pDst, int
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
dst_obj.bo = radeon_get_pixmap_bo(pDst);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
+#ifdef XF86DRM_MODE
+ dst_obj.surface = radeon_get_pixmap_surface(pDst);
+#endif
if (!R600SetAccelState(pScrn,
&src_obj,
@@ -1946,6 +2020,9 @@ R600DownloadFromScreenCS(PixmapPtr pSrc,
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
+#ifdef XF86DRM_MODE
+ src_obj.surface = radeon_get_pixmap_surface(pSrc);
+#endif
dst_obj.pitch = scratch_pitch;
dst_obj.width = w;
@@ -1955,6 +2032,9 @@ R600DownloadFromScreenCS(PixmapPtr pSrc,
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
dst_obj.tiling_flags = 0;
+#ifdef XF86DRM_MODE
+ dst_obj.surface = NULL;
+#endif
if (!R600SetAccelState(pScrn,
&src_obj,
Index: xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c
diff -u xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c:1.5 xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c:1.6
--- xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c:1.5 Sun Mar 20 07:08:58 2011
+++ xsrc/external/mit/xf86-video-ati/dist/src/r6xx_accel.c Sun Jun 3 16:42:23 2012
@@ -223,12 +223,37 @@ void
r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain)
{
uint32_t cb_color_info, cb_color_control;
- int pitch, slice, h;
+ unsigned pitch, slice, h, array_mode;
RADEONInfoPtr info = RADEONPTR(pScrn);
+
+#if defined(XF86DRM_MODE)
+ if (cb_conf->surface) {
+ switch (cb_conf->surface->level[0].mode) {
+ case RADEON_SURF_MODE_1D:
+ array_mode = 2;
+ break;
+ case RADEON_SURF_MODE_2D:
+ array_mode = 4;
+ break;
+ default:
+ array_mode = 0;
+ break;
+ }
+ pitch = (cb_conf->surface->level[0].nblk_x >> 3) - 1;
+ slice = ((cb_conf->surface->level[0].nblk_x * cb_conf->surface->level[0].nblk_y) / 64) - 1;
+ } else
+#endif
+ {
+ array_mode = cb_conf->array_mode;
+ pitch = (cb_conf->w / 8) - 1;
+ h = RADEON_ALIGN(cb_conf->h, 8);
+ slice = ((cb_conf->w * h) / 64) - 1;
+ }
+
cb_color_info = ((cb_conf->endian << ENDIAN_shift) |
(cb_conf->format << CB_COLOR0_INFO__FORMAT_shift) |
- (cb_conf->array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) |
+ (array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) |
(cb_conf->number_type << NUMBER_TYPE_shift) |
(cb_conf->comp_swap << COMP_SWAP_shift) |
(cb_conf->tile_mode << CB_COLOR0_INFO__TILE_MODE_shift));
@@ -251,10 +276,6 @@ r600_set_render_target(ScrnInfoPtr pScrn
if (cb_conf->source_format)
cb_color_info |= SOURCE_FORMAT_bit;
- pitch = (cb_conf->w / 8) - 1;
- h = RADEON_ALIGN(cb_conf->h, 8);
- slice = ((cb_conf->w * h) / 64) - 1;
-
BEGIN_BATCH(3 + 2);
EREG(ib, (CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8));
RELOC_BATCH(cb_conf->bo, 0, domain);
@@ -345,9 +366,6 @@ r600_cp_wait_vline_sync(ScrnInfoPtr pScr
if (!crtc)
return;
- if (stop < start)
- return;
-
if (!crtc->enabled)
return;
@@ -367,10 +385,10 @@ r600_cp_wait_vline_sync(ScrnInfoPtr pScr
return;
}
- start = max(start, 0);
- stop = min(stop, crtc->mode.VDisplay);
+ start = max(start, crtc->y);
+ stop = min(stop, crtc->y + crtc->mode.VDisplay);
- if (start > crtc->mode.VDisplay)
+ if (start >= stop)
return;
#if defined(XF86DRM_MODE)
@@ -605,12 +623,34 @@ r600_set_tex_resource(ScrnInfoPtr pScrn,
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
uint32_t sq_tex_resource_word5, sq_tex_resource_word6;
+ uint32_t array_mode, pitch;
+
+#if defined(XF86DRM_MODE)
+ if (tex_res->surface) {
+ switch (tex_res->surface->level[0].mode) {
+ case RADEON_SURF_MODE_1D:
+ array_mode = 2;
+ break;
+ case RADEON_SURF_MODE_2D:
+ array_mode = 4;
+ break;
+ default:
+ array_mode = 0;
+ break;
+ }
+ pitch = tex_res->surface->level[0].nblk_x >> 3;
+ } else
+#endif
+ {
+ array_mode = tex_res->tile_mode;
+ pitch = (tex_res->pitch + 7) >> 3;
+ }
sq_tex_resource_word0 = ((tex_res->dim << DIM_shift) |
- (tex_res->tile_mode << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift));
+ (array_mode << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift));
if (tex_res->w)
- sq_tex_resource_word0 |= (((((tex_res->pitch + 7) >> 3) - 1) << PITCH_shift) |
+ sq_tex_resource_word0 |= (((pitch - 1) << PITCH_shift) |
((tex_res->w - 1) << TEX_WIDTH_shift));
if (tex_res->tile_type)
@@ -1121,7 +1161,7 @@ r600_set_default_state(ScrnInfoPtr pScrn
r600_fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
// VGT
- BEGIN_BATCH(43);
+ BEGIN_BATCH(46);
PACK0(ib, VGT_MAX_VTX_INDX, 4);
E32(ib, 0xffffff); // VGT_MAX_VTX_INDX
E32(ib, 0); // VGT_MIN_VTX_INDX
@@ -1160,6 +1200,7 @@ r600_set_default_state(ScrnInfoPtr pScrn
E32(ib, 0); // VGT_VTX_CNT_EN
EREG(ib, VGT_STRMOUT_BUFFER_EN, 0);
+ EREG(ib, SX_MISC, 0);
END_BATCH();
}
Index: xsrc/external/mit/xf86-video-ati/dist/src/radeon_dri.c
diff -u xsrc/external/mit/xf86-video-ati/dist/src/radeon_dri.c:1.7 xsrc/external/mit/xf86-video-ati/dist/src/radeon_dri.c:1.8
--- xsrc/external/mit/xf86-video-ati/dist/src/radeon_dri.c:1.7 Sat Jul 17 06:34:13 2010
+++ xsrc/external/mit/xf86-video-ati/dist/src/radeon_dri.c Sun Jun 3 16:42:23 2012
@@ -56,7 +56,6 @@
/* X and server generic header files */
#include "xf86.h"
-#include "xf86PciInfo.h"
#include "windowstr.h"
/* GLX/DRI/DRM definitions */
@@ -1451,8 +1450,26 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pSc
}
/* We don't, bummer ! */
- if (info->dri->pKernelDRMVersion->version_major != req_major ||
- info->dri->pKernelDRMVersion->version_minor < req_minor ||
+ if (info->dri->pKernelDRMVersion->version_major != req_major) {
+ /* Looks like we're trying to start in UMS mode on a KMS kernel.
+ * This can happen if the radeon kernel module wasn't loaded before
+ * X starts.
+ */
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "[dri] RADEONDRIGetVersion failed because of a version mismatch.\n"
+ "[dri] This chipset requires a kernel module version of %d.%d.%d,\n"
+ "[dri] but the kernel reports a version of %d.%d.%d."
+ "[dri] Make sure your module is loaded prior to starting X, and\n"
+ "[dri] that this driver was built with support for KMS.\n"
+ "[dri] Aborting.\n",
+ req_major, req_minor, req_patch,
+ info->dri->pKernelDRMVersion->version_major,
+ info->dri->pKernelDRMVersion->version_minor,
+ info->dri->pKernelDRMVersion->version_patchlevel);
+ drmFreeVersion(info->dri->pKernelDRMVersion);
+ info->dri->pKernelDRMVersion = NULL;
+ return -1;
+ } else if (info->dri->pKernelDRMVersion->version_minor < req_minor ||
(info->dri->pKernelDRMVersion->version_minor == req_minor &&
info->dri->pKernelDRMVersion->version_patchlevel < req_patch)) {
/* Incompatible drm version */
@@ -1460,10 +1477,7 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pSc
"[dri] RADEONDRIGetVersion failed because of a version mismatch.\n"
"[dri] This chipset requires a kernel module version of %d.%d.%d,\n"
"[dri] but the kernel reports a version of %d.%d.%d."
- "[dri] If using legacy modesetting, upgrade your kernel.\n"
- "[dri] If using kernel modesetting, make sure your module is\n"
- "[dri] loaded prior to starting X, and that this driver was built\n"
- "[dri] with support for KMS.\n"
+ "[dri] Try upgrading your kernel.\n"
"[dri] Disabling DRI.\n",
req_major, req_minor, req_patch,
info->dri->pKernelDRMVersion->version_major,
@@ -1566,7 +1580,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScre
pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4;
pDRIInfo->ddxDriverMinorVersion = 3;
pDRIInfo->ddxDriverPatchVersion = 0;
- pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->dri->frontOffset;
+ pDRIInfo->frameBufferPhysicalAddress = (void *)(uintptr_t)info->LinearAddr + info->dri->frontOffset;
pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize;
pDRIInfo->frameBufferStride = (pScrn->displayWidth *
info->CurrentLayout.pixel_bytes);
Index: xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c
diff -u xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c:1.7 xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c:1.8
--- xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c:1.7 Sat Jul 23 08:19:19 2011
+++ xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa_funcs.c Sun Jun 3 16:42:23 2012
@@ -27,7 +27,7 @@
* Eric Anholt <[email protected]>
* Zack Rusin <[email protected]>
* Benjamin Herrenschmidt <[email protected]>
- * Michel Dänzer <[email protected]>
+ * Michel Dänzer <[email protected]>
*
*/
@@ -132,14 +132,13 @@ static void FUNC_NAME(Emit2DState)(ScrnI
}
static void
-FUNC_NAME(RADEONDone2D)(PixmapPtr pPix)
+FUNC_NAME(RADEONFlush2D)(PixmapPtr pPix)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
ACCEL_PREAMBLE();
TRACE;
- info->state_2d.op = 0;
BEGIN_ACCEL(2);
OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
OUT_ACCEL_REG(RADEON_WAIT_UNTIL,
@@ -147,6 +146,15 @@ FUNC_NAME(RADEONDone2D)(PixmapPtr pPix)
FINISH_ACCEL();
}
+static void
+FUNC_NAME(RADEONDone2D)(PixmapPtr pPix)
+{
+ RINFO_FROM_SCREEN(pPix->drawable.pScreen);
+ info->state_2d.op = 0;
+
+ FUNC_NAME(RADEONFlush2D)(pPix);
+}
+
static Bool
FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
{
@@ -220,7 +228,7 @@ FUNC_NAME(RADEONSolid)(PixmapPtr pPix, i
#if defined(ACCEL_CP) && defined(XF86DRM_MODE)
if (info->cs && CS_FULL(info->cs)) {
- FUNC_NAME(RADEONDone2D)(info->accel_state->dst_pix);
+ FUNC_NAME(RADEONFlush2D)(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
}
#endif
@@ -332,7 +340,7 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst,
#if defined(ACCEL_CP) && defined(XF86DRM_MODE)
if (info->cs && CS_FULL(info->cs)) {
- FUNC_NAME(RADEONDone2D)(info->accel_state->dst_pix);
+ FUNC_NAME(RADEONFlush2D)(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
}
#endif
Index: xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c
diff -u xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c:1.10 xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c:1.11
--- xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c:1.10 Wed Aug 24 22:40:56 2011
+++ xsrc/external/mit/xf86-video-ati/dist/src/radeon_driver.c Sun Jun 3 16:42:23 2012
@@ -1475,7 +1475,9 @@ static void RADEONInitMemoryMap(ScrnInfo
(info->ChipFamily != CHIP_FAMILY_RS740) &&
(info->ChipFamily != CHIP_FAMILY_RS780) &&
(info->ChipFamily != CHIP_FAMILY_RS880) &&
- (info->ChipFamily != CHIP_FAMILY_PALM)) {
+ (info->ChipFamily != CHIP_FAMILY_PALM) &&
+ (info->ChipFamily != CHIP_FAMILY_SUMO) &&
+ (info->ChipFamily != CHIP_FAMILY_SUMO2)) {
if (info->IsIGP)
info->mc_fb_location = INREG(RADEON_NB_TOM);
else
@@ -1894,7 +1896,7 @@ static Bool RADEONPreInitChipType(ScrnIn
}
}
- if (IS_DCE5_VARIANT) {
+ if (info->ChipFamily >= CHIP_FAMILY_SUMO) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Chipset: \"%s\" (ChipID = 0x%04x) requires KMS\n",
pScrn->chipset,
@@ -2334,6 +2336,7 @@ static Bool RADEONPreInitInt10(ScrnInfoP
static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
+ Bool ret;
MessageType from;
char *reason;
@@ -2400,8 +2403,9 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr
info->dri->pLibDRMVersion = NULL;
info->dri->pKernelDRMVersion = NULL;
- if (!RADEONDRIGetVersion(pScrn))
- return FALSE;
+ ret = RADEONDRIGetVersion(pScrn);
+ if (ret <= 0)
+ return ret;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[dri] Found DRI library version %d.%d.%d and kernel"
@@ -3019,9 +3023,11 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, in
}
info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
+#ifndef XSERVER_LIBPCIACCESS
info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo),
PCI_DEV_DEV(info->PciInfo),
PCI_DEV_FUNC(info->PciInfo));
+#endif
info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL;
info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TOTO SAYS %016llx\n",
@@ -3125,8 +3131,10 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, in
} else
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE,"
" VGA module load skipped\n");
- if (info->VGAAccess)
+ if (info->VGAAccess) {
+ vgaHWSetStdFuncs(VGAHWPTR(pScrn));
vgaHWGetIOBase(VGAHWPTR(pScrn));
+ }
#endif
@@ -3164,6 +3172,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, in
* memory map
*/
info->directRenderingEnabled = RADEONPreInitDRI(pScrn);
+ if (info->directRenderingEnabled < 0)
+ goto fail;
#endif
if (!info->directRenderingEnabled) {
if (info->ChipFamily >= CHIP_FAMILY_R600) {
@@ -4468,22 +4478,17 @@ static void RADEONSaveMemMapRegisters(Sc
}
/* Read palette data */
-static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save)
+static void RADEONSavePalette(ScrnInfoPtr pScrn, int palID, RADEONSavePtr save)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
int i;
- PAL_SELECT(1);
+ PAL_SELECT(palID);
INPAL_START(0);
- for (i = 0; i < 256; i++) {
- save->palette2[i] = INREG(RADEON_PALETTE_30_DATA);
- }
- PAL_SELECT(0);
- INPAL_START(0);
for (i = 0; i < 256; i++) {
- save->palette[i] = INREG(RADEON_PALETTE_30_DATA);
+ save->palette[palID][i] = INREG(RADEON_PALETTE_30_DATA);
}
}
@@ -4493,16 +4498,21 @@ static void RADEONRestorePalette(ScrnInf
unsigned char *RADEONMMIO = info->MMIO;
int i;
- PAL_SELECT(1);
- OUTPAL_START(0);
- for (i = 0; i < 256; i++) {
- OUTREG(RADEON_PALETTE_30_DATA, restore->palette2[i]);
+ if (restore->palette_saved[1]) {
+ ErrorF("Restore Palette 2\n");
+ PAL_SELECT(1);
+ OUTPAL_START(0);
+ for (i = 0; i < 256; i++) {
+ OUTREG(RADEON_PALETTE_30_DATA, restore->palette[1][i]);
+ }
}
-
- PAL_SELECT(0);
- OUTPAL_START(0);
- for (i = 0; i < 256; i++) {
- OUTREG(RADEON_PALETTE_30_DATA, restore->palette[i]);
+ if (restore->palette_saved[0]) {
+ ErrorF("Restore Palette 1\n");
+ PAL_SELECT(0);
+ OUTPAL_START(0);
+ for (i = 0; i < 256; i++) {
+ OUTREG(RADEON_PALETTE_30_DATA, restore->palette[0][i]);
+ }
}
}
@@ -5728,6 +5738,20 @@ RADEONSaveBIOSRegisters(ScrnInfoPtr pScr
}
}
+void radeon_save_palette_on_demand(ScrnInfoPtr pScrn, int palID)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONSavePtr save = info->SavedReg;
+
+ if (save->palette_saved[palID] == TRUE)
+ return;
+
+ if (!IS_AVIVO_VARIANT)
+ RADEONSavePalette(pScrn, palID, save);
+
+ save->palette_saved[palID] = TRUE;
+}
+
/* Save everything needed to restore the original VC state */
static void RADEONSave(ScrnInfoPtr pScrn)
{
@@ -5751,12 +5775,9 @@ static void RADEONSave(ScrnInfoPtr pScrn
* setup in the card at all !!
*/
vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */
-# elif defined(__linux__)
+# else
/* Save only mode * & fonts */
vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
-# else
- /* Save mode * & fonts & cmap */
- vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL);
# endif
vgaHWLock(hwp);
}
@@ -5781,7 +5802,7 @@ static void RADEONSave(ScrnInfoPtr pScrn
RADEONSaveCrtcRegisters(pScrn, save);
RADEONSaveFPRegisters(pScrn, save);
RADEONSaveDACRegisters(pScrn, save);
- RADEONSavePalette(pScrn, save);
+ /* Palette saving is done on demand now */
if (pRADEONEnt->HasCRTC2) {
RADEONSaveCrtc2Registers(pScrn, save);
@@ -5835,6 +5856,7 @@ static void RADEONRestore(ScrnInfoPtr pS
RADEONRestoreMemMapRegisters(pScrn, restore);
RADEONRestoreCommonRegisters(pScrn, restore);
+ RADEONRestorePalette(pScrn, restore);
if (pRADEONEnt->HasCRTC2) {
RADEONRestoreCrtc2Registers(pScrn, restore);
RADEONRestorePLL2Registers(pScrn, restore);
@@ -5874,12 +5896,12 @@ static void RADEONRestore(ScrnInfoPtr pS
if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) {
if (info->crtc2_on && xf86_config->num_crtc > 1) {
crtc = xf86_config->crtc[1];
- crtc->funcs->dpms(crtc, DPMSModeOn);
+ radeon_do_crtc_dpms(crtc, DPMSModeOn);
}
}
if (info->crtc_on) {
crtc = xf86_config->crtc[0];
- crtc->funcs->dpms(crtc, DPMSModeOn);
+ radeon_do_crtc_dpms(crtc, DPMSModeOn);
}
#ifdef WITH_VGAHW
@@ -5891,10 +5913,8 @@ static void RADEONRestore(ScrnInfoPtr pS
* write VGA fonts, will find a better solution in the future
*/
vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE );
-# elif defined(__linux__)
- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
# else
- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL );
+ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
# endif
vgaHWLock(hwp);
}
@@ -5908,7 +5928,6 @@ static void RADEONRestore(ScrnInfoPtr pS
else if (IS_AVIVO_VARIANT)
avivo_restore_vga_regs(pScrn, restore);
else {
- RADEONRestorePalette(pScrn, restore);
RADEONRestoreDACRegisters(pScrn, restore);
}
#if 0
Index: xsrc/external/mit/xf86-video-ati/dist/src/radeon_textured_video.c
diff -u xsrc/external/mit/xf86-video-ati/dist/src/radeon_textured_video.c:1.2 xsrc/external/mit/xf86-video-ati/dist/src/radeon_textured_video.c:1.3
--- xsrc/external/mit/xf86-video-ati/dist/src/radeon_textured_video.c:1.2 Sun Mar 20 10:40:24 2011
+++ xsrc/external/mit/xf86-video-ati/dist/src/radeon_textured_video.c Sun Jun 3 16:42:23 2012
@@ -66,6 +66,9 @@ R600CopyToVRAM(ScrnInfoPtr pScrn,
#define IMAGE_MAX_WIDTH_R600 8192
#define IMAGE_MAX_HEIGHT_R600 8192
+#define IMAGE_MAX_WIDTH_EG 16384
+#define IMAGE_MAX_HEIGHT_EG 16384
+
static Bool
RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix)
{
@@ -383,7 +386,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn
/* copy data */
top = (y1 >> 16) & ~1;
- nlines = RADEON_ALIGN((y2 + 0xffff) >> 16, 2) - top;
+ nlines = ((y2 + 0xffff) >> 16) - top;
pPriv->src_offset = pPriv->video_offset;
if (info->cs) {
@@ -554,6 +557,16 @@ static XF86VideoEncodingRec DummyEncodin
}
};
+static XF86VideoEncodingRec DummyEncodingEG[1] =
+{
+ {
+ 0,
+ "XV_IMAGE",
+ IMAGE_MAX_WIDTH_EG, IMAGE_MAX_HEIGHT_EG,
+ {1, 1}
+ }
+};
+
#define NUM_FORMATS 3
static XF86VideoFormatRec Formats[NUM_FORMATS] =
@@ -824,7 +837,9 @@ RADEONSetupImageTexturedVideo(ScreenPtr
adapt->flags = 0;
adapt->name = "Radeon Textured Video";
adapt->nEncodings = 1;
- if (IS_R600_3D)
+ if (IS_EVERGREEN_3D)
+ adapt->pEncodings = DummyEncodingEG;
+ else if (IS_R600_3D)
adapt->pEncodings = DummyEncodingR600;
else if (IS_R500_3D)
adapt->pEncodings = DummyEncodingR500;
