Module Name: src
Committed By: matt
Date: Fri Aug 24 06:34:08 UTC 2012
Modified Files:
src/sys/arch/arm/omap: omap2_reg.h
Log Message:
Add registers for OMAP 3530 / TI DM37xx to determine CPU speed.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/omap/omap2_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/omap/omap2_reg.h
diff -u src/sys/arch/arm/omap/omap2_reg.h:1.8 src/sys/arch/arm/omap/omap2_reg.h:1.9
--- src/sys/arch/arm/omap/omap2_reg.h:1.8 Thu Aug 23 01:27:24 2012
+++ src/sys/arch/arm/omap/omap2_reg.h Fri Aug 24 06:34:08 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_reg.h,v 1.8 2012/08/23 01:27:24 matt Exp $ */
+/* $NetBSD: omap2_reg.h,v 1.9 2012/08/24 06:34:08 matt Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -108,7 +108,7 @@
#define OMAP2_CM_BASE 0x48008000
#endif
#ifdef OMAP_3530
-#define OMAP2_CM_BASE 0x48004000
+#define OMAP2_CM_BASE (OMAP3530_L4_CORE_BASE + 0x04000)
#endif
#ifdef OMAP_4430
#define OMAP2_CM_BASE (OMAP4430_L4_CORE_BASE + 0x04000)
@@ -117,7 +117,7 @@
#define OMAP2_CM_BASE TI_AM335X_L4_WAKEUP_BASE
#endif
#ifdef TI_DM37XX
-#define OMAP2_CM_BASE TI_DM37XX_L4_WAKEUP_BASE
+#define OMAP2_CM_BASE 0x48004000
#endif
#define OMAP2_CM_CLKSEL_MPU 0x140
@@ -128,7 +128,6 @@
#define OMAP2_CM_CLKSEL2_CORE 0x244
#define OMAP2_CM_SIZE (OMAP2_CM_CLKSEL2_CORE + 4)
-
/*
* bit defines for OMAP2_CM_CLKSEL_MPU
*/
@@ -280,6 +279,15 @@
|OMAP2_CM_CLKSEL2_CORE_RESb)
+#define OMAP3_CM_CLKSEL1_PLL_MPU 0x940
+#define OMAP3_CM_CLKSEL2_PLL_MPU 0x944
+
+#define OMAP3_CM_CLKSEL1_PLL_MPU_CLK_SRC __BITS(21,9)
+#define OMAP3_CM_CLKSEL1_PLL_MPU_DPLL_MULT __BITS(18,8)
+#define OMAP3_CM_CLKSEL1_PLL_MPU_DPLL_DIV __BITS(6,0)
+
+#define OMAP3_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV __BITS(4,0)
+
/*
* Power Management registers base, offsets, and size
*/
@@ -334,6 +342,17 @@
#define OMAP_RST_DPLL3 __BIT(2)
#define OMAP_RST_GS __BIT(1)
+#define OMAP3_PRM_CLKSEL 0x40 // from PLL_MOD
+#define OMAP3_PRM_CLKSEL_CLKIN __BITS(2,0)
+#define OMAP3_PRM_CLKSEL_CLKIN_12000KHZ 0
+#define OMAP3_PRM_CLKSEL_CLKIN_13000KHZ 1
+#define OMAP3_PRM_CLKSEL_CLKIN_19200KHZ 2
+#define OMAP3_PRM_CLKSEL_CLKIN_26000KHZ 3
+#define OMAP3_PRM_CLKSEL_CLKIN_38400KHZ 4
+#define OMAP3_PRM_CLKSEL_CLKIN_16800KHZ 5
+#define OMAP3_PRM_CLKSEL_FREQS { 12000, 13000, 19200, 26000, 38400, 16800, 0, 0 }
+#define OMAP3_PRM_CLKSEL_MULT 1000
+
/*
* L3 Interconnect Target Agent Common Registers
*/
