Module Name: src
Committed By: matt
Date: Sat Sep 1 00:07:32 UTC 2012
Modified Files:
src/sys/arch/arm/imx: imx51_ccm.c imx51_ccmreg.h
Added Files:
src/sys/arch/arm/imx: files.imx6 imx6_intr.h imx6_reg.h
Log Message:
Some initial iMX.6 support
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/imx/files.imx6 \
src/sys/arch/arm/imx/imx6_intr.h src/sys/arch/arm/imx/imx6_reg.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/imx/imx51_ccm.c \
src/sys/arch/arm/imx/imx51_ccmreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/imx/imx51_ccm.c
diff -u src/sys/arch/arm/imx/imx51_ccm.c:1.1 src/sys/arch/arm/imx/imx51_ccm.c:1.2
--- src/sys/arch/arm/imx/imx51_ccm.c:1.1 Tue Apr 17 09:33:31 2012
+++ src/sys/arch/arm/imx/imx51_ccm.c Sat Sep 1 00:07:32 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/* $NetBSD: imx51_ccm.c,v 1.2 2012/09/01 00:07:32 matt Exp $ */
/*
* Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.2 2012/09/01 00:07:32 matt Exp $");
#include <sys/types.h>
#include <sys/time.h>
@@ -82,6 +82,9 @@ imxccm_match(device_t parent, cfdata_t c
{
struct axi_attach_args *aa = aux;
+ if (ccm_softc != NULL)
+ return 0;
+
if (aa->aa_addr == CCMC_BASE)
return 1;
@@ -91,24 +94,23 @@ imxccm_match(device_t parent, cfdata_t c
static void
imxccm_attach(device_t parent, device_t self, void *aux)
{
+ struct imxccm_softc * const sc = device_private(self);
struct axi_attach_args *aa = aux;
bus_space_tag_t iot = aa->aa_iot;
- int i;
- ccm_softc = device_private(self);
- ccm_softc->sc_dev = self;
- ccm_softc->sc_iot = iot;
-
- if (bus_space_map(iot, aa->aa_addr, CCMC_SIZE, 0,
- &ccm_softc->sc_ioh)) {
- aprint_error(": can't map\n");
+ ccm_softc = sc;
+ sc->sc_dev = self;
+ sc->sc_iot = iot;
+
+ if (bus_space_map(iot, aa->aa_addr, CCMC_SIZE, 0, &sc->sc_ioh)) {
+ aprint_error(": can't map registers\n");
return;
}
- for (i=1; i <= IMX51_N_DPLLS; ++i) {
+ for (u_int i=1; i <= IMX51_N_DPLLS; ++i) {
if (bus_space_map(iot, DPLL_BASE(i), DPLL_SIZE, 0,
- &ccm_softc->sc_pll[i-1].pll_ioh)) {
- aprint_error(": can't map\n");
+ &sc->sc_pll[i-1].pll_ioh)) {
+ aprint_error(": can't map pll registers\n");
return;
}
}
@@ -153,7 +155,7 @@ imx51_get_clock(enum imx51_clock clk)
case IMX51CLK_PLL1:
case IMX51CLK_PLL2:
case IMX51CLK_PLL3:
- return ccm_softc->sc_pll[clk-IMX51CLK_PLL1].pll_freq;
+ return ccm_softc->sc_pll[clk - IMX51CLK_PLL1].pll_freq;
case IMX51CLK_PLL1SW:
ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0)
@@ -162,19 +164,17 @@ imx51_get_clock(enum imx51_clock clk)
/* FALLTHROUGH */
case IMX51CLK_PLL1STEP:
ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
- switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) {
+ switch (__SHIFTOUT(ccsr, CCSR_STEP_SEL)) {
case 0:
return imx51_get_clock(IMX51CLK_LP_APM);
case 1:
return 0; /* XXX PLL bypass clock */
case 2:
return ccm_softc->sc_pll[2-1].pll_freq /
- (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >>
- CCSR_PLL2_DIV_PODF_SHIFT));
+ (1 + __SHIFTOUT(ccsr, CCSR_PLL2_DIV_PODF));
case 3:
return ccm_softc->sc_pll[3-1].pll_freq /
- (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >>
- CCSR_PLL3_DIV_PODF_SHIFT));
+ (1 + __SHIFTOUT(ccsr & CCSR_PLL3_DIV_PODF))
}
/*NOTREACHED*/
case IMX51CLK_PLL2SW:
@@ -206,8 +206,7 @@ imx51_get_clock(enum imx51_clock clk)
else {
freq = 0;
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
- switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >>
- CBCMR_PERIPH_APM_SEL_SHIFT) {
+ switch (__SHIFTOUT(cbcmr, CBCMR_PERIPH_APM_SEL)) {
case 0:
freq = imx51_get_clock(IMX51CLK_PLL1SW);
break;
@@ -226,18 +225,15 @@ imx51_get_clock(enum imx51_clock clk)
case IMX51CLK_MAIN_BUS_CLK:
freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
cdcr = bus_space_read_4(iot, ioh, CCMC_CDCR);
- return freq / (cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >>
- CDCR_PERIPH_CLK_DVFS_PODF_SHIFT;
+ return freq / __SHIFTOUT(cdcr, CDCR_PERIPH_CLK_DVFS_PODF);
case IMX51CLK_AHB_CLK_ROOT:
freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK);
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
- return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >>
- CBCDR_AHB_PODF_SHIFT));
+ return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_AHB_PODF));
case IMX51CLK_IPG_CLK_ROOT:
freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
- return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >>
- CBCDR_IPG_PODF_SHIFT));
+ return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_IPG_PODF));
case IMX51CLK_PERCLK_ROOT:
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
@@ -253,12 +249,9 @@ imx51_get_clock(enum imx51_clock clk)
printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr);
#endif
- freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >>
- CBCDR_PERCLK_PRED1_SHIFT);
- freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >>
- CBCDR_PERCLK_PRED2_SHIFT);
- freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >>
- CBCDR_PERCLK_PODF_SHIFT);
+ freq /= 1 + __SHIFTOUT(cbcdr & CBCDR_PERCLK_PRED1);
+ freq /= 1 + __SHIFTOUT(cbcdr & CBCDR_PERCLK_PRED2);
+ freq /= 1 + __SHIFTOUT(cbcdr & CBCDR_PERCLK_PODF);
return freq;
case IMX51CLK_UART_CLK_ROOT:
cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1);
@@ -268,8 +261,7 @@ imx51_get_clock(enum imx51_clock clk)
printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1);
#endif
- sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >>
- CSCMR1_UART_CLK_SEL_SHIFT;
+ sel = __SHIFTOUT(cscmr1 & CSCMR1_UART_CLK_SEL);
freq = 0; /* shut up GCC */
switch (sel) {
@@ -283,15 +275,12 @@ imx51_get_clock(enum imx51_clock clk)
break;
}
- return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >>
- CSCDR1_UART_CLK_PRED_SHIFT)) /
- (1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >>
- CSCDR1_UART_CLK_PODF_SHIFT));
+ return freq / (1 + __SHIFTOUT(cscdr1. CSCDR1_UART_CLK_PRED));
+ / (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PODF));
case IMX51CLK_IPU_HSP_CLK_ROOT:
freq = 0;
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
- switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >>
- CBCMR_IPU_HSP_CLK_SEL_SHIFT) {
+ switch (__SHIFTOUT(cbcmr, CBCMR_IPU_HSP_CLK_SEL)) {
case 0:
freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK);
break;
@@ -347,7 +336,7 @@ imx51_get_pll_freq(u_int pll_no)
}
pdf = dp_op & DP_OP_PDF_MASK;
- mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT);
+ mfi = max(5, __SHIFTOUT(dp_op, DP_OP_MFI));
mfd = dp_mfd;
if (dp_mfn & __BIT(26))
/* 27bit signed value */
Index: src/sys/arch/arm/imx/imx51_ccmreg.h
diff -u src/sys/arch/arm/imx/imx51_ccmreg.h:1.1 src/sys/arch/arm/imx/imx51_ccmreg.h:1.2
--- src/sys/arch/arm/imx/imx51_ccmreg.h:1.1 Tue Apr 17 09:33:31 2012
+++ src/sys/arch/arm/imx/imx51_ccmreg.h Sat Sep 1 00:07:32 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_ccmreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/* $NetBSD: imx51_ccmreg.h,v 1.2 2012/09/01 00:07:32 matt Exp $ */
/*
* Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -32,8 +32,10 @@
/* register offset address */
#define CCMC_BASE 0x73fd4000
+#define CCMC_IMX6_BASE 0x020c4040
#define CCMC_CCR 0x0000
#define CCR_FPM_MULT __BIT(12)
+#define CCR_COSC_EN __BIT(12)
#define CCMC_CCDR 0x0004
#define CCMC_CSR 0x0008
#define CCMC_CCSR 0x000c
@@ -52,6 +54,7 @@
#define CBCDR_DDR_HIGH_FREQ_CLK_SEL __BIT(30)
#define CBCDR_DDR_CLK_PODF_SHIFT 27
#define CBCDR_DDR_CLK_PODF_MASK __BITS(29, CBCDR_DDR_CLK_PODF_SHIFT)
+#define CDCDR_PERIPH_CLK2 __BITS(29, 27)
#define CBCDR_EMI_CLK_SEL __BIT(26)
#define CBCDR_PERIPH_CLK_SEL __BIT(25)
#define CBCDR_EMI_SLOW_PODF_SHIFT 22
@@ -91,6 +94,7 @@
#define CCMC_CS1CDR 0x0028
#define CCMC_CS2CDR 0x002c
#define CCMC_CDCDR 0x0030
+#define CCMC_CHSCCDR 0x0034 // i.MX6
#define CCMC_CSCDR2 0x0038
#define CCMC_CSCDR3 0x003c
#define CCMC_CSCDR4 0x0040
Added files:
Index: src/sys/arch/arm/imx/files.imx6
diff -u /dev/null src/sys/arch/arm/imx/files.imx6:1.1
--- /dev/null Sat Sep 1 00:07:32 2012
+++ src/sys/arch/arm/imx/files.imx6 Sat Sep 1 00:07:32 2012
@@ -0,0 +1,105 @@
+# $NetBSD: files.imx6,v 1.1 2012/09/01 00:07:32 matt Exp $
+#
+# Configuration info for the Freescale i.MX6
+#
+
+defparam opt_imx.h MEMSIZE
+defflag opt_imx.h IMX6
+
+define bus_dma_generic
+
+file arch/arm/imx/imx_space.c
+file arch/arm/imx/imx_dma.c bus_dma_generic needs-flag
+
+# iMX6 AXI/AHB bus interface and SoC domains
+device axi { [addr=-1], [size=0], [irq=-1], [irqbase=-1]} : bus_space_generic
+attach axi at mainbus
+file arch/arm/imx/imx6_axi.c axi
+
+# iMX6 Enhanced Periodic Interrupt Timer
+device imxclock
+attach imxclock at axi
+file arch/arm/imx/imxclock.c
+file arch/arm/imx/imx6_clock.c
+
+# Clock Control Module
+device imxccm
+attach imxccm at axi
+file arch/arm/imx/imx6_ccm.c imxccm needs-flag
+
+# frequency of external low frequency clock
+# typically 32000, 32768, or 38400.
+defparam opt_imx6clk.h IMX6_CKIL_FREQ
+
+# frequency of on-chip oscillator. typically 24000000.
+defparam opt_imx6clk.h IMX6_OSC_FREQ
+
+# following parameters are used when imxccm is not configured in the kernel.
+defparam opt_imx6clk.h IMX6_AHBCLK_FREQ
+defparam opt_imx6clk.h IMX6_IPGCLK_FREQ
+
+# iMX GPIO
+#device imxgpio: gpiobus
+attach imxgpio at axi
+#file arch/arm/imx/imxgpio.c imxgpio needs-flag
+#file arch/arm/imx/imx6_gpio.c imxgpio
+
+# iMX IOMUX
+#device imxiomux : bus_space_generic
+#attach imxiomux at axi
+#file arch/arm/imx/imx6_iomux.c imxiomux
+
+# IPU v3 controller
+#device ipu : bus_dma_generic, wsemuldisplaydev, rasops16, rasops8, rasops4, rasops_rotation, vcons
+#file arch/arm/imx/imx6_ipuv3.c ipu needs-flag
+#defflag opt_imx6_ipuv3.h IMXIPUCONSOLE
+#defparam opt_imx6_ipuv3.h IPUV3_DEBUG
+
+# iMX M3IF - Multi Master Memory Interface
+# iMX ESDCTL/MDDRC - Enhanced SDRAM/LPDDR memory controller
+# iMX PCMCIA - PCMCIA memory controller
+# iMX NANDFC - NAND Flash memory controller
+# iMX WEIM - Wireless External Interface Module
+
+# iMX UART
+device imxuart
+attach imxuart at axi
+file arch/arm/imx/imxuart.c imxuart needs-flag
+file arch/arm/imx/imx6_uart.c imxuart
+defflag opt_imxuart.h IMXUARTCONSOLE
+
+# USB controller
+# attach of this driver need to be specified in paltform configuration
+device imxusbc { unit, irq } : bus_dma_generic
+file arch/arm/imx/imx6_usb.c imxusbc
+
+attach ehci at imxusbc with imxehci
+file arch/arm/imx/imxusb.c imxehci
+
+# attach wdc at ahb with wdc_ahb : bus_dma_generic
+# file arch/arm/imx/wdc_axi.c wdc_axi
+
+# SD host controller for SD/MMC
+attach sdhc at axi with sdhc_axi
+file arch/arm/imx/imx6_esdhc.c sdhc_axi
+
+# iic Controler
+# device imxi2c: i2cbus
+# file arch/arm/imx/imx6_i2c.c imxi2c
+
+# attach imxi2c at aips with imxi2c_aips
+# file arch/arm/imx/imxi2c_aips.c imxi2c_aips
+
+# spi bus controlloer
+# device imxspi: spibus
+# file arch/arm/imx/imx6_spi.c imxspi
+
+# Smart Direct Memory Access Controller
+# device imxsdma: dmover_service, bus_dma_generic
+# attach imxsdma at ahb
+# file arch/arm/imx/imxsdma.c imxsdma
+# file arch/arm/imx/imxsdmaprog.c imxsdma
+
+# iis sound Controller (SSI module)
+# device imxi2s {} : bus_dma_generic
+# file arch/arm/imx/imx6_i2s.c imxi2s needs-flag
Index: src/sys/arch/arm/imx/imx6_intr.h
diff -u /dev/null src/sys/arch/arm/imx/imx6_intr.h:1.1
--- /dev/null Sat Sep 1 00:07:32 2012
+++ src/sys/arch/arm/imx/imx6_intr.h Sat Sep 1 00:07:32 2012
@@ -0,0 +1,172 @@
+/* $NetBSD: imx6_intr.h,v 1.1 2012/09/01 00:07:32 matt Exp $ */
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ARM_IMX6_INTR_H_
+#define _ARM_ARM_IMX6_INTR_H_
+
+#define PIC_MAXSOURCES 256
+#define PIC_MAXMAXSOURCES (256 + 6 * 32)
+
+/*
+ * The BCM53xx uses a generic interrupt controller so pull that stuff.
+ */
+#include <arm/cortex/gic_intr.h>
+#include <arm/cortex/a9tmr_intr.h> /* A9 Timer PPIs */
+
+#define IRQ_IOMUXC 32
+#define IRQ_DAP 33
+#define IRQ_SDMA 34
+#define IRQ_VPU_JPEG 35
+#define IRQ_SNVS 36
+#define IRQ_IPU1_ERROR 37
+#define IRQ_IPU1_SYNC 38
+#define IRQ_IPU2_ERROR 39
+#define IRQ_IPU2_SYNC 40
+#define IRQ_GPU3D 41
+#define IRQ_GPU2D_IDLE 42
+#define IRQ_GPU2D 43
+#define IRQ_VPU 44
+#define IRQ_APBH 45
+#define IRQ_EIM 46
+#define IRQ_BCH 47
+#define IRQ_GPMI 48
+#define IRQ_DTCP 49
+#define IRQ_VDOA 50
+#define IRQ_SNVS 51
+#define IRQ_SNVS_SEC 52
+#define IRQ_CSU 53
+#define IRQ_USDHC1 54
+#define IRQ_USDHC2 55
+#define IRQ_USDHC3 56
+#define IRQ_USDHC4 57
+#define IRQ_UART1 58
+#define IRQ_UART2 59
+#define IRQ_UART3 60
+#define IRQ_UART4 61
+#define IRQ_UART5 62
+#define IRQ_ECSPI1 63
+#define IRQ_ECSPI2 64
+#define IRQ_ECSPI3 65
+#define IRQ_ECSPI4 66
+#define IRQ_ECSPI5 67
+#define IRQ_I2C1 68
+#define IRQ_I2C2 69
+#define IRQ_I2C3 70
+#define IRQ_SATA 71
+#define IRQ_USB1 72
+#define IRQ_USB2 73
+#define IRQ_USB3 74
+#define IRQ_USBOTG 75
+#define IRQ_USBPHY0 76
+#define IRQ_USBPHY1 77
+#define IRQ_SSI1 78
+#define IRQ_SSI2 79
+#define IRQ_SSI3 80
+#define IRQ_TEMP 81
+#define IRQ_ASRC 82
+#define IRQ_ESAI 83
+#define IRQ_SPDIF 84
+#define IRQ_MLB 85
+#define IRQ__RSVD86 86
+#define IRQ_GPT 87
+#define IRQ_EPIT1 88
+#define IRQ_EPIT2 89
+#define IRQ_GPIO7 90
+#define IRQ_GPIO6 91
+#define IRQ_GPIO5 92
+#define IRQ_GPIO4 93
+#define IRQ_GPIO3 94
+#define IRQ_GPIO2 95
+#define IRQ_GPIO1 96
+#define IRQ_GPIO0 97
+#define IRQ_GPIO1L 98
+#define IRQ_GPIO1H 99
+#define IRQ_GPIO2L 100
+#define IRQ_GPIO2H 101
+#define IRQ_GPIO3L 102
+#define IRQ_GPIO3H 103
+#define IRQ_GPIO4L 104
+#define IRQ_GPIO4H 105
+#define IRQ_GPIO5L 106
+#define IRQ_GPIO5H 107
+#define IRQ_GPIO6L 108
+#define IRQ_GPIO6H 109
+#define IRQ_GPIO7L 110
+#define IRQ_GPIO7H 111
+#define IRQ_WDOG1 112
+#define IRQ_WDOG2 113
+#define IRQ_KPP 114
+#define IRQ_PWM1 115
+#define IRQ_PWM2 116
+#define IRQ_PWM3 117
+#define IRQ_PWM4 118
+#define IRQ_CCM1 119
+#define IRQ_CCM2 120
+#define IRQ_GPC 121
+#define IRQ__RSVD122 122
+#define IRQ_SRC 123
+#define IRQ_CPU_L2 124
+#define IRQ_CPU_PARITY 125
+#define IRQ_CPU_PMU 126
+#define IRQ_CPU_CTI 127
+#define IRQ_CPU_WDOG 128
+#define IRQ__RSVD129 129
+#define IRQ__RSVD130 130
+#define IRQ__RSVD131 131
+#define IRQ_MIPI_CSI1 132
+#define IRQ_MIPI_CSI2 133
+#define IRQ_MIPI_DSI 134
+#define IRQ_MIPI_HSI 135
+#define IRQ_SJC 136
+#define IRQ_CAAM0 137
+#define IRQ_CAAM1 138
+#define IRQ__RSVD139 139
+#define IRQ_ASC1 140
+#define IRQ_ASC2 141
+#define IRQ_FLEXCAN1 142
+#define IRQ_FLEXCAN2 143
+#define IRQ__RSVD139 144
+#define IRQ__RSVD139 145
+#define IRQ__RSVD139 146
+#define IRQ_HDMI_MASTER 147
+#define IRQ_HDMI_CEC 148
+#define IRQ_MLB150L 149
+#define IRQ_ENET 150
+#define IRQ_ENET_1588 151
+#define IRQ_PCIE1 152
+#define IRQ_PCIE2 153
+#define IRQ_PCIE3 154
+#define IRQ_PCIE4 155
+#define IRQ_DCIC1 156
+#define IRQ_DCIC2 157
+#define IRQ_MLB150H 158
+#define IRQ_PMU 159
+
+#endif /* _ARM_ARM_IMX6INTR_H_ */
Index: src/sys/arch/arm/imx/imx6_reg.h
diff -u /dev/null src/sys/arch/arm/imx/imx6_reg.h:1.1
--- /dev/null Sat Sep 1 00:07:32 2012
+++ src/sys/arch/arm/imx/imx6_reg.h Sat Sep 1 00:07:32 2012
@@ -0,0 +1,198 @@
+/* $NetBSD: imx6_reg.h,v 1.1 2012/09/01 00:07:32 matt Exp $ */
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_IMX_IMX6_REG_H_
+#define _ARM_IMX_IMX6_REG_H_
+
+#define IMX6_MEM_BASE 0x10000000
+#define IMX6_MEM_SIZE 0xF0000000
+
+#define IMX6_CS0_BASE 0x08000000
+#define IMX6_CS0_SIZE 0x08000000
+
+#define IMX6_IPU2_BASE 0x02c00000
+#define IMX6_IPU2_SIZE 0x00400000
+
+#define IMX6_IPU1_BASE 0x02800000
+#define IMX6_IPU1_SIZE 0x00400000
+
+#define IMX6_HSI_BASE 0x02208000
+#define IMX6_HSI_SIZE 0x00004000
+
+#define IMX6_GPU2D_BASE 0x02204000
+#define IMX6_GPU2D_SIZE 0x00004000
+
+#define IMX6_SATA_BASE 0x02200000
+#define IMX6_SATA_SIZE 0x00004000
+
+#define IMX6_AIPS2_BASE 0x02100000
+#define IMX6_AIPS2_SIZE 0x00100000
+
+#define IMX6_AIPS1_BASE 0x02000000
+#define IMX6_AIPS1_SIZE 0x00100000
+
+#define IMX6_PCIE_BASE 0x01ffc000
+#define IMX6_PCIE_SIZE 0x00004000
+
+#define IMX6_PCIEMEM_BASE 0x01000000
+#define IMX6_PCIEMEM_SIZE 0x00ffc000
+
+#define IMX6_GPV1_BASE 0x00c00000
+#define IMX6_GPV1_SIZE 0x00100000
+
+#define IMX6_GPV0_BASE 0x00b00000
+#define IMX6_GPV0_SIZE 0x00100000
+
+#define IMX6_L2CC_BASE 0x00a02000
+#define IMX6_L2CC_SIZE 0x00001000
+
+#define IMX6_MPCORE_BASE 0x00a00000
+#define IMX6_MPCORE_SIZE 0x00a00000
+
+#define IMX6_OCRAM1_BASE 0x00940000
+#define IMX6_OCRAM1_SIZE 0x000c0000
+
+#define IMX6_OCRAM0_BASE 0x00900000
+#define IMX6_OCRAM0_SIZE 0x00040000
+
+#define IMX6_GPV4_BASE 0x00800000
+#define IMX6_GPV4_SIZE 0x00100000
+
+#define IMX6_GPV3_BASE 0x00300000
+#define IMX6_GPV3_SIZE 0x00100000
+
+#define IMX6_GPV2_BASE 0x00200000
+#define IMX6_GPV2_SIZE 0x00100000
+
+#define IMX6_DTPC_BASE 0x00138000
+#define IMX6_DTPC_SIZE 0x00004000
+
+#define IMX6_GPU2D_BASE 0x00134000
+#define IMX6_GPU2D_SIZE 0x00004000
+
+#define IMX6_GPU3D_BASE 0x00130000
+#define IMX6_GPU3D_SIZE 0x00004000
+
+#define IMX6_HDMI_BASE 0x00120000
+#define IMX6_HDMI_SIZE 0x00009000
+
+#define IMX6_APBHDMA_BASE 0x00110000
+#define IMX6_APBHDMA_SIZE 0x00002000
+
+#define IMX6_GPMI_BASE 0x00112000
+#define IMX6_GPMI_SIZE 0x00002000
+
+#define IMX6_BCH_BASE 0x00114000
+#define IMX6_BCH_SIZE 0x00004000
+
+#define IMX6_CAAM_BASE 0x00100000
+#define IMX6_CAAM_SIZE 0x00004000
+
+#define IMX6_ROMCP_BASE 0x00000000
+#define IMX6_ROMCP_SIZE 0x00018000
+
+#define AIPS1_SDMA_BASE 0x000ec000
+#define AIPS1_DCIC2_BASE 0x000e8000
+#define AIPS1_DCIC1_BASE 0x000e4000
+#define AIPS1_IOMUXC_BASE 0x000e0000
+#define AIPS1_GPC_BASE 0x000dc000
+#define AIPS1_SRC_BASE 0x000d8000
+#define AIPS1_EPIT2_BASE 0x000d4000
+#define AIPS1_EPIT1_BASE 0x000d0000
+#define AIPS1_SNVS_HP_BASE 0x000cc000
+#define AIPS1_USBPHY2_BASE 0x000ca000
+#define AIPS1_USBPHY1_BASE 0x000c9000
+#define AIPS1_ANATOP_DIG_BASE 0x000c8000
+#define AIPS1_CCM_BASE 0x000c4000
+#define AIPS1_WDOG2_BASE 0x000c0000
+#define AIPS1_WDOG1_BASE 0x000bc000
+#define AIPS1_KPP_BASE 0x000b8000
+#define AIPS1_GPIO7_BASE 0x000b4000
+#define AIPS1_GPIO6_BASE 0x000b0000
+#define AIPS1_GPIO5_BASE 0x000ac000
+#define AIPS1_GPIO4_BASE 0x000a8000
+#define AIPS1_GPIO3_BASE 0x000a4000
+#define AIPS1_GPIO2_BASE 0x000a0000
+#define AIPS1_GPIO1_BASE 0x0009c000
+#define AIPS1_GPT_BASE 0x00098000
+#define AIPS1_CAN2_BASE 0x00094000
+#define AIPS1_CAN1_BASE 0x00090000
+#define AIPS1_PWM4_BASE 0x0008c000
+#define AIPS1_PWM3_BASE 0x00088000
+#define AIPS1_PWM2_BASE 0x00084000
+#define AIPS1_PWM1_BASE 0x00080000
+#define AIPS1_CONFIG_BASE 0x0007c000
+#define AIPS1_VPU_BASE 0x00040000
+#define AIPS1_SPBA_BASE 0x0003c000
+#define AIPS1_ASRC_BASE 0x00034000
+#define AIPS1_SSI3_BASE 0x00030000
+#define AIPS1_SSI2_BASE 0x0002c000
+#define AIPS1_SSI1_BASE 0x00028000
+#define AIPS1_ESAI_BASE 0x00024000
+#define AIPS1_UART1_BASE 0x00020000
+#define AIPS1_ECSPI5_BASE 0x00018000
+#define AIPS1_ECSPI4_BASE 0x00014000
+#define AIPS1_ECSPI3_BASE 0x00010000
+#define AIPS1_ECSPI2_BASE 0x0000c000
+#define AIPS1_ECSPI1_BASE 0x00008000
+#define AIPS1_SPDIF_BASE 0x00004000
+
+#define AIPS2_UART5_BASE 0x001f4000
+#define AIPS2_UART4_BASE 0x001f0000
+#define AIPS2_UART3_BASE 0x001ec000
+#define AIPS2_UART2_BASE 0x001e8000
+#define AIPS2_VDOA_BASE 0x001e3000
+#define AIPS2_MIPIDSI_BASE 0x001e0000
+#define AIPS2_MIPICSI_BASE 0x001dc000
+#define AIPS2_AUDMUX_BASE 0x001d8000
+#define AIPS2_TZASC2_BASE 0x001d4000
+#define AIPS2_TZASC1_BASE 0x001d0000
+#define AIPS2_CSU_BASE 0x001c0000
+#define AIPS2_OCOTP_CTRL_BASE 0x001bc000
+#define AIPS2_WEIM_BASE 0x001b8000
+#define AIPS2_MMDC1_BASE 0x001b4000
+#define AIPS2_MMDC0_BASE 0x001b0000
+#define AIPS2_ROMCP_BASE 0x001ac000
+#define AIPS2_I2C3_BASE 0x001a8000
+#define AIPS2_I2C2_BASE 0x001a4000
+#define AIPS2_I2C1_BASE 0x001a0000
+#define AIPS2_USDHC4_BASE 0x0019c000
+#define AIPS2_USDHC3_BASE 0x00198000
+#define AIPS2_USDHC2_BASE 0x00194000
+#define AIPS2_USDHC1_BASE 0x00190000
+#define AIPS2_MLB150_BASE 0x0018c000
+#define AIPS2_ENET_BASE 0x00188000
+#define AIPS2_USBOH3A_BASE 0x00184000
+#define AIPS2_USBOH3B_BASE 0x00180000
+#define AIPS2_CONFIG_BASE 0x0017c000
+#define AIPS2_DAP_BASE 0x00140000
+#define AIPS2_CAAM_BASE 0x00100000
+
+#endif /* _ARM_IMX_IMX6_REG_H_ */
