Module Name: src
Committed By: matt
Date: Sat Sep 1 00:15:11 UTC 2012
Added Files:
src/sys/arch/evbarm/bcm53xx: bcm53xx_machdep.c bcm53xx_start.S
genassym.cf platform.h
src/sys/arch/evbarm/conf: BCM5301X files.bcm53xx mk.bcm53xx std.bcm53xx
Log Message:
Add support for the BCM95301X development board
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c \
src/sys/arch/evbarm/bcm53xx/bcm53xx_start.S \
src/sys/arch/evbarm/bcm53xx/genassym.cf \
src/sys/arch/evbarm/bcm53xx/platform.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbarm/conf/BCM5301X \
src/sys/arch/evbarm/conf/files.bcm53xx \
src/sys/arch/evbarm/conf/mk.bcm53xx src/sys/arch/evbarm/conf/std.bcm53xx
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c
diff -u /dev/null src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c:1.1
--- /dev/null Sat Sep 1 00:15:11 2012
+++ src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c Sat Sep 1 00:15:11 2012
@@ -0,0 +1,268 @@
+/* $NetBSD: bcm53xx_machdep.c,v 1.1 2012/09/01 00:15:11 matt Exp $ */
+
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define CCA_PRIVATE
+#define IDM_PRIVATE
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: bcm53xx_machdep.c,v 1.1 2012/09/01 00:15:11 matt Exp $");
+
+#include "opt_evbarm_boardtype.h"
+#include "opt_broadcom.h"
+#include "opt_kgdb.h"
+#include "com.h"
+#include "bcmrng_ccb.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/atomic.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/reboot.h>
+#include <sys/termios.h>
+
+#include <dev/cons.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <arm/db_machdep.h>
+#include <arm/undefined.h>
+#include <arm/arm32/machdep.h>
+
+#include <machine/autoconf.h>
+#include <machine/bootconfig.h>
+
+#define CCA_PRIVATE
+
+#include <arm/cortex/scu_reg.h>
+#include <arm/broadcom/bcm53xx_var.h>
+
+#include <evbarm/bcm53xx/platform.h>
+
+#if NCOM == 0
+#error missing COM device for console
+#endif
+
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+
+extern int _end[];
+extern int KERNEL_BASE_phys[];
+extern int KERNEL_BASE_virt[];
+
+BootConfig bootconfig;
+static char bootargs[MAX_BOOT_STRING];
+char *boot_args = NULL;
+
+static void bcm53xx_system_reset(void);
+
+/*
+ * Macros to translate between physical and virtual for a subset of the
+ * kernel address space. *Not* for general use.
+ */
+#define KERN_VTOPDIFF ((vaddr_t)KERNEL_BASE_phys - (vaddr_t)KERNEL_BASE_virt)
+#define KERN_VTOPHYS(va) ((paddr_t)((vaddr_t)va + KERN_VTOPDIFF))
+#define KERN_PHYSTOV(pa) ((vaddr_t)((paddr_t)pa - KERN_VTOPDIFF))
+
+#ifndef CONADDR
+#define CONADDR (BCM53XX_IOREG_PBASE + CCA_UART0_BASE)
+#endif
+#ifndef CONSPEED
+#define CONSPEED B115200
+#endif
+#ifndef CONMODE
+#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
+#endif
+
+#if (NCOM > 0)
+static const bus_addr_t comcnaddr = (bus_addr_t)CONADDR;
+
+int comcnspeed = CONSPEED;
+int comcnmode = CONMODE | CLOCAL;
+#endif
+
+#ifdef KGDB
+#include <sys/kgdb.h>
+#endif
+
+/*
+ * Static device mappings. These peripheral registers are mapped at
+ * fixed virtual addresses very early in initarm() so that we can use
+ * them while booting the kernel, and stay at the same address
+ * throughout whole kernel's life time.
+ *
+ * We use this table twice; once with bootstrap page table, and once
+ * with kernel's page table which we build up in initarm().
+ *
+ * Since we map these registers into the bootstrap page table using
+ * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map
+ * registers segment-aligned and segment-rounded in order to avoid
+ * using the 2nd page tables.
+ */
+
+static const struct pmap_devmap devmap[] = {
+ {
+ KERNEL_IO_VBASE,
+ BCM53XX_IOREG_PBASE, /* 0x18000000 */
+ BCM53XX_IOREG_SIZE, /* 2MB */
+ VM_PROT_READ|VM_PROT_WRITE,
+ PTE_NOCACHE,
+ },
+ {
+ KERNEL_IO_VBASE + BCM53XX_IOREG_SIZE,
+ BCM53XX_ARMCORE_PBASE, /* 0x19000000 */
+ BCM53XX_ARMCORE_SIZE, /* 16MB */
+ VM_PROT_READ|VM_PROT_WRITE,
+ PTE_NOCACHE,
+ },
+ { 0, 0, 0, 0, 0 }
+};
+
+/*
+ * u_int initarm(...)
+ *
+ * Initial entry point on startup. This gets called before main() is
+ * entered.
+ * It should be responsible for setting up everything that must be
+ * in place when main is called.
+ * This includes
+ * Taking a copy of the boot configuration structure.
+ * Initialising the physical console so characters can be printed.
+ * Setting up page tables for the kernel
+ */
+u_int
+initarm(void *arg)
+{
+ pmap_devmap_register(devmap);
+ bcm53xx_bootstrap(KERNEL_IO_VBASE);
+
+#ifdef MULTIPROCESSOR
+ uint32_t scu_cfg = bus_space_read_4(bcm53xx_armcore_bst, bcm53xx_armcore_bsh,
+ ARMCORE_SCU_BASE + SCU_CFG);
+ arm_cpu_max = scu_cfg & SCU_CFG_CPUMAX;
+ membar_producer();
+#endif
+ /*
+ * Heads up ... Setup the CPU / MMU / TLB functions
+ */
+ if (set_cpufuncs()) // starts PMC counter
+ panic("cpu not recognized!");
+
+ cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
+
+ consinit();
+
+ bcm53xx_cpu_softc_init(curcpu());
+ bcm53xx_print_clocks();
+
+#if NBCMRNG_CCB > 0
+ /*
+ * Start this early since it takes a while to startup up.
+ */
+ bcm53xx_rng_start(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh);
+#endif
+
+ /* Talk to the user */
+ printf("\nNetBSD/evbarm (" ___STRING(EVBARM_BOARDTYPE) ") booting ...\n");
+
+ bootargs[0] = '\0';
+
+#if defined(VERBOSE_INIT_ARM) || 1
+ printf("initarm: Configuring system");
+#ifdef MULTIPROCESSOR
+ printf(" (%u cpu%s, hatched %#x)",
+ arm_cpu_max + 1, arm_cpu_max + 1 ? "s" : "",
+ arm_cpu_hatched);
+#endif
+ printf("\n");
+#endif
+
+ arm32_bootmem_init(KERN_VTOPHYS(KERNEL_BASE), bcm53xx_memprobe(),
+ (paddr_t)KERNEL_BASE_phys);
+
+ /*
+ * This is going to do all the hard work of setting up the first and
+ * and second level page tables. Pages of memory will be allocated
+ * and mapped for other structures that are required for system
+ * operation. When it returns, physical_freestart and free_pages will
+ * have been updated to reflect the allocations that were made. In
+ * addition, kernel_l1pt, kernel_pt_table[], systempage, irqstack,
+ * abtstack, undstack, kernelstack, msgbufphys will be set to point to
+ * the memory that was allocated for them.
+ */
+ arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, devmap, true);
+
+ cpu_reset_address = bcm53xx_system_reset;
+ /* we've a specific device_register routine */
+ evbarm_device_register = bcm53xx_device_register;
+
+ return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
+}
+
+void
+consinit(void)
+{
+ static bool consinit_called = false;
+ uint32_t v;
+ if (consinit_called)
+ return;
+
+ consinit_called = true;
+
+ /*
+ * Force UART clock to the reference clock
+ */
+ v = bus_space_read_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
+ IDM_BASE + IDM_APBX_BASE + IDM_IO_CONTROL_DIRECT);
+ v &= ~IO_CONTROL_DIRECT_UARTCLKSEL;
+ bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
+ IDM_BASE + IDM_APBX_BASE + IDM_IO_CONTROL_DIRECT, v);
+
+ /*
+ * Switch to the reference clock
+ */
+ v = bus_space_read_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
+ CCA_MISC_BASE + MISC_CORECTL);
+ v &= ~CORECTL_UART_CLK_OVERRIDE;
+ bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
+ CCA_MISC_BASE + MISC_CORECTL, v);
+
+ if (comcnattach(bcm53xx_ioreg_bst, comcnaddr, comcnspeed,
+ BCM53XX_REF_CLK, COM_TYPE_NORMAL, comcnmode))
+ panic("Serial console can not be initialized.");
+}
+
+static void
+bcm53xx_system_reset(void)
+{
+ bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
+ MISC_WATCHDOG, 1);
+}
Index: src/sys/arch/evbarm/bcm53xx/bcm53xx_start.S
diff -u /dev/null src/sys/arch/evbarm/bcm53xx/bcm53xx_start.S:1.1
--- /dev/null Sat Sep 1 00:15:11 2012
+++ src/sys/arch/evbarm/bcm53xx/bcm53xx_start.S Sat Sep 1 00:15:11 2012
@@ -0,0 +1,525 @@
+/* $NetBSD: bcm53xx_start.S,v 1.1 2012/09/01 00:15:11 matt Exp $ */
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+//#define GXEMUL
+
+#include "opt_broadcom.h"
+#include "opt_cpuoptions.h"
+#include "opt_cputypes.h"
+#include "opt_multiprocessor.h"
+
+#include <arm/asm.h>
+#include <arm/armreg.h>
+#include "assym.h"
+
+#include <arm/cortex/a9tmr_reg.h>
+
+RCSID("$NetBSD: bcm53xx_start.S,v 1.1 2012/09/01 00:15:11 matt Exp $")
+
+#undef VERBOSE_INIT_ARM
+#define VERBOSE_INIT_ARM
+
+#if defined(VERBOSE_INIT_ARM)
+#define PUTC(n) mov r0, n; bl xputc
+#else
+#define PUTC(n)
+#endif
+
+/*
+ * Kernel start routine for BCM5301X boards.
+ * At this point, this code has been loaded into SDRAM
+ * and the MMU is off
+ */
+ .text
+
+ .global _C_LABEL(bcm53xx_start)
+_C_LABEL(bcm53xx_start):
+ cpsid if, #PSR_SVC32_MODE
+
+ PUTC(#64)
+ bl _C_LABEL(armv7_icache_inv_all) @ invalidate i-cache
+
+ /*
+ * Step 1a, invalidate the all cache tags in all ways on the SCU.
+ */
+ PUTC(#65)
+ mrc p15, 4, r3, c15, c0, 0 @ read cbar
+
+ mrc p15, 0, r0, c0, c0, 5 @ get MPIDR
+ and r0, r0, #7 @ get our cpu numder
+ lsl r0, r0, #2 @ multiply by 4
+ mov r1, #0xf @ select all ways
+ lsl r1, r1, r0 @ shift into place
+ str r1, [r3, #12] @ write scu invalidate all
+ dsb
+ isb
+
+ /*
+ * Step 1b, invalidate the data cache
+ */
+ PUTC(#66)
+ bl _C_LABEL(armv7_dcache_wbinv_all) @ writeback/invalidate d-cache
+
+ /*
+ * Step 2, disable the data cache
+ */
+ mrc p15, 0, r2, c1, c0, 0 @ get system ctl register (save)
+ bic r1, r2, #CPU_CONTROL_DC_ENABLE @ clear data cache enable
+ mcr p15, 0, r1, c1, c0, 0 @ set system ctl register
+ isb
+
+ /*
+ * Step 3, enable the SCU (and set SMP mode)
+ */
+ ldr r1, [r3, #4] @ read scu config
+ orr r1, r1, #0xf0 @ set smp mode
+ str r1, [r3, #4] @ write scu config
+ ldr r1, [r3, #0] @ read scu control
+ orr r1, r1, #1 @ set scu enable flag
+ str r1, [r3, #4] @ write scu control
+ dsb
+ isb
+
+ /*
+ * Step 4a, enable the data cache
+ */
+ mcr p15, 0, r2, c1, c0, 0 @ reenable caches
+ isb
+
+ /*
+ * Step 4b, set ACTLR.SMP=1 (and ACTRL.FX=1)
+ */
+ mrc p15, 0, r0, c1, c0, 1 @ read aux ctl
+ orr r0, #0x40 @ enable SMP mode
+ mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
+ isb
+ orr r0, #0x1 @ enable cache/tlb/coherency
+ mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
+ isb
+
+ PUTC(#67)
+ /*
+ * Set up a preliminary mapping in the MMU to allow us to run
+ * at KERNEL_BASE with caches on.
+ */
+ /* Build page table from scratch */
+ ldr r0, .Ltemp_l1_table /* The page table address - entered into TTB later */
+ mov r1, r0 /* Start address to clear memory. */
+ /* Zero the entire table so all virtual addresses are invalid. */
+ mov r2, #L1_TABLE_SIZE /* in bytes */
+ mov r3, #0
+ mov r4, r3
+ mov r5, r3
+ mov r6, r3
+ mov r7, r3
+ mov r8, r3
+ mov r10, r3
+ mov r11, r3
+1: stmia r1!, {r3-r8,r10-r11}
+ stmia r1!, {r3-r8,r10-r11}
+ stmia r1!, {r3-r8,r10-r11}
+ stmia r1!, {r3-r8,r10-r11}
+ subs r2, r2, #(4 * 4 * 8) /* bytes per loop */
+ bne 1b
+
+ /* Now create our entries per the mmu_init_table. */
+ l1table .req r0
+ va .req r1
+ pa .req r2
+ n_sec .req r3
+ attr .req r4
+ itable .req r5
+
+ adr itable, mmu_init_table
+ b 3f
+
+2: str pa, [l1table, va]
+ add va, va, #4
+ add pa, pa, #(L1_S_SIZE)
+ subs n_sec, n_sec, #1
+ bhi 2b
+
+3: ldmia itable!, {va,pa,n_sec,attr}
+ /* Convert va to l1 offset: va = 4 * (va >> L1_S_SHIFT) */
+ lsr va, va, #L1_S_SHIFT
+ lsl va, va, #2
+ /* Convert pa to l1 entry: pa = (pa & L1_S_FRAME) | attr */
+ bfc pa, #0, #L1_S_SHIFT
+ orr pa, pa, attr
+ cmp n_sec, #0
+ bne 2b
+
+ .unreq va
+ .unreq pa
+ .unreq n_sec
+ .unreq attr
+ .unreq itable
+ .unreq l1table
+
+ PUTC(#68)
+ /*
+ * Before we turn on the MMU, let's the other process out of the
+ * SKU ROM but setting the magic LUT address to our own mp_start
+ * routine.
+ */
+ ldr r1, .Lsku_rom_lut
+ adr r2, mp_start
+ str r2, [r1]
+ sev /* wake up the others */
+
+ /*
+ * init the CPU TLB, Cache, MMU.
+ */
+ PUTC(#69)
+
+ ldr r0, .Ltemp_l1_table /* The page table address */
+ bl cpu_init
+
+ PUTC(#33)
+ PUTC(#10)
+ PUTC(#13)
+
+ /*
+ * Jump to start in locore.S, which in turn will call initarm and main.
+ */
+ b start
+ nop
+ nop
+ nop
+ nop
+
+ /* NOTREACHED */
+
+.Lsku_rom_lut:
+ .word 0xffff0400
+
+.Ltemp_l1_table:
+ /* Put the temporary L1 translation table far enough away. */
+ .word KERNEL_BASE_phys + 31 * 0x100000 - L1_TABLE_SIZE
+
+/*
+ * Coprocessor register initialization values
+ */
+
+ .p2align 3
+ /* bits to clear in the Control Register */
+.Lcontrol_clr:
+ .word 0
+
+ /* bits to set in the Control Register */
+.Lcontrol_set:
+ .word CPU_CONTROL_MMU_ENABLE | \
+ CPU_CONTROL_AFLT_ENABLE | \
+ CPU_CONTROL_DC_ENABLE | \
+ CPU_CONTROL_SYST_ENABLE | \
+ CPU_CONTROL_SWP_ENABLE | \
+ CPU_CONTROL_IC_ENABLE
+#if 0
+ (15 << 3) | /* SBOP */ \
+ (1 << 16) | /* SBO */ \
+ (1 << 18) | /* SBO */ \
+ (3 << 22) /* SB0 */
+#endif
+
+ /* bits to disable the caches */
+.Lctl_ID_dis:
+ .word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
+
+/* We'll modify va and pa at run time so we can use relocatable addresses. */
+#define MMU_INIT(va,pa,n_sec,attr) \
+ .word va ; \
+ .word pa ; \
+ .word n_sec ; \
+ .word attr ;
+
+mmu_init_table:
+ /* Add 32MB of VA==PA at 0x80000000 so we can keep the kernel going */
+ MMU_INIT(KERNEL_BASE, 0x80000000,
+ (128 * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO | L1_S_APv7_KRW | L1_S_B | L1_S_C)
+
+ MMU_INIT(0, 0x00000000,
+ (16 * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO | L1_S_APv7_KRW | L1_S_B | L1_S_C)
+
+ /* Map the 2MB of primary peripherals */
+ MMU_INIT(KERNEL_IO_VBASE, BCM53XX_IOREG_PBASE,
+ (BCM53XX_IOREG_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO | L1_S_APv7_KRW)
+
+ /* Map the 2MB of primary peripherals at PA:VA 1:1 */
+ MMU_INIT(BCM53XX_IOREG_PBASE, BCM53XX_IOREG_PBASE,
+ (BCM53XX_IOREG_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO | L1_S_APv7_KRW)
+
+ /* Map the 1MB of armcore peripherals */
+ MMU_INIT(KERNEL_IO_VBASE + BCM53XX_IOREG_SIZE,
+ BCM53XX_ARMCORE_PBASE,
+ (BCM53XX_ARMCORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO | L1_S_APv7_KRW)
+
+ /* end of table */
+ MMU_INIT(0, 0, 0, 0)
+
+cpu_init:
+ /*
+ * In theory, because the MMU is off, we shouldn't need all of this,
+ * but let's not take any chances and do a typical sequence to set
+ * the Translation Table Base.
+ */
+ mov ip, lr
+ mov r10, r0
+ mov r1, #0 /* SBZ */
+
+ ldr r3, .Lctl_ID_dis /* Disable I+D caches */
+ mrc p15, 0, r2, c1, c0, 0 /* " " " */
+ and r2, r2, r3 /* " " " */
+ mcr p15, 0, r2, c1, c0, 0 /* " " " */
+
+ PUTC(#70)
+ mov r1, #0
+ mcr p15, 0, r1, c7, c10, 4 /* Drain the write buffers. */
+
+ PUTC(#71)
+ mcr p15, 0, r10, c2, c0, 0 /* Set Translation Table Base */
+
+ PUTC(#72)
+ mov r1, #0
+ mcr p15, 0, r1, c8, c7, 0 /* Invalidate TLBs */
+
+ /* Set the Domain Access register. Very important! */
+ PUTC(#74)
+ mov r1, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
+ mcr p15, 0, r1, c3, c0, 0
+
+ /*
+ * Enable the MMU, etc.
+ */
+ PUTC(#75)
+ mrc p15, 0, r0, c1, c0, 0
+
+ ldr r2, .Lcontrol_clr
+ bic r0, r0, r2
+ ldr r3, .Lcontrol_set
+ orr r0, r0, r3
+
+ dsb
+ .align 5
+ @ turn mmu on!
+ mov r0, r0
+ mcr p15, 0, r0, c1, c0, 0
+
+ /*
+ * Ensure that the coprocessor has finished turning on the MMU.
+ */
+ mrc p15, 0, r0, c0, c0, 0 /* Read an arbitrary value. */
+ mov r0, r0 /* Stall until read completes. */
+
+ bx ip /* return */
+
+#if defined(VERBOSE_INIT_ARM)
+#define TIMO 0x25000
+xputc:
+ mov r2, #1
+ ldr r3, .Lcomlock
+10:
+ ldrex r1, [r3]
+ cmp r1, #0
+ bne 10b
+ strex r1, r2, [r3]
+ cmp r1, #0
+ bne 10b
+
+ mov r2, #TIMO
+ ldr r3, .Luart0
+1: ldrb r1, [r3, #COM_LSR]
+ tst r1, #LSR_TXRDY
+ bne 2f
+ subs r2, r2, #1
+ bne 1b
+2:
+ strb r0, [r3, #COM_DATA]
+
+ mov r2, #TIMO
+3: ldrb r1, [r3, #COM_LSR]
+ tst r1, #LSR_TSRE
+ bne 4f
+ subs r2, r2, #1
+ bne 3b
+4:
+ ldr r3, .Lcomlock
+ mov r0, #0
+ str r0, [r3]
+ dsb
+ bx lr
+
+.Luart0:
+ .word 0x18000300
+
+.Lcomlock:
+ .word comlock
+
+ .pushsection .data
+comlock:
+ .p2align 2
+ .word 0 @ not in bss
+
+ .popsection
+#endif /* VERBOSE_INIT_ARM */
+
+/*
+ * Secondary processors come here after exiting the SKU ROM.
+ */
+mp_start:
+#ifdef MULTIPROCESSOR
+ /*
+ * Step 1, invalidate the caches
+ */
+ bl _C_LABEL(armv7_icache_inv_all) @ toss i-cache
+ bl _C_LABEL(armv7_dcache_inv_all) @ toss d-cache
+
+ mrc p15, 0, r4, c0, c0, 5 @ get MPIDR
+ and r4, r4, #7 @ get our cpu numder
+
+ /*
+ * Step 2, wait for the SCU to be enabled
+ */
+ mrc p15, 4, r3, c15, c0, 0 @ read cbar
+1: ldr r0, [r3, #0] @ read scu control
+ tst r0, #1 @ enable bit set yet?
+ bne 1b @ try again
+
+ lsl r0, r4, #2 @ multiply our cpu num by 4
+ mov r1, #0xf @ select all ways
+ lsl r1, r1, r0 @ shift into place
+ str r1, [r3, #12] @ write scu invalidate all
+ dsb
+ isb
+
+ /*
+ * Step 3, set ACTLR.SMP=1 (and ACTRL.FX=1)
+ */
+ mrc p15, 0, r0, c1, c0, 1 @ read aux ctl
+ orr r0, #0x40 @ enable SMP
+ mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
+ isb
+ orr r0, #0x01 @ enable cache/tlb/coherency
+ mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
+ isb
+
+ /*
+ * We should be in SMP mode now.
+ */
+
+#if defined(VERBOSE_INIT_ARM)
+ add r0, r4, #48
+ bl xputc
+#endif
+
+ ldr r0, .Lcpu_hatched @ now show we've hatched
+ mov r5, #1
+ lsl r5, r5, r4
+ mov r1, r5
+ bl _C_LABEL(atomic_or_32)
+
+ PUTC(#97)
+#endif
+
+ cpsid if, #PSR_SVC32_MODE @ make sure we are in SVC mode
+
+ /* Now we will wait for someone tell this cpu to start running */
+#ifdef MULTIPROCESSOR
+ ldr r0, .Lcpu_mbox
+#else
+ cmp r0, r0
+#endif
+2:
+#ifdef MULTIPROCESSOR
+ dmb
+ ldr r2, [r0]
+ tst r2, r5
+#endif
+ @wfeeq
+ beq 2b
+
+#ifdef MULTIPROCESSOR
+3: PUTC(#98)
+ ldr r0, .Lcpu_marker
+ str pc, [r0]
+
+ ldr r0, .Lkernel_l1pt /* get address of l1pt pvaddr */
+ ldr r0, [r0, #PV_PA] /* Now get the phys addr */
+ bl cpu_init
+
+ ldr r0, .Lcpu_marker
+ str pc, [r0]
+
+ /* MMU, L1, are now on. */
+
+ ldr r0, .Lcpu_info /* get pointer to cpu_infos */
+ ldr r5, [r0, r4, lsl #2] /* load our cpu_info */
+ ldr r6, [r5, #CI_IDLELWP] /* get the idlelwp */
+ ldr r7, [r6, #L_PCB] /* now get its pcb */
+ ldr sp, [r7, #PCB_SP] /* finally, we can load our SP */
+#ifdef TPIDRPRW_IS_CURCPU
+ mcr p15, 0, r5, c13, c0, 4 /* squirrel away curcpu() */
+#elif defined(TPIDRPRW_IS_CURLWP)
+ mcr p15, 0, r6, c13, c0, 4 /* squirrel away curlwp() */
+#else
+#error either TPIDRPRW_IS_CURCPU or TPIDRPRW_IS_CURLWP must be defined
+#endif
+ str r6, [r5, #CI_CURLWP] /* and note we are running on it */
+
+ ldr r0, .Lcpu_marker
+ str pc, [r0]
+
+ mov r0, r5 /* pass cpu_info */
+ mov r1, r4 /* pass cpu_id */
+ ldr r2, .Lbcm53xx_cpu_hatch /* pass md_cpu_hatch */
+ bl _C_LABEL(cpu_hatch)
+ b _C_LABEL(idle_loop)
+
+ /* NOT REACHED */
+
+.Lkernel_l1pt:
+ .word _C_LABEL(kernel_l1pt)
+.Lcpu_info:
+ .word _C_LABEL(cpu_info)
+.Lcpu_max:
+ .word _C_LABEL(arm_cpu_max)
+.Lcpu_hatched:
+ .word _C_LABEL(arm_cpu_hatched)
+.Lcpu_mbox:
+ .word _C_LABEL(arm_cpu_mbox)
+.Lcpu_marker:
+ .word _C_LABEL(arm_cpu_marker)
+.Lbcm53xx_cpu_hatch:
+ .word _C_LABEL(bcm53xx_cpu_hatch)
+#endif /* MULTIPROCESSOR */
Index: src/sys/arch/evbarm/bcm53xx/genassym.cf
diff -u /dev/null src/sys/arch/evbarm/bcm53xx/genassym.cf:1.1
--- /dev/null Sat Sep 1 00:15:11 2012
+++ src/sys/arch/evbarm/bcm53xx/genassym.cf Sat Sep 1 00:15:11 2012
@@ -0,0 +1,47 @@
+# $NetBSD: genassym.cf,v 1.1 2012/09/01 00:15:11 matt Exp $
+
+#-
+# Copyright (c) 2012 The NetBSD Foundation, Inc.
+# All rights reserved.
+#
+# This code is derived from software contributed to The NetBSD Foundation
+# by Nick Hudson
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+include <evbarm/bcm53xx/platform.h>
+
+include <dev/ic/ns16550reg.h>
+include <dev/ic/comreg.h>
+
+define BCM53XX_IOREG_PBASE BCM53XX_IOREG_PBASE
+define BCM53XX_IOREG_SIZE BCM53XX_IOREG_SIZE
+define BCM53XX_ARMCORE_PBASE BCM53XX_ARMCORE_PBASE
+define BCM53XX_ARMCORE_SIZE BCM53XX_ARMCORE_SIZE
+define KERNEL_IO_VBASE KERNEL_IO_VBASE
+define KERNEL_IO_VSIZE KERNEL_IO_VSIZE
+
+define LSR_TXRDY LSR_TXRDY
+define LSR_TSRE LSR_TSRE
+define COM_DATA com_data
+define COM_LSR com_lsr
Index: src/sys/arch/evbarm/bcm53xx/platform.h
diff -u /dev/null src/sys/arch/evbarm/bcm53xx/platform.h:1.1
--- /dev/null Sat Sep 1 00:15:11 2012
+++ src/sys/arch/evbarm/bcm53xx/platform.h Sat Sep 1 00:15:11 2012
@@ -0,0 +1,54 @@
+/* $NetBSD: platform.h,v 1.1 2012/09/01 00:15:11 matt Exp $ */
+
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _EVBARM_BCM53XX_PLATFORM_H
+#define _EVBARM_BCM53XX_PLATFORM_H
+
+#include <arm/broadcom/bcm53xx_reg.h>
+
+/*
+ * Memory will be mapped starting at 0x8000_0000 through 0xbfff_ffff
+ * Kernel VM space: KERNEL_VM_BASE to 0xc0000000. Leave 1MB unused.
+ */
+#define KERNEL_VM_BASE (KERNEL_BASE + 0x40000000)
+#define KERNEL_VM_TOP (0xfff00000 - KERNEL_IO_VSIZE)
+#define KERNEL_VM_SIZE (KERNEL_VM_TOP - KERNEL_VM_BASE)
+
+/*
+ * BCM53xx ARM Peripherals. Their physical address would live in the user
+ * address space, so we can't map 1:1 VA:PA. So shove them just after the
+ * top of the kernel VM.
+ */
+#define KERNEL_IO_VBASE KERNEL_VM_TOP
+#define KERNEL_IO_PBASE BCM53XX_IOREG_PBASE
+#define KERNEL_IO_VSIZE BCM53XX_IO_SIZE
+
+#endif /* _EVBARM_BCM53XX_PLATFORM_H */
Index: src/sys/arch/evbarm/conf/BCM5301X
diff -u /dev/null src/sys/arch/evbarm/conf/BCM5301X:1.1
--- /dev/null Sat Sep 1 00:15:11 2012
+++ src/sys/arch/evbarm/conf/BCM5301X Sat Sep 1 00:15:11 2012
@@ -0,0 +1,262 @@
+#
+# $NetBSD: BCM5301X,v 1.1 2012/09/01 00:15:11 matt Exp $
+#
+# BCM5301X -- Broadcom BCM5301X Eval Board Kernel
+#
+
+include "arch/evbarm/conf/std.bcm53xx"
+
+# estimated number of users
+
+maxusers 32
+
+# Standard system options
+
+options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
+#options NTP # NTP phase/frequency locked loop
+
+# CPU options
+
+#makeoptions DEFCOPTS="-O0"
+#options UVMHIST,UVMHIST_PRINT,A9WDT_PERIOD_DEFAULT=30
+options BCM53XX_CONSOLE_EARLY
+#options MULTIPROCESSOR
+options CPU_CORTEXA9
+#options FPU_VFP
+options BCM5301
+options PMAPCOUNTERS
+
+# Architecture options
+
+# File systems
+
+file-system FFS # UFS
+#file-system LFS # log-structured file system
+file-system MFS # memory file system
+file-system NFS # Network file system
+#file-system ADOSFS # AmigaDOS-compatible file system
+#file-system EXT2FS # second extended file system (linux)
+file-system CD9660 # ISO 9660 + Rock Ridge file system
+file-system MSDOSFS # MS-DOS file system
+#file-system FDESC # /dev/fd
+file-system KERNFS # /kern
+#file-system NULLFS # loopback file system
+#file-system PROCFS # /proc
+#file-system UMAPFS # NULLFS + uid and gid remapping
+#file-system UNION # union file system
+file-system TMPFS # memory file system
+file-system PTYFS # /dev/pts/N support
+
+# File system options
+#options QUOTA # legacy UFS quotas
+#options QUOTA2 # new, in-filesystem UFS quotas
+#options FFS_EI # FFS Endian Independent support
+#options NFSSERVER
+options WAPBL # File system journaling support
+#options FFS_NO_SNAPSHOT # No FFS snapshot support
+
+# Networking options
+
+#options GATEWAY # packet forwarding
+options INET # IP + ICMP + TCP + UDP
+options INET6 # IPV6
+#options IPSEC # IP security
+#options IPSEC_ESP # IP security (encryption part; define w/ IPSEC)
+#options IPSEC_NAT_T # IPsec NAT traversal (NAT-T)
+#options IPSEC_DEBUG # debug for IP security
+#options MROUTING # IP multicast routing
+#options PIM # Protocol Independent Multicast
+#options NS # XNS
+#options NSIP # XNS tunneling over IP
+#options ISO,TPIP # OSI
+#options EON # OSI tunneling over IP
+#options CCITT,LLC,HDLC # X.25
+#options NETATALK # AppleTalk networking
+#options PFIL_HOOKS # pfil(9) packet filter hooks
+#options PPP_BSDCOMP # BSD-Compress compression support for PPP
+#options PPP_DEFLATE # Deflate compression support for PPP
+#options PPP_FILTER # Active filter support for PPP (requires bpf)
+#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
+
+options NFS_BOOT_BOOTP
+options NFS_BOOT_DHCP
+#options NFS_BOOT_BOOTSTATIC
+#options NFS_BOOTSTATIC_MYIP="\"192.168.1.4\""
+#options NFS_BOOTSTATIC_GWIP="\"192.168.1.1\""
+#options NFS_BOOTSTATIC_MASK="\"255.255.255.0\""
+#options NFS_BOOTSTATIC_SERVADDR="\"192.168.1.1\""
+#options NFS_BOOTSTATIC_SERVER="\"192.168.1.1:/nfs/sdp2430\""
+
+options NFS_BOOT_RWSIZE=1024
+
+# Compatibility options
+
+#options COMPAT_43 # 4.3BSD compatibility.
+options COMPAT_50 # NetBSD 5.0 compatibility.
+options COMPAT_40 # NetBSD 4.0 compatibility.
+options COMPAT_30 # NetBSD 3.0 compatibility.
+#options COMPAT_20 # NetBSD 2.0 compatibility.
+#options COMPAT_16 # NetBSD 1.6 compatibility.
+#options COMPAT_15 # NetBSD 1.5 compatibility.
+#options COMPAT_14 # NetBSD 1.4 compatibility.
+#options COMPAT_13 # NetBSD 1.3 compatibility.
+#options COMPAT_12 # NetBSD 1.2 compatibility.
+#options COMPAT_11 # NetBSD 1.1 compatibility.
+#options COMPAT_10 # NetBSD 1.0 compatibility.
+#options COMPAT_09 # NetBSD 0.9 compatibility.
+#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
+#options COMPAT_BSDPTY # /dev/[pt]ty?? ptys.
+
+# Shared memory options
+
+options SYSVMSG # System V-like message queues
+options SYSVSEM # System V-like semaphores
+options SYSVSHM # System V-like memory sharing
+
+# Device options
+
+#options MEMORY_DISK_HOOKS # boottime setup of ramdisk
+#options MEMORY_DISK_ROOT_SIZE=8192 # Size in blocks
+#options MEMORY_DISK_DYNAMIC
+#options MINIROOTSIZE=1000 # Size in blocks
+#options MEMORY_DISK_IS_ROOT # use memory disk as root
+
+# Miscellaneous kernel options
+options KTRACE # system call tracing, a la ktrace(1)
+#options KMEMSTATS # kernel memory statistics
+options RNDVERBOSE # Verbose rnd messages
+#options SCSIVERBOSE # Verbose SCSI errors
+#options MIIVERBOSE # Verbose MII autoconfuration messages
+#options DDB_KEYCODE=0x40
+#options USERCONF # userconf(4) support
+#options PIPE_SOCKETPAIR # smaller, but slower pipe(2)
+
+# Development and Debugging options
+
+#options PERFCTRS # performance counters
+options DIAGNOSTIC # internally consistency checks
+options DEBUG
+#options LOCKDEBUG # Enable lock debugging
+#options PMAP_DEBUG # Enable pmap_debug_level code
+#options IPKDB # remote kernel debugging
+#options VERBOSE_INIT_ARM # verbose bootstraping messages
+options DDB # in-kernel debugger
+options DDB_ONPANIC=1
+options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
+options DDB_COMMANDONENTER="t; show event"
+options DB_MAX_LINE=INT_MAX
+#options KGDB
+makeoptions DEBUG="-g" # compile full symbol table
+options SYMTAB_SPACE=530000
+
+## USB Debugging options
+options USB_DEBUG
+options EHCI_DEBUG
+options OHCI_DEBUG
+options UHUB_DEBUG
+
+
+# Valid options for BOOT_ARGS:
+# single Boot to single user only
+# kdb Give control to kernel debugger
+# ask Ask for file name to reboot from
+# pmapdebug=<n> If PMAP_DEBUG, set pmap_debug_level to <n>
+# memorydisk=<n> Set memorydisk size to <n> KB
+# quiet Show aprint_naive output
+# verbose Show aprint_normal and aprint_verbose output
+options BOOT_ARGS="\"\""
+
+config netbsd root on ? type ?
+
+# The main bus device
+mainbus0 at root
+
+# The boot cpu
+cpu0 at mainbus?
+#cpu* at mainbus?
+
+# The MPCore interrupt controller and global timer
+armperiph0 at mainbus? # A9 On-Chip Peripherals
+armgic0 at armperiph? # ARM Generic Interrupt Controller
+a9tmr0 at armperiph? # A9 Global Timer
+a9wdt0 at armperiph? flags 1 # A9 Watchdog Timer
+
+# ChipCommonA Peripherals
+bcmcca0 at mainbus? # ChipCommonA
+#options CONADDR=0x18000300, CONSPEED=115200
+com0 at bcmcca? channel 0
+com* at bcmcca? channel 1
+
+# ChipCommonB Peripherals
+bcmccb0 at mainbus? # ChipCommonB
+bcmpax* at bcmccb? port ?
+pci* at bcmpax?
+
+bcmmdio0 at bcmccb0
+bcmeth* at bcmccb? port ?
+
+# SDHC controllers
+sdhc0 at bcmccb0
+sdmmc* at sdhc? # SD/MMC bus
+ld* at sdmmc?
+
+# Random Number Generator
+bcmrng0 at bcmccb0
+
+# NAND controller
+#bcmnand0 at bcmccb0
+
+# NAND layer
+#nand0 at nandbus?
+
+# use the bad block table
+#options NAND_BBT
+
+# Define flash partitions for board
+#flash0 at nand0 offset 0x000000 size 0x080000 readonly 1 # X-Loader
+#flash1 at nand0 offset 0x080000 size 0x1e0000 readonly 1 # U-Boot
+#flash2 at nand0 offset 0x260000 size 0x020000 readonly 1 # UB Env
+#flash3 at nand0 offset 0x280000 size 0x400000 # kernel
+#flash4 at nand0 offset 0x680000 size 0 # filesystem
+
+# I2C Controller
+bcmi2c0 at bcmccb0
+iic* at bcmi2c?
+
+# Watchdog timers
+#bcmwdt* at bcmccb0
+
+# On-board USB
+bcmusb* at bcmccb0
+ohci* at bcmusb0
+usb* at ohci?
+ehci* at bcmusb0
+usb* at ehci?
+uhub* at usb?
+uhub* at uhub? port ?
+umass* at uhub? port ? configuration ? interface ?
+scsibus* at scsi?
+sd* at scsibus? target ? lun ?
+wd* at umass?
+
+axe* at uhub? port ? configuration ? interface ?
+
+# Hardware clocking and power management
+
+# Pseudo-Devices
+
+# disk/mass storage pseudo-devices
+#pseudo-device md # memory disk device (ramdisk)
+#pseudo-device vnd # disk-like interface to files
+#pseudo-device fss # file system snapshot device
+
+# network pseudo-devices
+pseudo-device bpfilter # Berkeley packet filter
+pseudo-device loop # network loopback
+#pseudo-device kttcp # network loopback
+
+# miscellaneous pseudo-devices
+pseudo-device pty # pseudo-terminals
+#options RND_COM
+#pseudo-device clockctl # user control of clock subsystem
+pseudo-device ksyms # /dev/ksyms
Index: src/sys/arch/evbarm/conf/files.bcm53xx
diff -u /dev/null src/sys/arch/evbarm/conf/files.bcm53xx:1.1
--- /dev/null Sat Sep 1 00:15:11 2012
+++ src/sys/arch/evbarm/conf/files.bcm53xx Sat Sep 1 00:15:11 2012
@@ -0,0 +1,12 @@
+# $NetBSD: files.bcm53xx,v 1.1 2012/09/01 00:15:11 matt Exp $
+#
+# BCM5301X evaluation board configuration info
+#
+
+file arch/evbarm/bcm53xx/bcm53xx_machdep.c
+
+# Kernel boot arguments
+defparam opt_machdep.h BOOT_ARGS
+
+# CPU support and integrated peripherals
+include "arch/arm/broadcom/files.bcm53xx"
Index: src/sys/arch/evbarm/conf/mk.bcm53xx
diff -u /dev/null src/sys/arch/evbarm/conf/mk.bcm53xx:1.1
--- /dev/null Sat Sep 1 00:15:11 2012
+++ src/sys/arch/evbarm/conf/mk.bcm53xx Sat Sep 1 00:15:11 2012
@@ -0,0 +1,34 @@
+# $NetBSD: mk.bcm53xx,v 1.1 2012/09/01 00:15:11 matt Exp $
+CPPFLAGS+= -mcpu=cortex-a9
+
+SYSTEM_FIRST_OBJ= bcm53xx_start.o
+SYSTEM_FIRST_SFILE= ${THISARM}/bcm53xx/bcm53xx_start.S
+
+GENASSYM_EXTRAS+= ${THISARM}/bcm53xx/genassym.cf
+
+_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
+
+MKUBOOTIMAGEARGS= -A arm -T kernel
+MKUBOOTIMAGEARGS+= -a $(LOADADDRESS) -e $(LOADADDRESS)
+MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
+MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
+MKUBOOTIMAGEARGS_GZ= ${MKUBOOTIMAGEARGS} -C gz
+
+KERNEL_BASE_PHYS=$(LOADADDRESS)
+KERNEL_BASE_VIRT=$(LOADADDRESS)
+
+SYSTEM_LD_TAIL_EXTRA+=; \
+ echo ${OBJCOPY} -S -O binary $@ [email protected]; \
+ ${OBJCOPY} -S -O binary $@ [email protected]; \
+ echo ${TOOL_GZIP} -9c [email protected] > [email protected]; \
+ ${TOOL_GZIP} -9c [email protected] > [email protected]; \
+ echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} [email protected] [email protected]; \
+ ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} [email protected] [email protected]; \
+ echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} [email protected] [email protected]; \
+ ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} [email protected] [email protected]; \
+ echo
+
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.ub@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin.gz@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.gz.ub@}
Index: src/sys/arch/evbarm/conf/std.bcm53xx
diff -u /dev/null src/sys/arch/evbarm/conf/std.bcm53xx:1.1
--- /dev/null Sat Sep 1 00:15:11 2012
+++ src/sys/arch/evbarm/conf/std.bcm53xx Sat Sep 1 00:15:11 2012
@@ -0,0 +1,30 @@
+# $NetBSD: std.bcm53xx,v 1.1 2012/09/01 00:15:11 matt Exp $
+#
+# standard NetBSD/evbarm for BEAGLEBAORD options
+
+machine evbarm arm
+include "conf/std" # MI standard options
+
+# Pull in BCM53xx config definitions.
+include "arch/evbarm/conf/files.bcm53xx"
+
+options EXEC_ELF32
+options EXEC_SCRIPT
+
+# To support easy transit to ../arch/arm/arm32
+options COM_TOLERANCE=40
+options ARM32
+options CORTEX_PMC
+options CORTEX_PMC_CCNT_HZ=500000000
+options __HAVE_FAST_SOFTINTS # should be in types.h
+options __HAVE_CPU_UAREA_ALLOC_IDLELWP
+options TPIDRPRW_IS_CURCPU
+options KERNEL_BASE_EXT=0x80000000
+options EVBARM_BOARDTYPE="bcm53xx"
+
+makeoptions LOADADDRESS="0x80100000"
+makeoptions BOARDMKFRAG="${THISARM}/conf/mk.bcm53xx"
+makeoptions CPPFLAGS+="-I$S/../../../include"
+
+options ARM_INTR_IMPL="<arch/arm/broadcom/bcm53xx_intr.h>"
+options ARM_GENERIC_TODR
