Module Name: src
Committed By: matt
Date: Sun Sep 2 16:55:10 UTC 2012
Modified Files:
src/sys/arch/arm/cortex: armperiph.c files.cortex
Added Files:
src/sys/arch/arm/cortex: pl310.c pl310_reg.h
Log Message:
Add driver to attach ARM PL210 L2 Cache Controller
arml2cc0 at armperiph0: ARM PL310 L2 r3p2 Cache Controller
arml2cc0: 256KB/32B 16-way L2 Unified cache
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/armperiph.c \
src/sys/arch/arm/cortex/files.cortex
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/cortex/pl310.c \
src/sys/arch/arm/cortex/pl310_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/armperiph.c
diff -u src/sys/arch/arm/cortex/armperiph.c:1.1 src/sys/arch/arm/cortex/armperiph.c:1.2
--- src/sys/arch/arm/cortex/armperiph.c:1.1 Sat Sep 1 00:03:14 2012
+++ src/sys/arch/arm/cortex/armperiph.c Sun Sep 2 16:55:10 2012
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.1 2012/09/01 00:03:14 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.2 2012/09/02 16:55:10 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -52,7 +52,7 @@ struct armperiph_softc {
bus_space_handle_t sc_memh;
};
-#ifdef CPU_CORTEXA9
+#ifdef CPU_CORTEXA5
static const char * const a5_devices[] = {
"armscu", "armgic", NULL
};
@@ -66,7 +66,7 @@ static const char * const a7_devices[] =
#ifdef CPU_CORTEXA9
static const char * const a9_devices[] = {
- "armscu", "armgic", "a9tmr", "a9wdt", NULL
+ "armscu", "arml2cc", "armgic", "a9tmr", "a9wdt", NULL
};
#endif
@@ -82,7 +82,7 @@ static const struct mpcore_config {
{ a7_devices, 0x410fc070, 32768 },
#endif
#ifdef CPU_CORTEXA9
- { a9_devices, 0x410fc090, 8192 },
+ { a9_devices, 0x410fc090, 3*4096 },
#endif
#ifdef CPU_CORTEXA15
{ a15_devices, 0x410fc0f0, 32768 },
Index: src/sys/arch/arm/cortex/files.cortex
diff -u src/sys/arch/arm/cortex/files.cortex:1.1 src/sys/arch/arm/cortex/files.cortex:1.2
--- src/sys/arch/arm/cortex/files.cortex:1.1 Sat Sep 1 00:03:14 2012
+++ src/sys/arch/arm/cortex/files.cortex Sun Sep 2 16:55:10 2012
@@ -1,4 +1,4 @@
-# $NetBSD: files.cortex,v 1.1 2012/09/01 00:03:14 matt Exp $
+# $NetBSD: files.cortex,v 1.2 2012/09/02 16:55:10 matt Exp $
device armperiph {}
attach armperiph at mainbus
@@ -9,6 +9,11 @@ device armgic: pic, pic_splfuncs
attach armgic at armperiph
file arch/arm/cortex/gic.c armgic
+# ARM PL310 L2 Cache Controller(initially on Cortex-A9)
+device arml2cc
+attach arml2cc at armperiph
+file arch/arm/cortex/pl310.c arml2cc
+
# A9 MPCore Global Timer
device a9tmr
attach a9tmr at armperiph
Added files:
Index: src/sys/arch/arm/cortex/pl310.c
diff -u /dev/null src/sys/arch/arm/cortex/pl310.c:1.1
--- /dev/null Sun Sep 2 16:55:10 2012
+++ src/sys/arch/arm/cortex/pl310.c Sun Sep 2 16:55:10 2012
@@ -0,0 +1,160 @@
+/* $NetBSD: pl310.c,v 1.1 2012/09/02 16:55:10 matt Exp $ */
+
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.1 2012/09/02 16:55:10 matt Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+
+#include <arm/cortex/mpcore_var.h>
+#include <arm/cortex/pl310_reg.h>
+
+static int arml2cc_match(device_t, cfdata_t, void *);
+static void arml2cc_attach(device_t, device_t, void *);
+
+#define L2CC_BASE 0x2000
+#define L2CC_SIZE 0x1000
+
+struct arml2cc_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_memt;
+ bus_space_handle_t sc_memh;
+};
+
+CFATTACH_DECL_NEW(arml2cc, sizeof(struct arml2cc_softc),
+ arml2cc_match, arml2cc_attach, NULL, NULL);
+
+static bool attached;
+
+static inline uint32_t
+arml2cc_read_4(struct arml2cc_softc *sc, bus_size_t o)
+{
+ return bus_space_read_4(sc->sc_memt, sc->sc_memh, o);
+}
+
+static inline void
+arml2cc_write_4(struct arml2cc_softc *sc, bus_size_t o, uint32_t v)
+{
+ bus_space_write_4(sc->sc_memt, sc->sc_memh, o, v);
+}
+
+
+/* ARGSUSED */
+static int
+arml2cc_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct mpcore_attach_args * const mpcaa = aux;
+
+ if (attached)
+ return 0;
+
+ if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid))
+ return 0;
+
+ if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0)
+ return 0;
+
+ /*
+ * This isn't present on UP A9s (since CBAR isn't present).
+ */
+ uint32_t mpidr = armreg_mpidr_read();
+ if (mpidr == 0 || (mpidr & MPIDR_U))
+ return 0;
+
+ return 1;
+}
+
+static const struct {
+ uint8_t rev;
+ uint8_t str[7];
+} pl310_revs[] = {
+ { 0, " r0p0" },
+ { 2, " r1p0" },
+ { 4, " r2p0" },
+ { 5, " r3p0" },
+ { 6, " r3p1" },
+ { 8, " r3p2" },
+ { 9, " r3p3" },
+};
+
+static void
+arml2cc_attach(device_t parent, device_t self, void *aux)
+{
+ struct arml2cc_softc * const sc = device_private(self);
+ struct mpcore_attach_args * const mpcaa = aux;
+
+ sc->sc_dev = self;
+ sc->sc_memt = mpcaa->mpcaa_memt;
+
+ bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
+ L2CC_BASE, L2CC_SIZE, &sc->sc_memh);
+
+ uint32_t id = arml2cc_read_4(sc, L2C_CACHE_ID);
+ u_int rev = __SHIFTOUT(id, CACHE_ID_REV);
+
+ const char *revstr = "";
+ for (size_t i = 0; i < __arraycount(pl310_revs); i++) {
+ if (rev == pl310_revs[i].rev) {
+ revstr = pl310_revs[i].str;
+ break;
+ }
+ }
+
+ aprint_naive("\n");
+ aprint_normal(": ARM PL310 L2%s Cache Controller\n", revstr);
+
+ uint32_t cfg = arml2cc_read_4(sc, L2C_CACHE_TYPE);
+ //u_int cfg_ctype = __SHIFTOUT(cfg, CACHE_TYPE_CTYPE);
+ bool cfg_harvard_p = __SHIFTOUT(cfg, CACHE_TYPE_HARVARD) != 0;
+ u_int cfg_dsize = __SHIFTOUT(cfg, CACHE_TYPE_DSIZE);
+ u_int d_waysize = 8192 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xWAYSIZE);
+ u_int d_assoc = 8 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xASSOC);
+ u_int d_linesize = 32 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xLINESIZE);
+ u_int d_size = d_waysize * d_assoc;
+
+ if (cfg_harvard_p) {
+ u_int cfg_isize = __SHIFTOUT(cfg, CACHE_TYPE_ISIZE);
+ u_int i_waysize = 8192 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xWAYSIZE);
+ u_int i_assoc = 8 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xASSOC);
+ u_int i_linesize = 32 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xLINESIZE);
+ u_int i_size = i_waysize * i_assoc;
+
+ aprint_normal_dev(self, "%uKB/%uB %u-way L2 Instruction cache\n",
+ i_size / 1024, i_linesize, i_assoc);
+ }
+
+ aprint_normal_dev(self, "%uKB/%uB %u-way L2 %s cache\n",
+ d_size / 1024, d_linesize, d_assoc,
+ (cfg_harvard_p ? "Data" : "Unified"));
+}
Index: src/sys/arch/arm/cortex/pl310_reg.h
diff -u /dev/null src/sys/arch/arm/cortex/pl310_reg.h:1.1
--- /dev/null Sun Sep 2 16:55:10 2012
+++ src/sys/arch/arm/cortex/pl310_reg.h Sun Sep 2 16:55:10 2012
@@ -0,0 +1,108 @@
+/* $NetBSD: pl310_reg.h,v 1.1 2012/09/02 16:55:10 matt Exp $ */
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_CORTEX_PL310_REG_H_
+#define _ARM_CORTEX_PL310_REG_H_
+
+/*
+ * ARM PL310 L2 Cache Controller
+ * Used by Cortex cores
+ */
+
+#define L2C_CACHE_ID 0x000
+#define CACHE_ID_IMPL __BITS(31,24)
+#define CACHE_ID_ID __BITS(15,10)
+#define CACHE_ID_PART __BITS(9,6)
+#define CACHE_ID_PART_PL310 3
+#define CACHE_ID_REV __BITS(5,0)
+#define CACHE_ID_REV_R3P3 9
+#define CACHE_ID_REV_R3P2 8
+#define L2C_CACHE_TYPE 0x004
+#define CACHE_TYPE_DATA_BANKING __BIT(31)
+#define CACHE_TYPE_CTYPE __BITS(28,25)
+#define CACHE_TYPE_HARVARD __BIT(24)
+#define CACHE_TYPE_DSIZE __BITS(23,12)
+#define CACHE_TYPE_ISIZE __BITS(11,0)
+#define CACHE_TYPE_xWAYSIZE __BITS(10,8)
+#define CACHE_TYPE_xASSOC __BIT(6)
+#define CACHE_TYPE_xLINESIZE __BITS(5,0)
+
+#define L2C_CTL 0x100
+#define L2C_AUXCTL 0x104
+#define L2C_TAGRAM_CTL 0x108
+#define L2C_DATARAM_CTL 0x10c
+
+#define L2C_EV_CTR_CTL 0x200
+#define L2C_EV_CTR1_CTL 0x204
+#define L2C_EV_CTR0_CTL 0x208
+#define L2C_EV_CTR1 0x20c
+#define L2C_EV_CTR0 0x210
+#define L2C_INT_MASK 0x214
+#define L2C_INT_MASK_STS 0x218
+#define L2C_INT_RAW_STS 0x21c
+#define L2C_INT_CLR 0x220
+
+#define L2C_CACHE_SYNC 0x730
+#define L2C_INV_PA 0x770
+#define L2C_INV_WAY 0x77c
+#define L2C_CLEAN_PA 0x7b0
+#define L2C_CLEAN_INDEX 0x7b8
+#define L2C_CLEAN_WAY 0x7bc
+#define L2C_CLEAN_INV_PA 0x7f0
+#define L2C_CLEAN_INV_INDEX 0x7f8
+#define L2C_CLEAN_INV_WAY 0x7fc
+
+#define L2C_D_LOCKDOWN0 0x900
+#define L2C_I_LOCKDOWN0 0x904
+#define L2C_D_LOCKDOWN1 0x908
+#define L2C_I_LOCKDOWN1 0x90c
+#define L2C_D_LOCKDOWN2 0x910
+#define L2C_I_LOCKDOWN2 0x914
+#define L2C_D_LOCKDOWN3 0x918
+#define L2C_I_LOCKDOWN3 0x91c
+#define L2C_D_LOCKDOWN4 0x920
+#define L2C_I_LOCKDOWN4 0x924
+#define L2C_D_LOCKDOWN5 0x928
+#define L2C_I_LOCKDOWN5 0x92c
+#define L2C_D_LOCKDOWN6 0x930
+#define L2C_I_LOCKDOWN6 0x934
+#define L2C_D_LOCKDOWN7 0x938
+#define L2C_I_LOCKDOWN7 0x93c
+#define L2C_LOCK_LINE_EN 0x950
+#define L2C_UNLOCK_WAY 0x954
+
+#define L2C_ADDR_FILTER_START 0xc00
+#define L2C_ADDR_FILTER_END 0xc04
+
+#define L2C_DEBUG_CTL 0xf40
+#define L2C_PREFETCH_CTL 0xf60
+#define L2C_POWER_CTL 0xf80
+
+#endif /* _ARM_CORTEX_PL310_REG_H_ */
