Module Name: src
Committed By: matt
Date: Wed Sep 26 18:18:08 UTC 2012
Modified Files:
src/sys/arch/arm/arm32: pmap.c
Log Message:
If we get a fault we shouldn't have, set pmap_needs_pte_sync and retry.
To generate a diff of this commit:
cvs rdiff -u -r1.237 -r1.238 src/sys/arch/arm/arm32/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/pmap.c
diff -u src/sys/arch/arm/arm32/pmap.c:1.237 src/sys/arch/arm/arm32/pmap.c:1.238
--- src/sys/arch/arm/arm32/pmap.c:1.237 Sat Sep 22 00:33:37 2012
+++ src/sys/arch/arm/arm32/pmap.c Wed Sep 26 18:18:08 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.237 2012/09/22 00:33:37 matt Exp $ */
+/* $NetBSD: pmap.c,v 1.238 2012/09/26 18:18:08 matt Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -212,7 +212,7 @@
#include <arm/cpuconf.h>
#include <arm/arm32/katelib.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.237 2012/09/22 00:33:37 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.238 2012/09/26 18:18:08 matt Exp $");
#ifdef PMAP_DEBUG
@@ -4002,6 +4002,17 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va,
}
#endif /* CPU_SA110 */
+ /*
+ * If 'rv == 0' at this point, it generally indicates that there is a
+ * stale TLB entry for the faulting address. That might be due to a
+ * wrong setting of pmap_needs_pte_sync. So set it and retry.
+ */
+ if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1
+ && pmap_needs_pte_sync == 0) {
+ pmap_needs_pte_sync = 1;
+ rv = 1;
+ }
+
#ifdef DEBUG
/*
* If 'rv == 0' at this point, it generally indicates that there is a
