Module Name: src
Committed By: matt
Date: Wed Oct 3 19:18:41 UTC 2012
Modified Files:
src/sys/arch/arm/broadcom: bcm53xx_board.c bcm53xx_ccb.c bcm53xx_reg.h
bcm53xx_var.h
Log Message:
Add code to init the SRAB (the switch robot). Don't configure eth3 by default.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/broadcom/bcm53xx_board.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/broadcom/bcm53xx_ccb.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/broadcom/bcm53xx_reg.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/broadcom/bcm53xx_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/broadcom/bcm53xx_board.c
diff -u src/sys/arch/arm/broadcom/bcm53xx_board.c:1.3 src/sys/arch/arm/broadcom/bcm53xx_board.c:1.4
--- src/sys/arch/arm/broadcom/bcm53xx_board.c:1.3 Tue Sep 18 05:47:27 2012
+++ src/sys/arch/arm/broadcom/bcm53xx_board.c Wed Oct 3 19:18:40 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm53xx_board.c,v 1.3 2012/09/18 05:47:27 matt Exp $ */
+/* $NetBSD: bcm53xx_board.c,v 1.4 2012/10/03 19:18:40 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.3 2012/09/18 05:47:27 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.4 2012/10/03 19:18:40 matt Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -43,10 +43,14 @@ __KERNEL_RCSID(1, "$NetBSD: bcm53xx_boar
#include <prop/proplib.h>
+#include <net/if.h>
+#include <net/if_ether.h>
+
#define CRU_PRIVATE
#define DDR_PRIVATE
#define DMU_PRIVATE
#define ARMCORE_PRIVATE
+#define SRAB_PRIVATE
#include <arm/cortex/a9tmr_var.h>
#include <arm/cortex/pl310_var.h>
@@ -519,5 +523,122 @@ bcm53xx_device_register(device_t self, v
prop_dictionary_set_uint32(dict, "frequency",
clk_info.clk_cpu / 2);
return;
- }
+ }
+
+ if (device_is_a(self, "bcmeth")) {
+ const struct bcmccb_attach_args * const ccbaa = aux;
+ const uint8_t enaddr[ETHER_ADDR_LEN] = {
+ 0x00, 0x01, 0x02, 0x03, 0x04,
+ 0x05 + 2 * ccbaa->ccbaa_loc.loc_port,
+ };
+ prop_data_t pd = prop_data_create_data(enaddr, ETHER_ADDR_LEN);
+ KASSERT(pd != NULL);
+ if (prop_dictionary_set(device_properties(self), "mac-address", pd) == false) {
+ printf("WARNING: Unable to set mac-address property for %s\n", device_xname(self));
+ }
+ prop_object_release(pd);
+ }
+}
+
+static kmutex_t srab_lock __cacheline_aligned;
+
+void
+bcm53xx_srab_init(void)
+{
+ mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM);
+
+ bcm53xx_srab_write_4(0x0079, 0x90); // reset switch
+ for (u_int port = 0; port < 8; port++) {
+ /* per port control: no stp */
+ bcm53xx_srab_write_4(port, 0x00);
+ }
+ bcm53xx_srab_write_4(0x0008, 0x1c); // IMP port (enab UC/MC/BC)
+ bcm53xx_srab_write_4(0x000e, 0xbb); // IMP port force-link 1G
+ bcm53xx_srab_write_4(0x005d, 0x7b); // port5 force-link 1G
+ bcm53xx_srab_write_4(0x005f, 0x7b); // port7 force-link 1G
+ bcm53xx_srab_write_4(0x000b, 0x7); // management mode
+ bcm53xx_srab_write_4(0x0203, 0x0); // disable BRCM tag
+ bcm53xx_srab_write_4(0x0200, 0x80); // enable IMP=port8
+}
+
+static inline void
+bcm53xx_srab_busywait(bus_space_tag_t bst, bus_space_handle_t bsh)
+{
+ while (bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT) & SRA_GORDYN) {
+ delay(10);
+ }
+}
+
+uint32_t
+bcm53xx_srab_read_4(u_int pageoffset)
+{
+ bus_space_tag_t bst = bcm53xx_ioreg_bst;
+ bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
+ uint32_t rv;
+
+ mutex_spin_enter(&srab_lock);
+
+ bcm53xx_srab_busywait(bst, bsh);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
+ __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN);
+ bcm53xx_srab_busywait(bst, bsh);
+ rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL);
+
+ mutex_spin_exit(&srab_lock);
+ return rv;
+}
+
+uint64_t
+bcm53xx_srab_read_8(u_int pageoffset)
+{
+ bus_space_tag_t bst = bcm53xx_ioreg_bst;
+ bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
+ uint64_t rv;
+
+ mutex_spin_enter(&srab_lock);
+
+ bcm53xx_srab_busywait(bst, bsh);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
+ __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN);
+ bcm53xx_srab_busywait(bst, bsh);
+ rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDH);
+ rv <<= 32;
+ rv |= bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL);
+
+ mutex_spin_exit(&srab_lock);
+ return rv;
+}
+
+void
+bcm53xx_srab_write_4(u_int pageoffset, uint32_t val)
+{
+ bus_space_tag_t bst = bcm53xx_ioreg_bst;
+ bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
+
+ mutex_spin_enter(&srab_lock);
+
+ bcm53xx_srab_busywait(bst, bsh);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
+ __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN);
+ bcm53xx_srab_busywait(bst, bsh);
+
+ mutex_spin_exit(&srab_lock);
+}
+
+void
+bcm53xx_srab_write_8(u_int pageoffset, uint64_t val)
+{
+ bus_space_tag_t bst = bcm53xx_ioreg_bst;
+ bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
+
+ mutex_spin_enter(&srab_lock);
+
+ bcm53xx_srab_busywait(bst, bsh);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDH, val >> 32);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
+ __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN);
+ bcm53xx_srab_busywait(bst, bsh);
+ mutex_spin_exit(&srab_lock);
}
Index: src/sys/arch/arm/broadcom/bcm53xx_ccb.c
diff -u src/sys/arch/arm/broadcom/bcm53xx_ccb.c:1.2 src/sys/arch/arm/broadcom/bcm53xx_ccb.c:1.3
--- src/sys/arch/arm/broadcom/bcm53xx_ccb.c:1.2 Sat Sep 22 01:46:57 2012
+++ src/sys/arch/arm/broadcom/bcm53xx_ccb.c Wed Oct 3 19:18:41 2012
@@ -34,7 +34,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_ccb.c,v 1.2 2012/09/22 01:46:57 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_ccb.c,v 1.3 2012/10/03 19:18:41 matt Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -108,7 +108,7 @@ static const struct bcm_locators bcmccb_
{ "bcmeth", GMAC0_BASE, 0x1000, 0, 1, { IRQ_GMAC0 }, },
{ "bcmeth", GMAC1_BASE, 0x1000, 1, 1, { IRQ_GMAC1 }, },
{ "bcmeth", GMAC2_BASE, 0x1000, 2, 1, { IRQ_GMAC2 }, },
- { "bcmeth", GMAC3_BASE, 0x1000, 3, 1, { IRQ_GMAC3 }, },
+ // { "bcmeth", GMAC3_BASE, 0x1000, 3, 1, { IRQ_GMAC3 }, },
{ "bcmpax", PCIE0_BASE, 0x1000, 0, 6, { IRQ_PCIE_INT0 }, },
{ "bcmpax", PCIE1_BASE, 0x1000, 1, 6, { IRQ_PCIE_INT1 }, },
{ "bcmpax", PCIE2_BASE, 0x1000, 2, 6, { IRQ_PCIE_INT2 }, },
@@ -159,6 +159,8 @@ bcmccb_mainbus_attach(device_t parent, d
aprint_naive("\n");
aprint_normal("\n");
+ bcm53xx_srab_init(); // need this for ethernet.
+
for (size_t i = 0; i < __arraycount(bcmccb_locators); i++) {
struct bcmccb_attach_args ccbaa = {
.ccbaa_ccb_bst = sc->sc_bst,
Index: src/sys/arch/arm/broadcom/bcm53xx_reg.h
diff -u src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.5 src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.6
--- src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.5 Sat Sep 22 01:46:31 2012
+++ src/sys/arch/arm/broadcom/bcm53xx_reg.h Wed Oct 3 19:18:41 2012
@@ -213,6 +213,20 @@
#define TIMER_FREQ BCM53XX_REF_CLK
+#ifdef SRAB_PRIVATE
+#define SRAB_CMDSTAT 0x002c
+#define SRA_PAGE __BITS(31,24)
+#define SRA_OFFSET __BITS(23,16)
+#define SRA_PAGEOFFSET __BITS(31,16)
+#define SRA_RST __BIT(2)
+#define SRA_WRITE __BIT(1)
+#define SRA_GORDYN __BIT(0)
+#define SRAB_WDH 0x0030
+#define SRAB_WDL 0x0034
+#define SRAB_RDH 0x0038
+#define SRAB_RDL 0x003c
+#endif
+
#ifdef MII_PRIVATE
#define MII_INTERNAL 0x0038003 /* internal phy bitmask */
#define MIIMGT 0x000
@@ -313,17 +327,17 @@
#define CRU_GPIO_PULL_DOWN 0x11e0
#define CRU_STRAPS_CONTROL 0x12a0
-#define STRAP_BOOT_DEV __BITS(17,16)
-#define STRAP_NAND_TYPE __BITS(15,12)
-#define STRAP_NAND_PAGE __BITS(11,10)
-#define STRAP_DDR3 __BIT(9)
-#define STRAP_P5_VOLT_15 __BIT(8)
-#define STRAP_P5_MODE __BITS(7,6)
-#define STRAP_PCIE0_MODE __BIT(5)
-#define STRAP_USB3_SEL __BIT(4)
-#define STRAP_EX_EXTCLK __BIT(3)
-#define STRAP_HW_FWDG_EN __BIT(2)
-#define STRAP_LED_SERIAL_MODE __BIT(1)
+#define STRAP_BOOT_DEV __BITS(17,16)
+#define STRAP_NAND_TYPE __BITS(15,12)
+#define STRAP_NAND_PAGE __BITS(11,10)
+#define STRAP_DDR3 __BIT(9)
+#define STRAP_P5_VOLT_15 __BIT(8)
+#define STRAP_P5_MODE __BITS(7,6)
+#define STRAP_PCIE0_MODE __BIT(5)
+#define STRAP_USB3_SEL __BIT(4)
+#define STRAP_EX_EXTCLK __BIT(3)
+#define STRAP_HW_FWDG_EN __BIT(2)
+#define STRAP_LED_SERIAL_MODE __BIT(1)
#define STRAP_BISR_BYPASS_AUTOLOAD __BIT(0)
#endif /* CRU_PRIVATE */
@@ -634,8 +648,7 @@
struct gmac_txdb {
uint32_t txdb_flags;
- uint16_t txdb_buflen;
- uint16_t txdb_addrext;
+ uint32_t txdb_buflen;
uint32_t txdb_addrlo;
uint32_t txdb_addrhi;
};
@@ -646,8 +659,7 @@ struct gmac_txdb {
struct gmac_rxdb {
uint32_t rxdb_flags;
- uint16_t rxdb_buflen;
- uint16_t rxdb_addrext;
+ uint32_t rxdb_buflen;
uint32_t rxdb_addrlo;
uint32_t rxdb_addrhi;
};
@@ -670,10 +682,46 @@ struct gmac_rxdb {
#define RXSTS_DESC_COUNT __BITS(27,24) // # of descriptors - 1
#define GMAC_DEVCONTROL 0x000
+#define ENABLE_DEL_G_TXC __BIT(21)
+#define ENABLE_DEL_G_RXC __BIT(20)
+#define TXC_DRNG __BITS(19,18)
+#define RXC_DRNG __BITS(17,16)
+#define TXQ_FLUSH __BIT(8)
+#define NWAY_AUTO_POLL_EN __BIT(7)
+#define FLOW_CTRL_MODE __BITS(6,5)
+#define MIB_RD_RESET_EN __BIT(4)
+#define RGMII_LINK_STATUS_SEL __BIT(3)
+#define CPU_FLOW_CTRL_ON __BIT(2)
+#define RXQ_OVERFLOW_CTRL_SEL __BIT(1)
+#define TXARB_STRICT_MODE __BIT(0)
#define GMAC_DEVSTATUS 0x004
#define GMAC_BISTSTATUS 0x00c
#define GMAC_INTSTATUS 0x020
#define GMAC_INTMASK 0x024
+#define TXQECCUNCORRECTED __BIT(31)
+#define TXQECCCORRECTED __BIT(30)
+#define RXQECCUNCORRECTED __BIT(29)
+#define RXQECCCORRECTED __BIT(28)
+#define XMTINT_3 __BIT(27)
+#define XMTINT_2 __BIT(26)
+#define XMTINT_1 __BIT(25)
+#define XMTINT_0 __BIT(24)
+#define RCVINT __BIT(16)
+#define XMTUF __BIT(15)
+#define RCVFIFOOF __BIT(14)
+#define RCVDESCUF __BIT(13)
+#define DESCPROTOERR __BIT(12)
+#define DATAERR __BIT(11)
+#define DESCERR __BIT(10)
+#define INT_SW_LINK_ST_CHG __BIT(8)
+#define INT_TIMEOUT __BIT(7)
+#define MIB_TX_INT __BIT(6)
+#define MIB_RX_INT __BIT(5)
+#define MDIOINT __BIT(4)
+#define NWAYLINKSTATINT __BIT(3)
+#define TXQ_FLUSH_DONEINT __BIT(2)
+#define MIB_TX_OVERFLOW __BIT(1)
+#define MIB_RX_OVERFLOW __BIT(0)
#define GMAC_GPTIMER 0x028
#define GMAC_INTRCVLAZY 0x100
@@ -697,24 +745,96 @@ struct gmac_rxdb {
#define GMAC_CLOCKCONTROLSTATUS 0x1e0
#define GMAC_POWERCONTROL 0x1e8
-#define GMAC_XMTCONTROL_0 0x200
-#define GMAC_XMTPTR_0 0x204
-#define GMAC_XMTADDR_LOW_0 0x208
-#define GMAC_XMTADDR_HIGH_0 0x20c
-#define GMAC_XMTSTATUS0_0 0x210
-#define GMAC_XMTSTATUS1_0 0x214
-#define GMAC_RCVCONTROL 0x220
+#define GMAC_XMTCONTROL 0x200
+#define XMTCTL_PREFETCH_THRESH __BITS(25,24)
+#define XMTCTL_PREFETCH_CTL __BITS(23,21)
+#define XMTCTL_BURSTLEN __BITS(20,18)
+#define XMTCTL_ADDREXT __BITS(17,16)
+#define XMTCTL_DMA_ACT_INDEX __BIT(13)
+#define XMTCTL_PARITY_DIS __BIT(11)
+#define XMTCTL_OUTSTANDING_READS __BITS(7,6)
+#define XMTCTL_BURST_ALIGN_EN __BIT(5)
+#define XMTCTL_DMA_LOOPBACK __BIT(2)
+#define XMTCTL_SUSPEND __BIT(1)
+#define XMTCTL_ENABLE __BIT(0)
+#define GMAC_XMTPTR 0x204
+#define XMT_LASTDSCR __BITS(11,4)
+#define GMAC_XMTADDR_LOW 0x208
+#define GMAC_XMTADDR_HIGH 0x20c
+#define GMAC_XMTSTATUS0 0x210
+#define XMTSTATE __BITS(31,28)
+#define XMTSTATE_DIS 0
+#define XMTSTATE_ACTIVE 1
+#define XMTSTATE_IDLE_WAIT 2
+#define XMTSTATE_STOPPED 3
+#define XMTSTATE_SUSP_PENDING 4
+#define XMT_CURRDSCR __BITS(11,4)
+#define GMAC_XMTSTATUS1 0x214
+#define XMTERR __BITS(31,28)
+#define XMT_ACTIVEDSCR __BITS(11,4)
+#define GMAC_RCVCONTROL 0x220
+#define RCVCTL_PREFETCH_THRESH __BITS(25,24)
+#define RCVCTL_PREFETCH_CTL __BITS(23,21)
+#define RCVCTL_BURSTLEN __BITS(20,18)
+#define RCVCTL_ADDREXT __BITS(17,16)
+#define RCVCTL_DMA_ACT_INDEX __BIT(13)
+#define RCVCTL_PARITY_DIS __BIT(11)
+#define RCVCTL_OFLOW_CONTINUE __BIT(10)
+#define RCVCTL_SEPRXHDRDESC __BIT(9)
+#define RCVCTL_RCVOFFSET __BITS(7,1)
+#define RCVCTL_ENABLE __BIT(0)
#define GMAC_RCVPTR 0x224
+#define RCVPTR __BITS(11,4)
#define GMAC_RCVADDR_LOW 0x228
#define GMAC_RCVADDR_HIGH 0x22c
#define GMAC_RCVSTATUS0 0x230
+#define RCVSTATE __BITS(31,28)
+#define RCVSTATE_DIS 0
+#define RCVSTATE_ACTIVE 1
+#define RCVSTATE_IDLE_WAIT 2
+#define RCVSTATE_STOPPED 3
+#define RCVSTATE_SUSP_PENDING 4
+#define RCV_CURRDSCR __BITS(11,4)
#define GMAC_RCVSTATUS1 0x234
+#define RCV_ACTIVEDSCR __BITS(11,4)
#define GMAC_TX_GD_OCTETS_LO 0x300
#define UNIMAC_IPG_HD_BPG_CNTL 0x804
#define UNIMAC_COMMAND_CONFIG 0x808
+#define RUNT_FILTER_DIS __BIT(30)
+#define OOB_EFC_EN __BIT(29)
+#define IGNORE_TX_PAUSE __BIT(28)
+#define PRBL_ENA __BIT(27)
+#define RX_ERR_DIS __BIT(26)
+#define LINE_LOOPBACK __BIT(25)
+#define NO_LENGTH_CHECK __BIT(24)
+#define CNTRL_FRM_ENA __BIT(23)
+#define ENA_EXT_CONFIG __BIT(22)
+#define EN_INTERNAL_TX_CRS __BIT(21)
+#define SW_OVERRIDE_RX __BIT(18)
+#define SW_OVERRIDE_TX __BIT(17)
+#define MAC_LOOP_CON __BIT(16)
+#define LOOP_ENA __BIT(15)
+#define RCS_CORRUPT_URUN_EN __BIT(14)
+#define SW_RESET __BIT(13)
+#define OVERFLOW_EN __BIT(12)
+#define RX_LOW_LATENCY_EN __BIT(11)
+#define HD_ENA __BIT(10)
+#define TX_ADDR_INS __BIT(9)
+#define PAUSE_IGNORE __BIT(8)
+#define PAUSE_FWD __BIT(7)
+#define CRC_FWD __BIT(6)
+#define PAD_EN __BIT(5)
+#define PROMISC_EN __BIT(4)
+#define ETH_SPEED __BITS(3,2)
+#define ETH_SPEED_10 0
+#define ETH_SPEED_100 1
+#define ETH_SPEED_1000 2
+#define ETH_SPEED_2500 3
+#define RX_ENA __BIT(1)
+#define TX_ENA __BIT(0)
#define UNIMAC_MAC_0 0x80c // bits 16:47 of macaddr
#define UNIMAC_MAC_1 0x810 // bits 0:15 of macaddr
#define UNIMAC_FRAME_LEN 0x814
Index: src/sys/arch/arm/broadcom/bcm53xx_var.h
diff -u src/sys/arch/arm/broadcom/bcm53xx_var.h:1.1 src/sys/arch/arm/broadcom/bcm53xx_var.h:1.2
--- src/sys/arch/arm/broadcom/bcm53xx_var.h:1.1 Sat Sep 1 00:04:44 2012
+++ src/sys/arch/arm/broadcom/bcm53xx_var.h Wed Oct 3 19:18:41 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm53xx_var.h,v 1.1 2012/09/01 00:04:44 matt Exp $ */
+/* $NetBSD: bcm53xx_var.h,v 1.2 2012/10/03 19:18:41 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -108,6 +108,11 @@ void bcm53xx_device_register(device_t, v
psize_t bcm53xx_memprobe(void);
void bcm53xx_print_clocks(void);
void bcm53xx_rng_start(bus_space_tag_t, bus_space_handle_t);
+void bcm53xx_srab_init(void);
+uint32_t bcm53xx_srab_read_4(u_int);
+uint64_t bcm53xx_srab_read_8(u_int);
+void bcm53xx_srab_write_4(u_int, uint32_t);
+void bcm53xx_srab_write_8(u_int, uint64_t);
extern struct arm32_bus_dma_tag bcm53xx_dma_tag;
extern struct bus_space bcmgen_bs_tag;
extern bus_space_tag_t bcm53xx_ioreg_bst;
