Module Name: src
Committed By: kiyohara
Date: Sat Oct 20 12:45:22 UTC 2012
Modified Files:
src/sys/arch/bebox/bebox: locore.S
Log Message:
Enable cpu0 I/D cache. Disable cpu1 it.
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/bebox/bebox/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/bebox/bebox/locore.S
diff -u src/sys/arch/bebox/bebox/locore.S:1.26 src/sys/arch/bebox/bebox/locore.S:1.27
--- src/sys/arch/bebox/bebox/locore.S:1.26 Sat Oct 20 12:13:46 2012
+++ src/sys/arch/bebox/bebox/locore.S Sat Oct 20 12:45:22 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.26 2012/10/20 12:13:46 kiyohara Exp $ */
+/* $NetBSD: locore.S,v 1.27 2012/10/20 12:45:22 kiyohara Exp $ */
/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
/*
@@ -49,6 +49,7 @@
#include <machine/asm.h>
#include <powerpc/spr.h>
+#include <powerpc/oea/hid.h>
#include <powerpc/oea/spr.h>
/*
@@ -123,6 +124,12 @@ __start:
nop
__start_cpu1:
+ /* Disable data and instruction caches for spinup. */
+ li 8,0
+ mtspr SPR_HID0,8
+ sync
+ isync
+
#ifdef MULTIPROCESSOR
li 3, 0x1 /* CPU ID 1 */
ba cpu_spinstart /* cpu_spinstart(CPU ID) */
@@ -133,6 +140,20 @@ __start_cpu1:
nop
__start_cpu0:
+ /* Enable data and instruction caches */
+ mfspr 8,SPR_HID0
+ andi. 8,8,(HID0_ICE|HID0_DCE)@l
+ andi. 0,8,HID0_DCE
+ ori 7,8,HID0_ICFI
+ bne 1f
+ ori 7,7,HID0_DCFI
+1:
+ sync
+ mtspr SPR_HID0,7
+ sync
+ mtspr SPR_HID0,8
+ sync
+ isync
/* compute end of kernel memory */
#if defined(DDB) || NKSYMS || defined(MODULAR)
