Module Name: src
Committed By: matt
Date: Wed Nov 21 19:39:39 UTC 2012
Modified Files:
src/sys/arch/arm/arm: cpufunc_asm_armv7.S
Log Message:
Always supply all registers (don't make one implicit).
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/arm/cpufunc_asm_armv7.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc_asm_armv7.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.10 src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.11
--- src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.10 Sun Oct 21 09:25:16 2012
+++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S Wed Nov 21 19:39:39 2012
@@ -48,8 +48,8 @@ ENTRY(armv7_context_switch)
dsb @ data synchronization barrier
mrc p15, 0, r2, c0, c0, 5 @ get MPIDR
cmp r2, #0
- orrlt r0, #0x5b @ MP, cachable (Normal WB)
- orrge r0, #0x1b @ Non-MP, cacheable, normal WB
+ orrlt r0, r0, #0x5b @ MP, cachable (Normal WB)
+ orrge r0, r0, #0x1b @ Non-MP, cacheable, normal WB
mcr p15, 0, r0, c2, c0, 0 @ set the new TTB
#ifdef MULTIPROCESSOR
mcr p15, 0, r0, c8, c3, 0 @ flush the I+D
@@ -76,8 +76,8 @@ END(armv7_tlb_flushID_SE)
ENTRY_NP(armv7_setttb)
mrc p15, 0, r2, c0, c0, 5 @ get MPIDR
cmp r2, #0
- orrlt r0, #0x5b @ MP, cachable (Normal WB)
- orrge r0, #0x1b @ Non-MP, cacheable, normal WB
+ orrlt r0, r0, #0x5b @ MP, cachable (Normal WB)
+ orrge r0, r0, #0x1b @ Non-MP, cacheable, normal WB
mcr p15, 0, r0, c2, c0, 0 @ load new TTB
cmp r1, #0
#ifdef MULTIPROCESSOR
