Module Name: src
Committed By: matt
Date: Tue Nov 27 19:24:47 UTC 2012
Modified Files:
src/sys/arch/powerpc/booke: e500_mpsubr.S e500_tlb.c genassym.cf
src/sys/arch/powerpc/include: cpu.h
src/sys/arch/powerpc/include/booke: e500var.h
Log Message:
Make the 85xx get closer to spinning up the secondary CPUs.
Don't assume TLB1[0] has the mapping for VA/PA 0.
Make sure the TLB1 entries that map physical memory have the M (memory
coherent) bit set.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/powerpc/booke/e500_mpsubr.S
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/powerpc/booke/e500_tlb.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/powerpc/booke/genassym.cf
cvs rdiff -u -r1.94 -r1.95 src/sys/arch/powerpc/include/cpu.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/powerpc/include/booke/e500var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/booke/e500_mpsubr.S
diff -u src/sys/arch/powerpc/booke/e500_mpsubr.S:1.2 src/sys/arch/powerpc/booke/e500_mpsubr.S:1.3
--- src/sys/arch/powerpc/booke/e500_mpsubr.S:1.2 Wed Jun 29 06:06:04 2011
+++ src/sys/arch/powerpc/booke/e500_mpsubr.S Tue Nov 27 19:24:46 2012
@@ -1,3 +1,31 @@
+/*-
+ * Copyright (c) 2011, 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
/*
* r3 = fdt pointer (ignored)
@@ -11,8 +39,6 @@
.p2align 5
ENTRY_NOPROFILE(e500_spinup_trampoline)
- stw %r7, 4(%r0) /* r7 to 4 */
-
lis %r31, 0xdeadbeef@h
ori %r31, %r31, 0xdeadbeef@l
mr %r30, %r31
@@ -49,16 +75,38 @@ ENTRY_NOPROFILE(e500_spinup_trampoline)
*/
lis %r20, _C_LABEL(cpu_hatch_data)@h
ori %r20, %r20, _C_LABEL(cpu_hatch_data)@l
+ sync
+
+ /*
+ * Ensure that the TLB entry we are using is memory coherent.
+ */
+ lis %r0, (MASX_TLBSEL_MAKE(1)|MAS0_ESEL_MAKE(0))@h
+ mtspr SPR_MAS0, %r0 /* setup MAS0 */
+ lis %r3, (MAS1_V|MAS1_IPROT)@h /* V | IPROT */
+ ori %r3, %r3, MASX_TSIZE_64MB /* and 64MB */
+ mtspr SPR_MAS1, %r3 /* save MAS1 */
+ li %r3, MAS2_M /* set M bit */
+ mtspr SPR_MAS2, %r3 /* save MAS2 */
+ li %r3, MAS3_SX|MAS3_SR|MAS3_SW /* set kernel RWX */
+ mtspr SPR_MAS3, %r3 /* save MAS3 */
+ tlbwe /* update entry */
+ isync /* flush i-stream */
+ sync /* sync memory. */
li %r0, 0
stw %r0, HATCH_RUNNING(%r20) /* progress */
- eieio
+ sync
+#if 0
+ dcbf 0, %r20
+#endif
lwz %r1, HATCH_SP(%r20) /* get hatch SP */
lwz %r21, HATCH_CI(%r20) /* get cpu_info */
mtsprg0 %r21 /* save cpu_info */
lwz %r13, CI_CURLWP(%r21) /* load r13 with curlwp */
mtsprg2 %r13 /* save it in sprg2 */
+ addi %r0,%r21,CI_SAVELIFO /* get SAVE area start */
+ mtsprg3 %r0 /* save it in sprg3 */
/*
* Now to synchronize timebase values. First to make sure HID0 is
@@ -102,6 +150,7 @@ ENTRY_NOPROFILE(e500_spinup_trampoline)
li %r0, 2
stw %r0, HATCH_RUNNING(%r20) /* progress */
+ sync
/*
* We have to setup the IVOR SPRs since the ones u-boot setup
@@ -146,15 +195,11 @@ ENTRY_NOPROFILE(e500_spinup_trampoline)
stw %r0, HATCH_RUNNING(%r20) /* progress */
/*
- * Let's find out what TLB1[0] entry we are supposed to use.
+ * Let's find out what TLB1 entry we are supposed to use.
*/
- li %r3, 0
+ lwz %r3, HATCH_TLBIDX(%r20)
bl _C_LABEL(e500_tlb1_fetch)
- lwz %r28, 0(%r3) /* load the saved TLB1 entry */
- mtspr SPR_MAS0, %r28 /* place into SPRs */
- mtspr SPR_MAS1, %r29
- mtspr SPR_MAS2, %r30
- mtspr SPR_MAS3, %r31
+ lmw %r28, 0(%r3) /* load the saved TLB1 entry */
li %r0, 6
stw %r0, HATCH_RUNNING(%r20) /* progress */
@@ -182,6 +227,30 @@ ENTRY_NOPROFILE(e500_spinup_trampoline)
li %r0, 8
stw %r0, HATCH_RUNNING(%r20) /* progress */
+ /*
+ * Let's clear TBL1[0] and TBL1[1]
+ */
+ li %r8, 0
+ mtspr SPR_MAS1, %r8
+ mtspr SPR_MAS2, %r8
+ mtspr SPR_MAS3, %r8
+ mtspr SPR_MAS7, %r8
+
+ lis %r8, (MASX_TLBSEL_MAKE(1)|MAS0_ESEL_MAKE(0))@h
+ mtspr SPR_MAS0, %r8
+ tlbwe
+
+ lis %r8, (MASX_TLBSEL_MAKE(1)|MAS0_ESEL_MAKE(1))@h
+ mtspr SPR_MAS0, %r8
+ tlbwe
+
+ /*
+ * Now load the new TLB data into the MAS registers.
+ */
+ mtspr SPR_MAS0, %r28 /* place into SPRs */
+ mtspr SPR_MAS1, %r29
+ mtspr SPR_MAS2, %r30
+ mtspr SPR_MAS3, %r31
tlbwe
mtsrr0 %r5
@@ -197,29 +266,29 @@ ENTRY_NOPROFILE(e500_spinup_trampoline)
stw %r0, HATCH_RUNNING(%r20) /* progress */
/*
- * Now we can use our stack...
+ * We now have our TLB1[0] in place. Now we need to load the rest of
+ * TLB1 with our entries. After this is done, we should have access
+ * to everything.
*/
- lwz %r0, CI_CURPCB(%r21)
- lwz %r1, PCB_SP(%r0)
+ bl _C_LABEL(e500_tlb1_sync)
li %r0, 11
stw %r0, HATCH_RUNNING(%r20) /* progress */
/*
- * Tell spinup code we are done with the hatch stack.
+ * Now we can use our stack...
*/
- li %r0, 0
- stw %r0, HATCH_SP(%r20)
+ lwz %r0, CI_CURPCB(%r21)
+ lwz %r1, PCB_SP(%r0)
li %r0, 12
stw %r0, HATCH_RUNNING(%r20) /* progress */
/*
- * We now have our TLB1[0] in place. Now we need to load the rest of
- * TLB1 with our entries. After this is done, we should have access
- * to everything.
+ * Tell spinup code we are done with the hatch stack.
*/
- bl _C_LABEL(e500_tlb1_sync)
+ li %r0, 0
+ stw %r0, HATCH_SP(%r20)
li %r0, 13
stw %r0, HATCH_RUNNING(%r20) /* progress */
Index: src/sys/arch/powerpc/booke/e500_tlb.c
diff -u src/sys/arch/powerpc/booke/e500_tlb.c:1.11 src/sys/arch/powerpc/booke/e500_tlb.c:1.12
--- src/sys/arch/powerpc/booke/e500_tlb.c:1.11 Wed Jul 25 22:11:36 2012
+++ src/sys/arch/powerpc/booke/e500_tlb.c Tue Nov 27 19:24:46 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: e500_tlb.c,v 1.11 2012/07/25 22:11:36 matt Exp $ */
+/* $NetBSD: e500_tlb.c,v 1.12 2012/11/27 19:24:46 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -38,7 +38,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: e500_tlb.c,v 1.11 2012/07/25 22:11:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: e500_tlb.c,v 1.12 2012/11/27 19:24:46 matt Exp $");
#include <sys/param.h>
@@ -202,6 +202,7 @@ hwtlb_write(const struct e500_hwtlb hwtl
*/
if (hwtlb.hwtlb_mas1 & MAS1_V) {
mtspr(SPR_MAS3, hwtlb.hwtlb_mas3);
+ //mtspr(SPR_MAS7, 0);
}
#if 0
@@ -543,6 +544,7 @@ e500_tlb_update_addr(vaddr_t va, tlb_asi
}
mtspr(SPR_MAS2, hwtlb.hwtlb_mas2);
mtspr(SPR_MAS3, hwtlb.hwtlb_mas3);
+ //mtspr(SPR_MAS7, 0);
__asm volatile("tlbwe");
if (asid == KERNEL_PID)
__asm volatile("isync\n\tsync");
@@ -641,11 +643,6 @@ e500_tlb_walk(void *ctx, bool (*func)(vo
mtspr(SPR_MAS2, epn);
__asm volatile("tlbre");
hwtlb.hwtlb_mas1 = mfspr(SPR_MAS1);
- /*
- * If this is a valid entry for AS space 1 and
- * its asid matches the constraints of the caller,
- * clear its valid bit.
- */
if (hwtlb.hwtlb_mas1 & MAS1_V) {
hwtlb.hwtlb_mas2 = mfspr(SPR_MAS2);
hwtlb.hwtlb_mas3 = mfspr(SPR_MAS3);
@@ -682,7 +679,7 @@ e500_tlb_lookup_xtlb_pa(vaddr_t pa, u_in
return NULL;
}
-static struct e500_xtlb *
+struct e500_xtlb *
e500_tlb_lookup_xtlb(vaddr_t va, u_int *slotp)
{
struct e500_tlb1 * const tlb1 = &e500_tlb1;
@@ -942,6 +939,15 @@ e500_tlb_init(vaddr_t endkernel, psize_t
if (xtlb->e_tlb.tlb_va == 0
|| xtlb->e_tlb.tlb_va + xtlb->e_tlb.tlb_size <= memsize) {
memmapped += xtlb->e_tlb.tlb_size;
+ /*
+ * Let make sure main memory is setup so it's memory
+ * coherent. For some reason u-boot doesn't set it up
+ * that way.
+ */
+ if ((xtlb->e_hwtlb.hwtlb_mas2 & MAS2_M) == 0) {
+ xtlb->e_hwtlb.hwtlb_mas2 |= MAS2_M;
+ hwtlb_write(xtlb->e_hwtlb, true);
+ }
}
}
Index: src/sys/arch/powerpc/booke/genassym.cf
diff -u src/sys/arch/powerpc/booke/genassym.cf:1.9 src/sys/arch/powerpc/booke/genassym.cf:1.10
--- src/sys/arch/powerpc/booke/genassym.cf:1.9 Wed Aug 1 16:19:43 2012
+++ src/sys/arch/powerpc/booke/genassym.cf Tue Nov 27 19:24:46 2012
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.9 2012/08/01 16:19:43 matt Exp $
+# $NetBSD: genassym.cf,v 1.10 2012/11/27 19:24:46 matt Exp $
#-
# Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
@@ -110,4 +110,5 @@ define HATCH_RUNNING offsetof(struct cp
define HATCH_SP offsetof(struct cpu_hatch_data, hatch_sp)
define HATCH_TBU offsetof(struct cpu_hatch_data, hatch_tbu)
define HATCH_TBL offsetof(struct cpu_hatch_data, hatch_tbl)
+define HATCH_TLBIDX offsetof(struct cpu_hatch_data, hatch_tlbidx)
endif
Index: src/sys/arch/powerpc/include/cpu.h
diff -u src/sys/arch/powerpc/include/cpu.h:1.94 src/sys/arch/powerpc/include/cpu.h:1.95
--- src/sys/arch/powerpc/include/cpu.h:1.94 Sat Oct 20 14:42:15 2012
+++ src/sys/arch/powerpc/include/cpu.h Tue Nov 27 19:24:45 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.94 2012/10/20 14:42:15 kiyohara Exp $ */
+/* $NetBSD: cpu.h,v 1.95 2012/11/27 19:24:45 matt Exp $ */
/*
* Copyright (C) 1999 Wolfgang Solfrank.
@@ -170,6 +170,7 @@ struct cpu_hatch_data {
#endif
#if defined(PPC_BOOKE)
vaddr_t hatch_sp;
+ u_int hatch_tlbidx;
#endif
};
Index: src/sys/arch/powerpc/include/booke/e500var.h
diff -u src/sys/arch/powerpc/include/booke/e500var.h:1.6 src/sys/arch/powerpc/include/booke/e500var.h:1.7
--- src/sys/arch/powerpc/include/booke/e500var.h:1.6 Fri Jul 27 22:24:13 2012
+++ src/sys/arch/powerpc/include/booke/e500var.h Tue Nov 27 19:24:47 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: e500var.h,v 1.6 2012/07/27 22:24:13 matt Exp $ */
+/* $NetBSD: e500var.h,v 1.7 2012/11/27 19:24:47 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -91,6 +91,9 @@ void e500_tlb1_sync(void);
void e500_ipi_halt(void);
void e500_spinup_trampoline(void);
void e500_cpu_hatch(struct cpu_info *);
+struct e500_xtlb *
+ e500_tlb_lookup_xtlb(vaddr_t, u_int *);
+
void pq3gpio_attach(device_t, device_t, void *);
