Module Name:    src
Committed By:   matt
Date:           Wed Nov 28 01:45:27 UTC 2012

Modified Files:
        src/common/lib/libc/arch/arm/gen [matt-nb6-plus]: byte_swap_2.S
            byte_swap_4.S

Log Message:
Use rev/rev16 on armv6 and later.


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.4.24.1 src/common/lib/libc/arch/arm/gen/byte_swap_2.S \
    src/common/lib/libc/arch/arm/gen/byte_swap_4.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/common/lib/libc/arch/arm/gen/byte_swap_2.S
diff -u src/common/lib/libc/arch/arm/gen/byte_swap_2.S:1.4 src/common/lib/libc/arch/arm/gen/byte_swap_2.S:1.4.24.1
--- src/common/lib/libc/arch/arm/gen/byte_swap_2.S:1.4	Mon Apr 28 20:22:52 2008
+++ src/common/lib/libc/arch/arm/gen/byte_swap_2.S	Wed Nov 28 01:45:26 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: byte_swap_2.S,v 1.4 2008/04/28 20:22:52 martin Exp $	*/
+/*	$NetBSD: byte_swap_2.S,v 1.4.24.1 2012/11/28 01:45:26 matt Exp $	*/
 
 /*-
  * Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -41,7 +41,11 @@ _ENTRY(_C_LABEL(ntohs))
 _ENTRY(_C_LABEL(htons))
 #endif
 _PROF_PROLOGUE
+#ifdef _ARM_ARCH_6
+	rev16		r0, r0
+#else
 	and		r1, r0, #0xff
 	mov		r0, r0, lsr #8
 	orr		r0, r0, r1, lsl #8
+#endif
 	RET
Index: src/common/lib/libc/arch/arm/gen/byte_swap_4.S
diff -u src/common/lib/libc/arch/arm/gen/byte_swap_4.S:1.4 src/common/lib/libc/arch/arm/gen/byte_swap_4.S:1.4.24.1
--- src/common/lib/libc/arch/arm/gen/byte_swap_4.S:1.4	Mon Apr 28 20:22:52 2008
+++ src/common/lib/libc/arch/arm/gen/byte_swap_4.S	Wed Nov 28 01:45:26 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: byte_swap_4.S,v 1.4 2008/04/28 20:22:52 martin Exp $	*/
+/*	$NetBSD: byte_swap_4.S,v 1.4.24.1 2012/11/28 01:45:26 matt Exp $	*/
 
 /*-
  * Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -41,8 +41,12 @@ _ENTRY(_C_LABEL(ntohl))
 _ENTRY(_C_LABEL(htonl))
 #endif
 _PROF_PROLOGUE
+#ifdef _ARM_ARCH_6
+	rev		r0, r0
+#else
 	eor		r1, r0, r0, ror #16
 	bic		r1, r1, #0x00FF0000
 	mov		r0, r0, ror #8
 	eor		r0, r0, r1, lsr #8
+#endif
 	RET

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