CVS commit: src/sys/arch/sh3/sh3

[Izumi Tsutsui]

Module Name:    src
Committed By:   tsutsui
Date:           Wed Dec 12 13:34:49 UTC 2012

Modified Files:
        src/sys/arch/sh3/sh3: cache_sh4.c

Log Message:
Fix fallouts in rev 1.19:
 
http://www.nerv.org/~ryo/netbsd/netbsd/?q=id:20080316T191753Z.1654448ada03ce3c4668f3fe472796d0b771e147
 - revert RUN_P1 -> PAD_P1_SWITCH changes where RUN_P1 is
   actually required  (all icache CCIA ops still need RUN_P2)
 - sh4_dcache_wbinv_all() and sh4_dcache_wbinv_range_index()
   (which manipulate CCDA arrays) are no longer have RUN_P2 so
   we can't call them directly from sh4_icache_sync_all() and
   sh4_icache_sync_range_index() funcitons;  use function pointers
   (which have appropriate addresses) instead for 7750 and 7750S


To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/sh3/sh3/cache_sh4.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/sh3/sh3/cache_sh4.c
diff -u src/sys/arch/sh3/sh3/cache_sh4.c:1.20 src/sys/arch/sh3/sh3/cache_sh4.c:1.21
--- src/sys/arch/sh3/sh3/cache_sh4.c:1.20	Mon Apr 28 20:23:35 2008
+++ src/sys/arch/sh3/sh3/cache_sh4.c	Wed Dec 12 13:34:49 2012
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache_sh4.c,v 1.20 2008/04/28 20:23:35 martin Exp $	*/
+/*	$NetBSD: cache_sh4.c,v 1.21 2012/12/12 13:34:49 tsutsui Exp $	*/
 
 /*-
  * Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_sh4.c,v 1.20 2008/04/28 20:23:35 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_sh4.c,v 1.21 2012/12/12 13:34:49 tsutsui Exp $");
 
 #include "opt_cache.h"
 
@@ -222,14 +222,15 @@ sh4_icache_sync_all(void)
 	vaddr_t va = 0;
 	vaddr_t eva = SH4_ICACHE_SIZE;
 
-	sh4_dcache_wbinv_all();
+	/* d$ index ops must be called via P2 on 7750 and 7750S */
+	(*sh_cache_ops._dcache_wbinv_all)();
 
 	RUN_P2;
 	while (va < eva) {
 		cache_sh4_op_8lines_32(va, SH4_CCIA, CCIA_ENTRY_MASK, CCIA_V);
 		va += 32 * 8;
 	}
-	PAD_P1_SWITCH;
+	RUN_P1;
 }
 
 void
@@ -248,7 +249,7 @@ sh4_icache_sync_range(vaddr_t va, vsize_
 		_reg_write_4(ccia, va & CCIA_TAGADDR_MASK); /* V = 0 */
 		va += 32;
 	}
-	PAD_P1_SWITCH;
+	RUN_P1;
 }
 
 void
@@ -257,7 +258,8 @@ sh4_icache_sync_range_index(vaddr_t va, 
 	vaddr_t eva = round_line(va + sz);
 	va = trunc_line(va);
 
-	sh4_dcache_wbinv_range_index(va, eva - va);
+	/* d$ index ops must be called via P2 on 7750 and 7750S */
+	(*sh_cache_ops._dcache_wbinv_range_index)(va, eva - va);
 
 	RUN_P2;
 	while ((eva - va) >= (8 * 32)) {
@@ -269,7 +271,7 @@ sh4_icache_sync_range_index(vaddr_t va, 
 		cache_sh4_op_line_32(va, SH4_CCIA, CCIA_ENTRY_MASK, CCIA_V);
 		va += 32;
 	}
-	PAD_P1_SWITCH;
+	RUN_P1;
 }
 
 void
@@ -419,7 +421,7 @@ sh4_emode_icache_sync_all(void)
 		    CCIA_V, 13);
 		va += 32 * 8;
 	}
-	PAD_P1_SWITCH;
+	RUN_P1;
 }
 
 void
@@ -442,7 +444,7 @@ sh4_emode_icache_sync_range_index(vaddr_
 		    CCIA_V, 13);
 		va += 32;
 	}
-	PAD_P1_SWITCH;
+	RUN_P1;
 }
 
 void