Module Name: src
Committed By: jmcneill
Date: Mon Dec 31 12:45:49 UTC 2012
Modified Files:
src/sys/arch/arm/omap: files.omap2
Added Files:
src/sys/arch/arm/omap: omap3_i2c.c omap3_i2creg.h
Log Message:
Add OMAP3530 I2C support
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/omap/files.omap2
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/omap/omap3_i2c.c \
src/sys/arch/arm/omap/omap3_i2creg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/omap/files.omap2
diff -u src/sys/arch/arm/omap/files.omap2:1.18 src/sys/arch/arm/omap/files.omap2:1.19
--- src/sys/arch/arm/omap/files.omap2:1.18 Wed Dec 12 00:33:45 2012
+++ src/sys/arch/arm/omap/files.omap2 Mon Dec 31 12:45:49 2012
@@ -1,4 +1,4 @@
-# $NetBSD: files.omap2,v 1.18 2012/12/12 00:33:45 matt Exp $
+# $NetBSD: files.omap2,v 1.19 2012/12/31 12:45:49 jmcneill Exp $
#
# Configuration info for Texas Instruments OMAP2/OMAP3 CPU support
# Based on xscale/files.pxa2x0
@@ -48,6 +48,11 @@ device omapgpio: gpiobus
attach omapgpio at obio with omap2gpio
file arch/arm/omap/omap2_gpio.c (omap2 | omap3) & omapgpio
+# OMAP3 I2C controllers
+device omapiic: i2cbus, i2cexec
+attach omapiic at obio with omap3_i2c
+file arch/arm/omap/omap3_i2c.c omap3_i2c
+
# OMAP dual-mode timer
device omapdmtimer
file arch/arm/omap/omap_dmtimer.c omapdmtimer
Added files:
Index: src/sys/arch/arm/omap/omap3_i2c.c
diff -u /dev/null src/sys/arch/arm/omap/omap3_i2c.c:1.1
--- /dev/null Mon Dec 31 12:45:50 2012
+++ src/sys/arch/arm/omap/omap3_i2c.c Mon Dec 31 12:45:49 2012
@@ -0,0 +1,436 @@
+/* $NetBSD: omap3_i2c.c,v 1.1 2012/12/31 12:45:49 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2012 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: omap3_i2c.c,v 1.1 2012/12/31 12:45:49 jmcneill Exp $");
+
+#include "opt_omap.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/conf.h>
+#include <sys/bus.h>
+#include <sys/proc.h>
+#include <sys/kernel.h>
+#include <sys/mutex.h>
+
+#include <dev/i2c/i2cvar.h>
+
+#include <arm/omap/omap2_obiovar.h>
+
+#include <arm/omap/omap2_reg.h>
+#include <arm/omap/omap3_i2creg.h>
+
+#ifndef OMAP3_I2C_SLAVE_ADDR
+#define OMAP3_I2C_SLAVE_ADDR 0x01
+#endif
+
+struct omap3_i2c_softc {
+ device_t sc_dev;
+ struct i2c_controller sc_ic;
+ kmutex_t sc_lock;
+ device_t sc_i2cdev;
+
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+};
+
+#define I2C_READ_REG(sc, reg) \
+ bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg))
+#define I2C_READ_DATA(sc) \
+ bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, OMAP3_I2C_DATA);
+#define I2C_WRITE_REG(sc, reg, val) \
+ bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
+#define I2C_WRITE_DATA(sc, val) \
+ bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, OMAP3_I2C_DATA, (val))
+
+static int omap3_i2c_match(device_t, cfdata_t, void *);
+static void omap3_i2c_attach(device_t, device_t, void *);
+static int omap3_i2c_rescan(device_t, const char *, const int *);
+static void omap3_i2c_childdet(device_t, device_t);
+
+static int omap3_i2c_acquire_bus(void *, int);
+static void omap3_i2c_release_bus(void *, int);
+static int omap3_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *,
+ size_t, void *, size_t, int);
+
+static int omap3_i2c_reset(struct omap3_i2c_softc *);
+static int omap3_i2c_read(struct omap3_i2c_softc *, i2c_addr_t,
+ uint8_t *, size_t, int);
+static int omap3_i2c_write(struct omap3_i2c_softc *, i2c_addr_t,
+ const uint8_t *, size_t, int);
+static int omap3_i2c_wait(struct omap3_i2c_softc *, uint16_t, uint16_t);
+static int omap3_i2c_stat(struct omap3_i2c_softc *);
+static int omap3_i2c_flush(struct omap3_i2c_softc *);
+
+CFATTACH_DECL2_NEW(omap3_i2c, sizeof(struct omap3_i2c_softc),
+ omap3_i2c_match, omap3_i2c_attach, NULL, NULL,
+ omap3_i2c_rescan, omap3_i2c_childdet);
+
+static int
+omap3_i2c_match(device_t parent, cfdata_t match, void *opaque)
+{
+ struct obio_attach_args *obio = opaque;
+
+#if defined(OMAP_3530)
+ if (obio->obio_addr == I2C1_BASE_3530 ||
+ obio->obio_addr == I2C2_BASE_3530 ||
+ obio->obio_addr == I2C3_BASE_3530)
+ return 1;
+#endif
+
+ return 0;
+}
+
+static void
+omap3_i2c_attach(device_t parent, device_t self, void *opaque)
+{
+ struct omap3_i2c_softc *sc = device_private(self);
+ struct obio_attach_args *obio = opaque;
+ uint16_t rev;
+
+ aprint_naive("\n");
+
+ sc->sc_dev = self;
+ sc->sc_iot = obio->obio_iot;
+ mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
+ sc->sc_ic.ic_cookie = sc;
+ sc->sc_ic.ic_acquire_bus = omap3_i2c_acquire_bus;
+ sc->sc_ic.ic_release_bus = omap3_i2c_release_bus;
+ sc->sc_ic.ic_exec = omap3_i2c_exec;
+
+ if (bus_space_map(obio->obio_iot, obio->obio_addr, obio->obio_size,
+ 0, &sc->sc_ioh) != 0) {
+ aprint_error(": couldn't map address space\n");
+ return;
+ }
+
+ rev = I2C_READ_REG(sc, OMAP3_I2C_REV);
+ aprint_normal(": rev %d.%d\n",
+ (int)((rev & OMAP3_I2C_REV_MAJ_MASK) >> OMAP3_I2C_REV_MAJ_SHIFT),
+ (int)((rev & OMAP3_I2C_REV_MIN_MASK) >> OMAP3_I2C_REV_MIN_SHIFT));
+
+ omap3_i2c_reset(sc);
+ omap3_i2c_flush(sc);
+
+ omap3_i2c_rescan(self, NULL, NULL);
+}
+
+static int
+omap3_i2c_rescan(device_t self, const char *ifattr, const int *locs)
+{
+ struct omap3_i2c_softc *sc = device_private(self);
+ struct i2cbus_attach_args iba;
+
+ if (ifattr_match(ifattr, "i2cbus") && sc->sc_i2cdev == NULL) {
+ memset(&iba, 0, sizeof(iba));
+ iba.iba_tag = &sc->sc_ic;
+ sc->sc_i2cdev = config_found_ia(self, "i2cbus",
+ &iba, iicbus_print);
+ }
+
+ return 0;
+}
+
+static void
+omap3_i2c_childdet(device_t self, device_t child)
+{
+ struct omap3_i2c_softc *sc = device_private(self);
+
+ if (sc->sc_i2cdev == child)
+ sc->sc_i2cdev = NULL;
+}
+
+static int
+omap3_i2c_acquire_bus(void *opaque, int flags)
+{
+ struct omap3_i2c_softc *sc = opaque;
+
+ if (flags & I2C_F_POLL) {
+ if (!mutex_tryenter(&sc->sc_lock))
+ return EBUSY;
+ } else {
+ mutex_enter(&sc->sc_lock);
+ }
+
+ return 0;
+}
+
+static void
+omap3_i2c_release_bus(void *opaque, int flags)
+{
+ struct omap3_i2c_softc *sc = opaque;
+
+ mutex_exit(&sc->sc_lock);
+}
+
+static int
+omap3_i2c_exec(void *opaque, i2c_op_t op, i2c_addr_t addr,
+ const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
+{
+ struct omap3_i2c_softc *sc = opaque;
+ int err;
+
+ if (cmdlen > 0) {
+ err = omap3_i2c_write(sc, addr, cmdbuf, cmdlen,
+ I2C_OP_READ_P(op) ? 0 : I2C_F_STOP);
+ if (err)
+ goto done;
+ }
+
+ if (I2C_OP_STOP_P(op))
+ flags |= I2C_F_STOP;
+
+ /*
+ * I2C controller doesn't allow for zero-byte transfers.
+ */
+ if (len == 0) {
+ err = EINVAL;
+ goto done;
+ }
+
+ if (I2C_OP_READ_P(op)) {
+ err = omap3_i2c_read(sc, addr, buf, len, flags);
+ } else {
+ err = omap3_i2c_write(sc, addr, buf, len, flags);
+ }
+
+done:
+ if (err)
+ omap3_i2c_reset(sc);
+
+ omap3_i2c_flush(sc);
+
+ return err;
+}
+
+static int
+omap3_i2c_reset(struct omap3_i2c_softc *sc)
+{
+ uint32_t psc, scll, sclh;
+
+ /* Soft reset */
+ I2C_WRITE_REG(sc, OMAP3_I2C_SYSC, OMAP3_I2C_SRST);
+ delay(1000);
+ I2C_WRITE_REG(sc, OMAP3_I2C_SYSC, 0);
+
+ /* Disable */
+ if (I2C_READ_REG(sc, OMAP3_I2C_CON) & OMAP3_I2C_CON_I2C_EN) {
+ I2C_WRITE_REG(sc, OMAP3_I2C_CON, 0);
+ delay(50000);
+ }
+
+ /* XXX standard speed only */
+ psc = (96000000 / 19200000) - 1;
+ scll = sclh = (19200000 / (2 * 100000)) - 6;
+
+ /* Clocks */
+ I2C_WRITE_REG(sc, OMAP3_I2C_PSC, psc);
+ I2C_WRITE_REG(sc, OMAP3_I2C_SCLL, scll);
+ I2C_WRITE_REG(sc, OMAP3_I2C_SCLH, sclh);
+
+ /* Own I2C address */
+ I2C_WRITE_REG(sc, OMAP3_I2C_OA0, OMAP3_I2C_SLAVE_ADDR);
+
+ /* Enable */
+ I2C_WRITE_REG(sc, OMAP3_I2C_CON, OMAP3_I2C_CON_I2C_EN);
+
+ /* Enable interrupts (required even for polling mode) */
+ I2C_WRITE_REG(sc, OMAP3_I2C_IE,
+ OMAP3_I2C_IE_XRDY_IE|OMAP3_I2C_IE_RRDY_IE|
+ OMAP3_I2C_IE_ARDY_IE|OMAP3_I2C_IE_NACK_IE|
+ OMAP3_I2C_IE_AL_IE);
+ delay(1000);
+
+ return 0;
+}
+
+static int
+omap3_i2c_read(struct omap3_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf,
+ size_t buflen, int flags)
+{
+ uint16_t con, stat;
+ int err, i, retry;
+
+ err = omap3_i2c_wait(sc, OMAP3_I2C_STAT_BB, 0);
+ if (err)
+ return err;
+
+ con = OMAP3_I2C_CON_I2C_EN;
+ con |= OMAP3_I2C_CON_MST;
+ con |= (OMAP3_I2C_CON_OPMODE_FASTSTD << OMAP3_I2C_CON_OPMODE_SHIFT);
+ con |= OMAP3_I2C_CON_STT;
+ if (flags & I2C_F_STOP)
+ con |= OMAP3_I2C_CON_STP;
+ if (addr & ~0x7f)
+ con |= OMAP3_I2C_CON_XSA;
+
+ I2C_WRITE_REG(sc, OMAP3_I2C_CNT, buflen);
+ I2C_WRITE_REG(sc, OMAP3_I2C_SA,
+ (addr << OMAP3_I2C_SA_SHIFT) & OMAP3_I2C_SA_MASK);
+ I2C_WRITE_REG(sc, OMAP3_I2C_CON, con);
+
+ for (i = 0; i < buflen; i++) {
+ stat = omap3_i2c_stat(sc);
+ if ((stat & OMAP3_I2C_STAT_RRDY) == 0)
+ return EBUSY;
+ buf[i] = I2C_READ_DATA(sc);
+ }
+
+ delay(50000);
+ if (I2C_READ_REG(sc, OMAP3_I2C_STAT) & OMAP3_I2C_STAT_NACK)
+ return EIO;
+
+ retry = 1000;
+ I2C_WRITE_REG(sc, OMAP3_I2C_CON, 0);
+ while (I2C_READ_REG(sc, OMAP3_I2C_STAT) ||
+ (I2C_READ_REG(sc, OMAP3_I2C_CON) & OMAP3_I2C_CON_MST)) {
+ delay(1000);
+ I2C_WRITE_REG(sc, OMAP3_I2C_STAT, 0xffff);
+ if (--retry == 0)
+ break;
+ }
+
+ return 0;
+}
+
+static int
+omap3_i2c_write(struct omap3_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf,
+ size_t buflen, int flags)
+{
+ uint16_t con, stat;
+ int err, i, retry;
+
+ err = omap3_i2c_wait(sc, OMAP3_I2C_STAT_BB, 0);
+ if (err)
+ return err;
+
+ con = OMAP3_I2C_CON_I2C_EN;
+ con |= OMAP3_I2C_CON_MST;
+ con |= (OMAP3_I2C_CON_OPMODE_FASTSTD << OMAP3_I2C_CON_OPMODE_SHIFT);
+ con |= OMAP3_I2C_CON_STT;
+ if (flags & I2C_F_STOP)
+ con |= OMAP3_I2C_CON_STP;
+ con |= OMAP3_I2C_CON_TRX;
+ if (addr & ~0x7f)
+ con |= OMAP3_I2C_CON_XSA;
+
+ I2C_WRITE_REG(sc, OMAP3_I2C_SA,
+ (addr << OMAP3_I2C_SA_SHIFT) & OMAP3_I2C_SA_MASK);
+ I2C_WRITE_REG(sc, OMAP3_I2C_CNT, buflen);
+ I2C_WRITE_REG(sc, OMAP3_I2C_CON, con);
+
+ for (i = 0; i < buflen; i++) {
+ stat = omap3_i2c_stat(sc);
+ if ((stat & OMAP3_I2C_STAT_XRDY) == 0)
+ return EBUSY;
+ I2C_WRITE_DATA(sc, buf[i]);
+ I2C_WRITE_REG(sc, OMAP3_I2C_STAT, OMAP3_I2C_STAT_XRDY);
+ }
+
+ delay(50000);
+ if (I2C_READ_REG(sc, OMAP3_I2C_STAT) & OMAP3_I2C_STAT_NACK)
+ return EIO;
+
+ retry = 1000;
+ I2C_WRITE_REG(sc, OMAP3_I2C_CON, 0);
+ while (I2C_READ_REG(sc, OMAP3_I2C_STAT) ||
+ (I2C_READ_REG(sc, OMAP3_I2C_CON) & OMAP3_I2C_CON_MST)) {
+ delay(1000);
+ I2C_WRITE_REG(sc, OMAP3_I2C_STAT, 0xffff);
+ if (--retry == 0)
+ break;
+ }
+
+ return 0;
+}
+
+static int
+omap3_i2c_wait(struct omap3_i2c_softc *sc, uint16_t mask, uint16_t val)
+{
+ int retry = 10;
+ uint16_t v;
+
+ I2C_WRITE_REG(sc, OMAP3_I2C_STAT, 0xffff);
+ while (((v = I2C_READ_REG(sc, OMAP3_I2C_STAT)) & mask) != val) {
+ I2C_WRITE_REG(sc, OMAP3_I2C_STAT, v);
+ --retry;
+ if (retry == 0) {
+ printf("%s: wait timeout, "
+ "mask = %#x val = %#x stat = %#x\n",
+ device_xname(sc->sc_dev), mask, val, v);
+ return EBUSY;
+ }
+ delay(50000);
+ }
+ I2C_WRITE_REG(sc, OMAP3_I2C_STAT, 0xffff);
+
+ return 0;
+}
+
+static int
+omap3_i2c_stat(struct omap3_i2c_softc *sc)
+{
+ uint16_t v;
+ int retry = 10;
+
+ while (--retry > 0) {
+ v = I2C_READ_REG(sc, OMAP3_I2C_STAT);
+ if ((v & (OMAP3_I2C_STAT_ROVR|OMAP3_I2C_STAT_XUDF|
+ OMAP3_I2C_STAT_XRDY|OMAP3_I2C_STAT_RRDY|
+ OMAP3_I2C_STAT_ARDY|OMAP3_I2C_STAT_NACK|
+ OMAP3_I2C_STAT_AL)) != 0)
+ break;
+ delay(1000);
+ }
+
+ return v;
+}
+
+static int
+omap3_i2c_flush(struct omap3_i2c_softc *sc)
+{
+ int retry = 1000;
+ uint16_t v;
+
+ while ((v = I2C_READ_REG(sc, OMAP3_I2C_STAT)) & OMAP3_I2C_STAT_RRDY) {
+ if (--retry == 0) {
+ printf("%s: flush timeout, stat = %#x\n",
+ device_xname(sc->sc_dev), v);
+ return EBUSY;
+ }
+ (void)I2C_READ_DATA(sc);
+ I2C_WRITE_REG(sc, OMAP3_I2C_STAT, OMAP3_I2C_STAT_RRDY);
+ delay(1000);
+ }
+
+ I2C_WRITE_REG(sc, OMAP3_I2C_STAT, 0xffff);
+ I2C_WRITE_REG(sc, OMAP3_I2C_CNT, 0);
+
+ return 0;
+}
Index: src/sys/arch/arm/omap/omap3_i2creg.h
diff -u /dev/null src/sys/arch/arm/omap/omap3_i2creg.h:1.1
--- /dev/null Mon Dec 31 12:45:50 2012
+++ src/sys/arch/arm/omap/omap3_i2creg.h Mon Dec 31 12:45:49 2012
@@ -0,0 +1,209 @@
+/* $NetBSD: omap3_i2creg.h,v 1.1 2012/12/31 12:45:49 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2012 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _OMAP3_I2CREG_H
+#define _OMAP3_I2CREG_H
+
+/*
+ * High-Speed I2C Controller registers
+ */
+
+#define OMAP3_I2C_REV 0x00 /* IP revision code */
+#define OMAP3_I2C_REV_MAJ_MASK __BITS(4,7)
+#define OMAP3_I2C_REV_MAJ_SHIFT 4
+#define OMAP3_I2C_REV_MIN_MASK __BITS(0,3)
+#define OMAP3_I2C_REV_MIN_SHIFT 0
+
+#define OMAP3_I2C_IE 0x04 /* Interrupt enable */
+#define OMAP3_I2C_IE_XDR_IE __BIT(14)
+#define OMAP3_I2C_IE_RDR_IE __BIT(13)
+#define OMAP3_I2C_IE_AAS_IE __BIT(9)
+#define OMAP3_I2C_IE_BF_IE __BIT(8)
+#define OMAP3_I2C_IE_AERR_IE __BIT(7)
+#define OMAP3_I2C_IE_STC_IE __BIT(6)
+#define OMAP3_I2C_IE_GC_IE __BIT(5)
+#define OMAP3_I2C_IE_XRDY_IE __BIT(4)
+#define OMAP3_I2C_IE_RRDY_IE __BIT(3)
+#define OMAP3_I2C_IE_ARDY_IE __BIT(2)
+#define OMAP3_I2C_IE_NACK_IE __BIT(1)
+#define OMAP3_I2C_IE_AL_IE __BIT(0)
+
+#define OMAP3_I2C_STAT 0x08 /* Interrupt status */
+#define OMAP3_I2C_STAT_XDR __BIT(14)
+#define OMAP3_I2C_STAT_RDR __BIT(13)
+#define OMAP3_I2C_STAT_BB __BIT(12)
+#define OMAP3_I2C_STAT_ROVR __BIT(11)
+#define OMAP3_I2C_STAT_XUDF __BIT(10)
+#define OMAP3_I2C_STAT_AAS __BIT(9)
+#define OMAP3_I2C_STAT_BF __BIT(8)
+#define OMAP3_I2C_STAT_AERR __BIT(7)
+#define OMAP3_I2C_STAT_STC __BIT(6)
+#define OMAP3_I2C_STAT_GC __BIT(5)
+#define OMAP3_I2C_STAT_XRDY __BIT(4)
+#define OMAP3_I2C_STAT_RRDY __BIT(3)
+#define OMAP3_I2C_STAT_ARDY __BIT(2)
+#define OMAP3_I2C_STAT_NACK __BIT(1)
+#define OMAP3_I2C_STAT_AL __BIT(0)
+
+#define OMAP3_I2C_WE 0x0c /* Wakeup enable */
+#define OMAP3_I2C_WE_XDR_WE __BIT(14)
+#define OMAP3_I2C_WE_RDR_WE __BIT(13)
+#define OMAP3_I2C_WE_AAS_WE __BIT(9)
+#define OMAP3_I2C_WE_BF_WE __BIT(8)
+#define OMAP3_I2C_WE_STC_WE __BIT(6)
+#define OMAP3_I2C_WE_GC_WE __BIT(5)
+#define OMAP3_I2C_WE_DRDY_WE __BIT(3)
+#define OMAP3_I2C_WE_ARDY_WE __BIT(2)
+#define OMAP3_I2C_WE_NACK_WE __BIT(1)
+#define OMAP3_I2C_WE_AL_WE __BIT(0)
+
+#define OMAP3_I2C_SYSS 0x10 /* Non-interrupt status */
+#define OMAP3_I2C_SYSS_RDONE __BIT(0)
+
+#define OMAP3_I2C_BUF 0x14 /* Receive DMA channel disabled */
+#define OMAP3_I2C_BUF_RDMA_EN __BIT(15)
+#define OMAP3_I2C_BUF_RXFIFO_CLR __BIT(14)
+#define OMAP3_I2C_BUF_RTRSH_MASK __BITS(8,13)
+#define OMAP3_I2C_BUF_RTRSH_SHIFT 8
+#define OMAP3_I2C_BUF_XDMA_EN __BIT(7)
+#define OMAP3_I2C_BUF_TXFIFO_CLR __BIT(6)
+#define OMAP3_I2C_BUF_XTRSH_MASK __BITS(0,5)
+#define OMAP3_I2C_BUF_XTRSH_SHIFT 0
+
+#define OMAP3_I2C_CNT 0x18 /* Number of bytes in I2C payload */
+#define OMAP3_I2C_CNT_DCOUNT_MASK __BITS(0,15)
+#define OMAP3_I2C_CNT_DCOUNT_SHIFT 0
+
+#define OMAP3_I2C_DATA 0x1c /* FIFO buffer */
+#define OMAP3_I2C_DATA_DATA_MASK __BITS(0,7)
+#define OMAP3_I2C_DATA_DATA_SHIFT 0
+
+#define OMAP3_I2C_SYSC 0x20 /* L4-Core interconnect control */
+#define OMAP3_I2C_CLOCKACTIVITY_MASK __BITS(8,9)
+#define OMAP3_I2C_CLOCKACTIVITY_SHIFT 8
+#define OMAP3_I2C_CLOCKACTIVITY_DIS 0x0
+#define OMAP3_I2C_CLOCKACTIVITY_ICLK_EN 0x1
+#define OMAP3_I2C_CLOCKACTIVITY_FCLK_EN 0x2
+#define OMAP3_I2C_CLOCKACTIVITY_ICLK_FCLK_EN 0x3
+#define OMAP3_I2C_IDLEMODE_MASK __BITS(3,4)
+#define OMAP3_I2C_IDLEMODE_SHIFT 3
+#define OMAP3_I2C_IDLEMODE_FORCEIDLE 0x0
+#define OMAP3_I2C_IDLEMODE_NOIDLE 0x1
+#define OMAP3_I2C_IDLEMODE_SMARTIDLE 0x2
+#define OMAP3_I2C_ENAWAKEUP __BIT(2)
+#define OMAP3_I2C_SRST __BIT(1)
+#define OMAP3_I2C_AUTOIDLE __BIT(0)
+
+#define OMAP3_I2C_CON 0x24 /* Function control */
+#define OMAP3_I2C_CON_I2C_EN __BIT(15)
+#define OMAP3_I2C_CON_OPMODE_MASK __BITS(12,13)
+#define OMAP3_I2C_CON_OPMODE_SHIFT 12
+#define OMAP3_I2C_CON_OPMODE_FASTSTD 0x0
+#define OMAP3_I2C_CON_OPMODE_HS 0x1
+#define OMAP3_I2C_CON_OPMODE_SCCB 0x2
+#define OMAP3_I2C_CON_STB __BIT(11)
+#define OMAP3_I2C_CON_MST __BIT(10)
+#define OMAP3_I2C_CON_TRX __BIT(9)
+#define OMAP3_I2C_CON_XSA __BIT(8)
+#define OMAP3_I2C_CON_XOA0 __BIT(7)
+#define OMAP3_I2C_CON_XOA1 __BIT(6)
+#define OMAP3_I2C_CON_XOA2 __BIT(5)
+#define OMAP3_I2C_CON_XOA3 __BIT(4)
+#define OMAP3_I2C_CON_STP __BIT(1)
+#define OMAP3_I2C_CON_STT __BIT(0)
+
+#define OMAP3_I2C_OA0 0x28 /* Own address 0 */
+#define OMAP3_I2C_OA0_MCODE_MASK __BITS(13,15)
+#define OMAP3_I2C_OA0_MCODE_SHIFT 13
+#define OMAP3_I2C_OA0_OA_MASK __BITS(0,9)
+#define OMAP3_I2C_OA0_OA_SHIFT 0
+
+#define OMAP3_I2C_SA 0x2c /* Slave address */
+#define OMAP3_I2C_SA_MASK __BITS(0,9)
+#define OMAP3_I2C_SA_SHIFT 0
+
+#define OMAP3_I2C_PSC 0x30 /* Prescale sampling clock */
+#define OMAP3_I2C_PSC_MASK __BITS(0,7)
+#define OMAP3_I2C_PSC_SHIFT 0
+
+#define OMAP3_I2C_SCLL 0x34 /* SCL low time (master) */
+#define OMAP3_I2C_SCLL_HSSCLL_MASK __BITS(8,15)
+#define OMAP3_I2C_SCLL_HSSCLL_SHIFT 8
+#define OMAP3_I2C_SCLL_SCLL_MASK __BITS(0,7)
+#define OMAP3_I2C_SCLL_SCLL_SHIFT 0
+
+#define OMAP3_I2C_SCLH 0x38 /* SCL high time (master) */
+#define OMAP3_I2C_SCLH_HSSCLH_MASK __BITS(8,15)
+#define OMAP3_I2C_SCLH_HSSCLH_SHIFT 8
+#define OMAP3_I2C_SCLH_SCLH_MASK __BITS(0,7)
+#define OMAP3_I2C_SCLH_SCLH_SHIFT 0
+
+#define OMAP3_I2C_SYSTEST 0x3c /* System tests */
+#define OMAP3_I2C_SYSTEST_ST_EN __BIT(15)
+#define OMAP3_I2C_SYSTEST_FREE __BIT(14)
+#define OMAP3_I2C_SYSTEST_TMODE_MASK __BITS(12,13)
+#define OMAP3_I2C_SYSTEST_TMODE_SHIFT 12
+#define OMAP3_I2C_SYSTEST_SSB __BIT(11)
+#define OMAP3_I2C_SYSTEST_SCCBE_O __BIT(4)
+#define OMAP3_I2C_SYSTEST_SCL_I __BIT(3)
+#define OMAP3_I2C_SYSTEST_SCL_O __BIT(2)
+#define OMAP3_I2C_SYSTEST_SDA_I __BIT(1)
+#define OMAP3_I2C_SYSTEST_SDA_O __BIT(0)
+
+#define OMAP3_I2C_BUFSTAT 0x40 /* FIFO status */
+#define OMAP3_I2C_BUFSTAT_FIFODEPTH_MASK __BITS(14,15)
+#define OMAP3_I2C_BUFSTAT_FIFODEPTH_SHIFT 14
+#define OMAP3_I2C_BUFSTAT_RXSTAT_MASK __BITS(8,13)
+#define OMAP3_I2C_BUFSTAT_RXSTAT_SHIFT 8
+#define OMAP3_I2C_BUFSTAT_TXSTAT_MASK __BITS(0,5)
+#define OMAP3_I2C_BUFSTAT_TXSTAT_SHIFT 0
+
+#define OMAP3_I2C_OA1 0x44 /* Own address 1 */
+#define OMAP3_I2C_OA1_OA_MASK __BITS(0,9)
+#define OMAP3_I2C_OA1_OA_SHIFT 0
+
+#define OMAP3_I2C_OA2 0x48 /* Own address 2 */
+#define OMAP3_I2C_OA2_OA_MASK __BITS(0,9)
+#define OMAP3_I2C_OA2_OA_SHIFT 0
+
+#define OMAP3_I2C_OA3 0x4c /* Own address 3 */
+#define OMAP3_I2C_OA3_OA_MASK __BITS(0,9)
+#define OMAP3_I2C_OA3_OA_SHIFT 0
+
+#define OMAP3_I2C_ACTOA 0x50 /* Active own addresses (slave) */
+#define OMAP3_I2C_ACTOA_OA3_ACT __BIT(3)
+#define OMAP3_I2C_ACTOA_OA2_ACT __BIT(2)
+#define OMAP3_I2C_ACTOA_OA1_ACT __BIT(1)
+#define OMAP3_I2C_ACTOA_OA0_ACT __BIT(0)
+
+#define OMAP3_I2C_SBLOCK 0x54 /* Bus locking (slave) */
+#define OMAP3_I2C_SBLOCK_OA3_EN __BIT(3)
+#define OMAP3_I2C_SBLOCK_OA2_EN __BIT(2)
+#define OMAP3_I2C_SBLOCK_OA1_EN __BIT(1)
+#define OMAP3_I2C_SBLOCK_OA0_EN __BIT(0)
+
+#endif /* !_OMAP3_I2CREG_H */
