Module Name: src
Committed By: tsutsui
Date: Sat Jan 12 07:04:58 UTC 2013
Modified Files:
src/sys/arch/luna68k/stand/boot: sio.c sioreg.h
Log Message:
Make sure to enable DTR and RTS on TX initialization for SIO console.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/luna68k/stand/boot/sio.c \
src/sys/arch/luna68k/stand/boot/sioreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/luna68k/stand/boot/sio.c
diff -u src/sys/arch/luna68k/stand/boot/sio.c:1.1 src/sys/arch/luna68k/stand/boot/sio.c:1.2
--- src/sys/arch/luna68k/stand/boot/sio.c:1.1 Sat Jan 5 17:44:24 2013
+++ src/sys/arch/luna68k/stand/boot/sio.c Sat Jan 12 07:04:57 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: sio.c,v 1.1 2013/01/05 17:44:24 tsutsui Exp $ */
+/* $NetBSD: sio.c,v 1.2 2013/01/12 07:04:57 tsutsui Exp $ */
/*
* Copyright (c) 1992 OMRON Corporation.
@@ -220,7 +220,7 @@ sioinit(void)
sioreg(REG(0, WR0), WR0_RSTINT); /* Reset E/S Interrupt */
sioreg(REG(0, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY); /* Tx/Rx */
sioreg(REG(0, WR3), WR3_RX8BIT | WR3_RXENBL); /* Rx */
- sioreg(REG(0, WR5), WR5_TX8BIT | WR5_TXENBL); /* Tx */
+ sioreg(REG(0, WR5), WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS); /* Tx */
sioreg(REG(0, WR0), WR0_RSTINT); /* Reset E/S Interrupt */
sioreg(REG(0, WR1), WR1_RXALLS); /* Interrupted All Char. */
Index: src/sys/arch/luna68k/stand/boot/sioreg.h
diff -u src/sys/arch/luna68k/stand/boot/sioreg.h:1.1 src/sys/arch/luna68k/stand/boot/sioreg.h:1.2
--- src/sys/arch/luna68k/stand/boot/sioreg.h:1.1 Sat Jan 5 17:44:24 2013
+++ src/sys/arch/luna68k/stand/boot/sioreg.h Sat Jan 12 07:04:57 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: sioreg.h,v 1.1 2013/01/05 17:44:24 tsutsui Exp $ */
+/* $NetBSD: sioreg.h,v 1.2 2013/01/12 07:04:57 tsutsui Exp $ */
/*
* Copyright (c) 1992 OMRON Corporation.
@@ -153,13 +153,14 @@ struct siodevice {
#define WR4_BAUD24 0xc0 /* Clock Rate (2400 BAUD) */
#define WR5_TXCRC 0x01 /* Tx CRC Check */
-#define WR5_REQSND 0x02 /* Request To Send (LOW) */
+#define WR5_RTS 0x02 /* Request To Send [RTS] */
#define WR5_TXENBL 0x08 /* Transmit Enable */
#define WR5_BREAK 0x10 /* Send Break */
#define WR5_TX5BIT 0x00 /* Tx Bits/Character: 5 Bits */
#define WR5_TX7BIT 0x20 /* Tx Bits/Character: 7 Bits */
#define WR5_TX6BIT 0x40 /* Tx Bits/Character: 6 Bits */
#define WR5_TX8BIT 0x60 /* Tx Bits/Character: 8 Bits */
+#define WR5_DTR 0x80 /* Data Terminal Ready [DTR] */
#define RR0_RXAVAIL 0x01 /* Rx Character Available */
#define RR0_INTRPEND 0x02 /* Interrupt Pending (Channel-A Only) */
