Module Name: src
Committed By: msaitoh
Date: Thu Apr 11 10:10:42 UTC 2013
Modified Files:
src/sys/dev/pci: if_bgereg.h
Log Message:
Add BGE_PCIMISCCTL_PCISTATE_RW in BGE_INIT. It's required to set the PCISTATE
register correctly.
To generate a diff of this commit:
cvs rdiff -u -r1.72 -r1.73 src/sys/dev/pci/if_bgereg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/if_bgereg.h
diff -u src/sys/dev/pci/if_bgereg.h:1.72 src/sys/dev/pci/if_bgereg.h:1.73
--- src/sys/dev/pci/if_bgereg.h:1.72 Mon Apr 8 15:55:58 2013
+++ src/sys/dev/pci/if_bgereg.h Thu Apr 11 10:10:41 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: if_bgereg.h,v 1.72 2013/04/08 15:55:58 msaitoh Exp $ */
+/* $NetBSD: if_bgereg.h,v 1.73 2013/04/11 10:10:41 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
* Copyright (c) 1997, 1998, 1999, 2001
@@ -275,7 +275,8 @@
#define BGE_INIT \
(BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
- BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
+ BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS| \
+ BGE_PCIMISCCTL_PCISTATE_RW)
#define BGE_CHIPID_TIGON_I 0x4000
#define BGE_CHIPID_TIGON_II 0x6000
