Module Name: src
Committed By: riz
Date: Sat May 11 22:34:38 UTC 2013
Modified Files:
src/sys/dev/pci [netbsd-5]: pcireg.h ppb.c
Log Message:
Applied patch (requested by msaitoh in ticket #1844):
sys/dev/pci/pcireg.h 1.69
sys/dev/pci/ppb.c 1.44-1.45
Support PCI Express 2.0.
Print version and device/port type information
[msaitoh, ticket #1844]
To generate a diff of this commit:
cvs rdiff -u -r1.57.20.1 -r1.57.20.2 src/sys/dev/pci/pcireg.h
cvs rdiff -u -r1.39 -r1.39.10.1 src/sys/dev/pci/ppb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.57.20.1 src/sys/dev/pci/pcireg.h:1.57.20.2
--- src/sys/dev/pci/pcireg.h:1.57.20.1 Fri Nov 19 23:40:28 2010
+++ src/sys/dev/pci/pcireg.h Sat May 11 22:34:38 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.57.20.1 2010/11/19 23:40:28 riz Exp $ */
+/* $NetBSD: pcireg.h,v 1.57.20.2 2013/05/11 22:34:38 riz Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -540,6 +540,17 @@ typedef u_int8_t pci_revision_t;
* PCI Express; access via capability pointer.
*/
#define PCI_PCIE_XCAP 0x00
+#define PCI_PCIE_XCAP_VER_MASK 0x000f0000
+#define PCI_PCIE_XCAP_VER_1_0 0x00010000
+#define PCI_PCIE_XCAP_VER_2_0 0x00020000
+#define PCI_PCIE_XCAP_TYPE_MASK 0x00f00000
+#define PCI_PCIE_XCAP_TYPE_PCIE_DEV 0x00000000
+#define PCI_PCIE_XCAP_TYPE_PCI_DEV 0x00100000
+#define PCI_PCIE_XCAP_TYPE_ROOT 0x00400000
+#define PCI_PCIE_XCAP_TYPE_UP 0x00500000
+#define PCI_PCIE_XCAP_TYPE_DOWN 0x00600000
+#define PCI_PCIE_XCAP_TYPE_PCIE2PCI 0x00700000
+#define PCI_PCIE_XCAP_TYPE_PCI2PCIE 0x00800000
#define PCI_PCIE_XCAP_SI 0x01000000
#define PCI_PCIE_DCAP 0x04
#define PCI_PCIE_DCSR 0x08
Index: src/sys/dev/pci/ppb.c
diff -u src/sys/dev/pci/ppb.c:1.39 src/sys/dev/pci/ppb.c:1.39.10.1
--- src/sys/dev/pci/ppb.c:1.39 Sat May 3 05:44:06 2008
+++ src/sys/dev/pci/ppb.c Sat May 11 22:34:38 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: ppb.c,v 1.39 2008/05/03 05:44:06 cegger Exp $ */
+/* $NetBSD: ppb.c,v 1.39.10.1 2013/05/11 22:34:38 riz Exp $ */
/*
* Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.39 2008/05/03 05:44:06 cegger Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.39.10.1 2013/05/11 22:34:38 riz Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -43,6 +43,10 @@ __KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.39
#include <dev/pci/ppbreg.h>
#include <dev/pci/pcidevs.h>
+#define PCI_PCIE_SLCSR_NOTIFY_MASK \
+ (PCI_PCIE_SLCSR_ABE | PCI_PCIE_SLCSR_PFE | PCI_PCIE_SLCSR_MSE | \
+ PCI_PCIE_SLCSR_PDE | PCI_PCIE_SLCSR_CCE | PCI_PCIE_SLCSR_HPE)
+
struct ppb_softc {
device_t sc_dev; /* generic device glue */
pci_chipset_tag_t sc_pc; /* our PCI chipset... */
@@ -72,7 +76,7 @@ ppbmatch(device_t parent, cfdata_t match
}
static void
-ppb_fix_pcix(device_t self)
+ppb_fix_pcie(device_t self)
{
struct ppb_softc *sc = device_private(self);
pcireg_t reg;
@@ -82,15 +86,55 @@ ppb_fix_pcix(device_t self)
&off, ®))
return; /* Not a PCIe device */
- if ((reg & 0x000f0000) != 0x00010000) {
- aprint_normal_dev(self, "unsupported PCI Express version\n");
+ aprint_normal_dev(self, "PCI Express ");
+ switch (reg & PCI_PCIE_XCAP_VER_MASK) {
+ case PCI_PCIE_XCAP_VER_1_0:
+ aprint_normal("1.0");
+ break;
+ case PCI_PCIE_XCAP_VER_2_0:
+ aprint_normal("2.0");
+ break;
+ default:
+ aprint_normal_dev(self, "version unsupported (0x%x)\n",
+ (reg & PCI_PCIE_XCAP_VER_MASK) >> 16);
return;
}
- reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + 0x18);
- if (reg & 0x003f) {
- aprint_normal_dev(self, "disabling notification events\n");
- reg &= ~0x003f;
- pci_conf_write(sc->sc_pc, sc->sc_tag, off + 0x18, reg);
+ aprint_normal(" <");
+ switch (reg & PCI_PCIE_XCAP_TYPE_MASK) {
+ case PCI_PCIE_XCAP_TYPE_PCIE_DEV:
+ aprint_normal("PCI-E Endpoint device");
+ break;
+ case PCI_PCIE_XCAP_TYPE_PCI_DEV:
+ aprint_normal("Legacy PCI-E Endpoint device");
+ break;
+ case PCI_PCIE_XCAP_TYPE_ROOT:
+ aprint_normal("Root Port of PCI-E Root Complex");
+ break;
+ case PCI_PCIE_XCAP_TYPE_UP:
+ aprint_normal("Upstream Port of PCI-E Switch");
+ break;
+ case PCI_PCIE_XCAP_TYPE_DOWN:
+ aprint_normal("Downstream Port of PCI-E Switch");
+ break;
+ case PCI_PCIE_XCAP_TYPE_PCIE2PCI:
+ aprint_normal("PCI-E to PCI/PCI-X Bridge");
+ break;
+ case PCI_PCIE_XCAP_TYPE_PCI2PCIE:
+ aprint_normal("PCI/PCI-X to PCI-E Bridge");
+ break;
+ default:
+ aprint_normal("Device/Port Type 0x%x",
+ (reg & PCI_PCIE_XCAP_TYPE_MASK) >> 20);
+ break;
+ }
+ aprint_normal(">\n");
+
+ reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCI_PCIE_SLCSR);
+ if (reg & PCI_PCIE_SLCSR_NOTIFY_MASK) {
+ aprint_debug_dev(self, "disabling notification events\n");
+ reg &= ~PCI_PCIE_SLCSR_NOTIFY_MASK;
+ pci_conf_write(sc->sc_pc, sc->sc_tag,
+ off + PCI_PCIE_SLCSR, reg);
}
}
@@ -120,7 +164,7 @@ ppbattach(device_t parent, device_t self
return;
}
- ppb_fix_pcix(self);
+ ppb_fix_pcie(self);
#if 0
/*
@@ -182,7 +226,7 @@ ppb_resume(device_t dv PMF_FN_ARGS)
sc->sc_pciconfext[(off - 0x40)/4]);
}
- ppb_fix_pcix(dv);
+ ppb_fix_pcie(dv);
return true;
}
