Module Name: src
Committed By: matt
Date: Thu Jun 20 05:30:21 UTC 2013
Modified Files:
src/sys/arch/arm/cortex: a9tmr.c a9tmr_var.h armperiph.c gic.c gtmr.c
gtmr_var.h mpcore_var.h
Log Message:
Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.
Modify the list of devices to include the offset(s) from PERIPHBASE.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/a9tmr.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/a9tmr_var.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/armperiph.c \
src/sys/arch/arm/cortex/gic.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/gtmr.c \
src/sys/arch/arm/cortex/gtmr_var.h src/sys/arch/arm/cortex/mpcore_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9tmr.c
diff -u src/sys/arch/arm/cortex/a9tmr.c:1.5 src/sys/arch/arm/cortex/a9tmr.c:1.6
--- src/sys/arch/arm/cortex/a9tmr.c:1.5 Wed Jun 12 00:59:50 2013
+++ src/sys/arch/arm/cortex/a9tmr.c Thu Jun 20 05:30:21 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: a9tmr.c,v 1.5 2013/06/12 00:59:50 matt Exp $ */
+/* $NetBSD: a9tmr.c,v 1.6 2013/06/20 05:30:21 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.5 2013/06/12 00:59:50 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.6 2013/06/20 05:30:21 matt Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -123,9 +123,7 @@ a9tmr_attach(device_t parent, device_t s
* This runs at the ARM PERIPHCLOCK which should be 1/2 of the CPU clock.
* The MD code should have setup our frequency for us.
*/
- prop_number_t pn = prop_dictionary_get(dict, "frequency");
- KASSERT(pn != NULL);
- sc->sc_freq = prop_number_unsigned_integer_value(pn);
+ prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq);
humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000);
Index: src/sys/arch/arm/cortex/a9tmr_var.h
diff -u src/sys/arch/arm/cortex/a9tmr_var.h:1.2 src/sys/arch/arm/cortex/a9tmr_var.h:1.3
--- src/sys/arch/arm/cortex/a9tmr_var.h:1.2 Thu Sep 27 00:23:27 2012
+++ src/sys/arch/arm/cortex/a9tmr_var.h Thu Jun 20 05:30:21 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: a9tmr_var.h,v 1.2 2012/09/27 00:23:27 matt Exp $ */
+/* $NetBSD: a9tmr_var.h,v 1.3 2013/06/20 05:30:21 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -39,7 +39,7 @@ struct a9tmr_softc {
bus_space_handle_t sc_private_memh;
bus_space_handle_t sc_wdog_memh;
struct evcnt sc_ev_missing_ticks;
- u_long sc_freq;
+ uint32_t sc_freq;
u_long sc_autoinc;
void *sc_global_ih;
};
Index: src/sys/arch/arm/cortex/armperiph.c
diff -u src/sys/arch/arm/cortex/armperiph.c:1.3 src/sys/arch/arm/cortex/armperiph.c:1.4
--- src/sys/arch/arm/cortex/armperiph.c:1.3 Sun Jun 16 16:44:39 2013
+++ src/sys/arch/arm/cortex/armperiph.c Thu Jun 20 05:30:21 2013
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.3 2013/06/16 16:44:39 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.4 2013/06/20 05:30:21 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -52,41 +52,59 @@ struct armperiph_softc {
bus_space_handle_t sc_memh;
};
+struct armperiph_info {
+ const char pi_name[12];
+ bus_size_t pi_off1;
+ bus_size_t pi_off2;
+};
+
#ifdef CPU_CORTEXA5
-static const char * const a5_devices[] = {
- "armscu", "armgic", NULL
+static const struct armperiph_info a5_devices[] = {
+ { "armscu", 0x0000, 0 },
+ { "armgic", 0x1000, 0x0100 },
+ { "a9tmr", 0x0200, 0 },
+ { "", 0, 0 },
};
#endif
#ifdef CPU_CORTEXA7
-static const char * const a7_devices[] = {
- "armgic", "armtmr", NULL
+static const struct armperiph_info a7_devices[] = {
+ { "armgic", 0x1000, 0x2000 },
+ { "armgtmr", 0, 0 },
+ { "", 0, 0 },
};
#endif
#ifdef CPU_CORTEXA9
-static const char * const a9_devices[] = {
- "armscu", "arml2cc", "armgic", "a9tmr", "a9wdt", NULL
+static const struct armperiph_info a9_devices[] = {
+ { "armscu", 0x0000, 0 },
+ { "arml2cc", 0x2000, 0 },
+ { "armgic", 0x1000, 0x0100 },
+ { "a9tmr", 0x0200, 0 },
+ { "a9wdt", 0x0600, 0 },
+ { "", 0, 0 },
};
#endif
#ifdef CPU_CORTEXA15
-static const char * const a15_devices[] = {
- "armgic", "armtmr", NULL
+static const struct armperiph_info a15_devices[] = {
+ { "armgic", 0x1000, 0x2000 },
+ { "armgtmr", 0, 0 },
+ { "", 0, 0 },
};
#endif
static const struct mpcore_config {
- const char * const *cfg_devices;
+ const struct armperiph_info *cfg_devices;
uint32_t cfg_cpuid;
uint32_t cfg_cbar_size;
} configs[] = {
#ifdef CPU_CORTEXA5
- { a5_devices, 0x410fc050, 8192 },
+ { a5_devices, 0x410fc050, 2*4096 },
#endif
#ifdef CPU_CORTEXA7
- { a7_devices, 0x410fc070, 32768 },
+ { a7_devices, 0x410fc070, 8*4096 },
#endif
#ifdef CPU_CORTEXA9
{ a9_devices, 0x410fc090, 3*4096 },
@@ -172,11 +190,13 @@ armperiph_attach(device_t parent, device
/*
* Let's try to attach any children we may have.
*/
- for (size_t i = 0; cfg->cfg_devices[i] != NULL; i++) {
+ for (size_t i = 0; cfg->cfg_devices[i].pi_name[0] != 0; i++) {
struct mpcore_attach_args mpcaa = {
- .mpcaa_name = cfg->cfg_devices[i],
+ .mpcaa_name = cfg->cfg_devices[i].pi_name,
.mpcaa_memt = sc->sc_memt,
.mpcaa_memh = sc->sc_memh,
+ .mpcaa_off1 = cfg->cfg_devices[i].pi_off1,
+ .mpcaa_off2 = cfg->cfg_devices[i].pi_off2,
};
config_found(self, &mpcaa, NULL);
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.3 src/sys/arch/arm/cortex/gic.c:1.4
--- src/sys/arch/arm/cortex/gic.c:1.3 Sun Sep 16 22:09:34 2012
+++ src/sys/arch/arm/cortex/gic.c Thu Jun 20 05:30:21 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.3 2012/09/16 22:09:34 rmind Exp $ */
+/* $NetBSD: gic.c,v 1.4 2013/06/20 05:30:21 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.3 2012/09/16 22:09:34 rmind Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.4 2013/06/20 05:30:21 matt Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -86,7 +86,8 @@ static struct armgic_softc {
struct pic_softc sc_pic;
device_t sc_dev;
bus_space_tag_t sc_memt;
- bus_space_handle_t sc_memh;
+ bus_space_handle_t sc_gicch;
+ bus_space_handle_t sc_gicdh;
size_t sc_gic_lines;
uint32_t sc_gic_type;
uint32_t sc_gic_valid_lines[1024/32];
@@ -108,7 +109,7 @@ __CTASSERT(NIPL == 8);
static inline uint32_t
gicc_read(struct armgic_softc *sc, bus_size_t o)
{
- uint32_t v = bus_space_read_4(sc->sc_memt, sc->sc_memh, GICC_BASE + o);
+ uint32_t v = bus_space_read_4(sc->sc_memt, sc->sc_gicch, o);
return le32toh(v);
}
@@ -116,13 +117,13 @@ static inline void
gicc_write(struct armgic_softc *sc, bus_size_t o, uint32_t v)
{
v = htole32(v);
- bus_space_write_4(sc->sc_memt, sc->sc_memh, GICC_BASE + o, v);
+ bus_space_write_4(sc->sc_memt, sc->sc_gicch, o, v);
}
static inline uint32_t
gicd_read(struct armgic_softc *sc, bus_size_t o)
{
- uint32_t v = bus_space_read_4(sc->sc_memt, sc->sc_memh, GICD_BASE + o);
+ uint32_t v = bus_space_read_4(sc->sc_memt, sc->sc_gicdh, o);
return le32toh(v);
}
@@ -130,7 +131,7 @@ static inline void
gicd_write(struct armgic_softc *sc, bus_size_t o, uint32_t v)
{
v = htole32(v);
- bus_space_write_4(sc->sc_memt, sc->sc_memh, GICD_BASE + o, v);
+ bus_space_write_4(sc->sc_memt, sc->sc_gicdh, o, v);
}
/*
@@ -454,9 +455,7 @@ armgic_match(device_t parent, cfdata_t c
if (strcmp(cf->cf_name, mpcaa->mpcaa_name) != 0)
return 0;
- if (!CPU_ID_CORTEX_P(cputype))
- return 0;
- if (CPU_ID_CORTEX_A8_P(cputype))
+ if (!CPU_ID_CORTEX_P(cputype) || CPU_ID_CORTEX_A8_P(cputype))
return 0;
return 1;
@@ -472,7 +471,10 @@ armgic_attach(device_t parent, device_t
self->dv_private = sc;
sc->sc_memt = mpcaa->mpcaa_memt; /* provided for us */
- sc->sc_memh = mpcaa->mpcaa_memh; /* provided for us */
+ bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, mpcaa->mpcaa_off1,
+ 4096, &sc->sc_gicdh);
+ bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, mpcaa->mpcaa_off2,
+ 4096, &sc->sc_gicch);
sc->sc_gic_type = gicd_read(sc, GICD_TYPER);
sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(sc->sc_gic_type);
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.1 src/sys/arch/arm/cortex/gtmr.c:1.2
--- src/sys/arch/arm/cortex/gtmr.c:1.1 Sun Jun 16 16:44:39 2013
+++ src/sys/arch/arm/cortex/gtmr.c Thu Jun 20 05:30:21 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.1 2013/06/16 16:44:39 matt Exp $ */
+/* $NetBSD: gtmr.c,v 1.2 2013/06/20 05:30:21 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.1 2013/06/16 16:44:39 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.2 2013/06/20 05:30:21 matt Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -91,12 +91,13 @@ static void
gtmr_attach(device_t parent, device_t self, void *aux)
{
struct gtmr_softc *sc = >mr_sc;
- char freqbuf[sizeof("XXX SHz")];
+ prop_dictionary_t dict = device_properties(self);
+ char freqbuf[sizeof("X.XXX SHz")];
/*
* This runs at a fixed frequency of 1 to 50MHz.
*/
- sc->sc_freq = armreg_cnt_frq_read();
+ prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq);
humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000);
@@ -145,7 +146,7 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
armreg_cntv_ctl_write(ARM_CNTCTL_ENABLE);
#if 0
printf("%s: %s: ctl %#x cmp %#"PRIx64" now %#"PRIx64"\n",
- __func__, ci->ci_data.cpu_name, armreg_cntvctl_read(),
+ __func__, ci->ci_data.cpu_name, armreg_cntv_ctl_read(),
armreg_cntv_cval_read(), armreg_cntv_ct_read());
int s = splsched();
Index: src/sys/arch/arm/cortex/gtmr_var.h
diff -u src/sys/arch/arm/cortex/gtmr_var.h:1.1 src/sys/arch/arm/cortex/gtmr_var.h:1.2
--- src/sys/arch/arm/cortex/gtmr_var.h:1.1 Sun Jun 16 16:44:39 2013
+++ src/sys/arch/arm/cortex/gtmr_var.h Thu Jun 20 05:30:21 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr_var.h,v 1.1 2013/06/16 16:44:39 matt Exp $ */
+/* $NetBSD: gtmr_var.h,v 1.2 2013/06/20 05:30:21 matt Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
struct gtmr_softc {
device_t sc_dev;
struct evcnt sc_ev_missing_ticks;
- u_long sc_freq;
+ uint32_t sc_freq;
u_long sc_autoinc;
void *sc_global_ih;
};
Index: src/sys/arch/arm/cortex/mpcore_var.h
diff -u src/sys/arch/arm/cortex/mpcore_var.h:1.1 src/sys/arch/arm/cortex/mpcore_var.h:1.2
--- src/sys/arch/arm/cortex/mpcore_var.h:1.1 Sat Sep 1 00:03:14 2012
+++ src/sys/arch/arm/cortex/mpcore_var.h Thu Jun 20 05:30:21 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: mpcore_var.h,v 1.1 2012/09/01 00:03:14 matt Exp $ */
+/* $NetBSD: mpcore_var.h,v 1.2 2013/06/20 05:30:21 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -35,6 +35,8 @@ struct mpcore_attach_args {
const char *mpcaa_name;
bus_space_tag_t mpcaa_memt;
bus_space_handle_t mpcaa_memh;
+ bus_size_t mpcaa_off1;
+ bus_size_t mpcaa_off2;
};
#endif /* _ARM_CORTEX_MPCORE_VAR_H_ */
