Module Name: src
Committed By: msaitoh
Date: Thu Jul 25 16:34:29 UTC 2013
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add some new bit definitions of Structured Extended Feature Flags Enumeration
Leat from the document (Intel 64 and IA-32 Architectures Software Developer's
Manual).
To generate a diff of this commit:
cvs rdiff -u -r1.64 -r1.65 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.64 src/sys/arch/x86/include/specialreg.h:1.65
--- src/sys/arch/x86/include/specialreg.h:1.64 Thu Jul 25 16:31:33 2013
+++ src/sys/arch/x86/include/specialreg.h Thu Jul 25 16:34:29 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.64 2013/07/25 16:31:33 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.65 2013/07/25 16:34:29 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -165,6 +165,7 @@
* Fn0000_0007 main leaf - %ebx.
*/
#define CPUID_SEF_FSGSBASE __BIT(0)
+#define CPUID_SEF_TSC_ADJUST __BIT(1)
#define CPUID_SEF_BMI1 __BIT(3)
#define CPUID_SEF_HLE __BIT(4)
#define CPUID_SEF_AVX2 __BIT(5)
@@ -173,12 +174,15 @@
#define CPUID_SEF_ERMS __BIT(9)
#define CPUID_SEF_INVPCID __BIT(10)
#define CPUID_SEF_RTM __BIT(11)
+#define CPUID_SEF_QM __BIT(12)
+#define CPUID_SEF_FPUCSDS __BIT(13)
#define CPUID_SEF_RDSEED __BIT(18)
#define CPUID_SEF_ADX __BIT(19)
#define CPUID_SEF_SMAP __BIT(20)
#define CPUID_SEF_FLAGS "\20" \
"\1" "FSGSBASE" \
+ "\2" "TSCADJUST" \
"\4" "BMI1" \
"\5" "HLE" \
"\6" "AVX2" \
@@ -187,6 +191,8 @@
"\12" "ERMS" \
"\13" "INVPCID" \
"\14" "RTM" \
+ "\15" "QM" \
+ "\16" "FPUCSDS" \
"\23" "RDSEED" \
"\24" "ADX" \
"\25" "SMAP"
