Module Name: src
Committed By: matt
Date: Fri Aug 2 01:59:00 UTC 2013
Modified Files:
src/sys/arch/arm/include: vfpreg.h
Log Message:
Add VFP_FPSCR_{QC,AHP} bits
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/include/vfpreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/vfpreg.h
diff -u src/sys/arch/arm/include/vfpreg.h:1.9 src/sys/arch/arm/include/vfpreg.h:1.10
--- src/sys/arch/arm/include/vfpreg.h:1.9 Thu Jun 20 05:24:46 2013
+++ src/sys/arch/arm/include/vfpreg.h Fri Aug 2 01:59:00 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: vfpreg.h,v 1.9 2013/06/20 05:24:46 matt Exp $ */
+/* $NetBSD: vfpreg.h,v 1.10 2013/08/02 01:59:00 matt Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -84,6 +84,8 @@
#define VFP_FPSCR_Z 0x40000000 /* set if compare = result */
#define VFP_FPSCR_C 0x20000000 /* set if compare (=,>=,UNORD) result */
#define VFP_FPSCR_V 0x10000000 /* set if compare UNORD result */
+#define VFP_FPSCR_QC 0x08000000 /* Cumulative saturation (SIMD) */
+#define VFP_FPSCR_AHP 0x04000000 /* Alternative Half-Precision */
#define VFP_FPSCR_DN 0x02000000 /* Default NaN mode */
#define VFP_FPSCR_FZ 0x01000000 /* Flush-to-zero mode */
#define VFP_FPSCR_RMODE 0x00c00000 /* Rounding Mode */
