Module Name: src
Committed By: matt
Date: Tue Sep 3 18:02:26 UTC 2013
Added Files:
src/sys/arch/arm/allwinner: awin_intr.h awin_reg.h awin_var.h
files.awin
Log Message:
Files for allwinner a20/a10 (need to compile stuff in evbarm/cubie)
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/allwinner/awin_intr.h \
src/sys/arch/arm/allwinner/awin_reg.h \
src/sys/arch/arm/allwinner/awin_var.h \
src/sys/arch/arm/allwinner/files.awin
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/arm/allwinner/awin_intr.h
diff -u /dev/null src/sys/arch/arm/allwinner/awin_intr.h:1.1
--- /dev/null Tue Sep 3 18:02:26 2013
+++ src/sys/arch/arm/allwinner/awin_intr.h Tue Sep 3 18:02:26 2013
@@ -0,0 +1,137 @@
+/* $NetBSD: awin_intr.h,v 1.1 2013/09/03 18:02:26 matt Exp $ */
+/*-
+ * Copyright (c) 2013 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ALLWINNER_AWIN_INTR_H_
+#define _ARM_ALLWINNER_AWIN_INTR_H_
+
+#define PIC_MAXSOURCES 128
+#define PIC_MAXMAXSOURCES 256
+
+/*
+ * The Allwinner can use a generic interrupt controller so pull in that stuff.
+ */
+#include <arm/cortex/gic_intr.h>
+#include <arm/cortex/a9tmr_intr.h> /* A7/A9/A15 Timer PPIs */
+
+/*
+ * There are for the A20 but the A10 are the same but offset by 32 less.
+ */
+#define AWIN_IRQ_UART0 33
+#define AWIN_IRQ_UART1 34
+#define AWIN_IRQ_UART2 35
+#define AWIN_IRQ_UART3 36
+#define AWIN_IRQ_IR0 37
+#define AWIN_IRQ_IR1 38
+#define AWIN_IRQ_TWI0 39
+#define AWIN_IRQ_TWI1 40
+#define AWIN_IRQ_TWI2 41
+#define AWIN_IRQ_SPI0 42
+#define AWIN_IRQ_SPI1 43
+#define AWIN_IRQ_SPI2 44
+#define AWIN_IRQ_SPDIF 45
+#define AWIN_IRQ_AC97 46
+#define AWIN_IRQ_TS 47
+#define AWIN_IRQ_IIS0 48
+#define AWIN_IRQ_UART4 49
+#define AWIN_IRQ_UART5 50
+#define AWIN_IRQ_UART6 51
+#define AWIN_IRQ_UART7 52
+#define AWIN_IRQ_KEYPAD 53
+#define AWIN_IRQ_TMR0 54
+#define AWIN_IRQ_TMR1 55
+#define AWIN_IRQ_TMR2 56 /* WatchDog */
+#define AWIN_IRQ_TMR3 57
+#define AWIN_IRQ_CAN 58
+#define AWIN_IRQ_DMA 59
+#define AWIN_IRQ_PIO 60
+#define AWIN_IRQ_TP 61
+#define AWIN_IRQ_ADDC 62
+#define AWIN_IRQ_LRADC 63
+#define AWIN_IRQ_SDMMC0 64
+#define AWIN_IRQ_SDMMC1 65
+#define AWIN_IRQ_SDMMC2 66
+#define AWIN_IRQ_SDMMC3 67
+#define AWIN_IRQ_MS 68
+#define AWIN_IRQ_NAND 69
+#define AWIN_IRQ_USB0 70
+#define AWIN_IRQ_USB1 71
+#define AWIN_IRQ_USB2 72
+#define AWIN_IRQ_SCR 73
+#define AWIN_IRQ_CSI0 74
+#define AWIN_IRQ_CSI1 75
+#define AWIN_IRQ_LCD0 76
+#define AWIN_IRQ_LCD1 77
+#define AWIN_IRQ_MP 78
+#define AWIN_IRQ_DE_XE0 79
+#define AWIN_IRQ_DE_XE1 80
+#define AWIN_IRQ_PMU 81
+#define AWIN_IRQ_SPI3 82
+#define AWIN_IRQ_TZASC 83
+#define AWIN_IRQ_PATA 84
+#define AWIN_IRQ_VE 85
+#define AWIN_IRQ_SS 86
+#define AWIN_IRQ_EMAC 87
+#define AWIN_IRQ_SATA 88
+#define AWIN_IRQ__RSVD89 89
+#define AWIN_IRQ_HDMI0 90
+#define AWIN_IRQ_TVE 91
+#define AWIN_IRQ_ACE 92
+#define AWIN_IRQ_TVD 93
+#define AWIN_IRQ_PS2_0 94
+#define AWIN_IRQ_PS2_1 95
+#define AWIN_IRQ_USB3 96
+#define AWIN_IRQ_USB4 97
+#define AWIN_IRQ_PERFM 98
+#define AWIN_IRQ_TMR4 99
+#define AWIN_IRQ_TMR5 100
+#define AWIN_IRQ_GPU_GP 101
+#define AWIN_IRQ_GPU_GPMMU 102
+#define AWIN_IRQ_GPU_PP0 103
+#define AWIN_IRQ_GPU_PPMMU0 104
+#define AWIN_IRQ_GPU_PMU 105
+#define AWIN_IRQ_GPU_PP1 106
+#define AWIN_IRQ_GPU_PPMMU1 107
+#define AWIN_IRQ_GPU_RSV0 108
+#define AWIN_IRQ_GPU_RSV1 109
+#define AWIN_IRQ_GPU_RSV2 110
+#define AWIN_IRQ_GPU_RSV3 111
+#define AWIN_IRQ_GPU_RSV4 112
+#define AWIN_IRQ_HSTMR0 113
+#define AWIN_IRQ_HSTMR1 114
+#define AWIN_IRQ_HSTMR2 115
+#define AWIN_IRQ_HSTMR3 116
+#define AWIN_IRQ_GMAC 117
+#define AWIN_IRQ_HDMI1 118
+#define AWIN_IRQ_IIS1 119
+#define AWIN_IRQ_TWI3 120
+#define AWIN_IRQ_TWI4 121
+#define AWIN_IRQ_IIS2 122
+
+#endif /* _ARM_ALLWINNER_AWIN_INTR_H_ */
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u /dev/null src/sys/arch/arm/allwinner/awin_reg.h:1.1
--- /dev/null Tue Sep 3 18:02:26 2013
+++ src/sys/arch/arm/allwinner/awin_reg.h Tue Sep 3 18:02:26 2013
@@ -0,0 +1,398 @@
+/* $NetBSD */
+/*-
+ * Copyright (c) 2013 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ALLWINNER_AWIN_REG_H
+#define _ARM_ALLWINNER_AWIN_REG_H
+
+#define AWIN_CPUBIST_PBASE 0x3f501000
+#define AWIN_CPUBIST_SIZE 0x00001000
+#define AWIN_SRAM_PBASE 0x00000000
+#define AWIN_SRAM_SIZE 0x00100000 /* round to 1MB */
+#define AWIN_SRAMA1_PBASE 0x00000000
+#define AWIN_SRAMA1_SIZE 0x00004000
+#define AWIN_SRAMA2_PBASE 0x00004000
+#define AWIN_SRAMA2_SIZE 0x00004000
+#define AWIN_SRAMA3_PBASE 0x00008000
+#define AWIN_SRAMA3_SIZE 0x00003400
+#define AWIN_SRAMA4_PBASE 0x0000b400
+#define AWIN_SRAMA4_SIZE 0x00000c00
+#define AWIN_SRAMD_PBASE 0x00010000
+#define AWIN_SRAMD_SIZE 0x00001000
+#define AWIN_SRAMB_PBASE 0x00020000 /* Secure */
+#define AWIN_SRAMB_SIZE 0x00010000 /* Secure */
+
+#define AWIN_CORE_PBASE 0x01c00000
+#define AWIN_CORE_SIZE 0x00300000
+#define AWIN_SRAM_OFFSET 0x00000000
+#define AWIN_DRAM_OFFSET 0x00001000
+#define AWIN_DMA_OFFSET 0x00002000
+#define AWIN_NFC_OFFSET 0x00003000
+#define AWIN_TS_OFFSET 0x00004000
+#define AWIN_SPI0_OFFSET 0x00005000
+#define AWIN_SPI1_OFFSET 0x00006000
+#define AWIN_MS_OFFSET 0x00007000
+#define AWIN_TVD_OFFSET 0x00008000
+#define AWIN_CSI0_OFFSET 0x00009000
+#define AWIN_TVE0_OFFSET 0x0000a000
+#define AWIN_EMAC_OFFSET 0x0000b000
+#define AWIN_LCD0_OFFSET 0x0000c000
+#define AWIN_LCD1_OFFSET 0x0000d000
+#define AWIN_VE_OFFSET 0x0000e000
+#define AWIN_SDMMC0_OFFSET 0x0000f000
+#define AWIN_SDMMC1_OFFSET 0x00010000
+#define AWIN_SDMMC2_OFFSET 0x00011000
+#define AWIN_SDMMC3_OFFSET 0x00012000
+#define AWIN_USB0_OFFSET 0x00013000
+#define AWIN_USB1_OFFSET 0x00014000
+#define AWIN_SS_OFFSET 0x00015000
+#define AWIN_HDMI_OFFSET 0x00016000
+#define AWIN_SPI2_OFFSET 0x00017000
+#define AWIN_SATA_OFFSET 0x00018000 /* A20 */
+#define AWIN_PATA_OFFSET 0x00019000 /* A10 */
+#define AWIN_ACE_OFFSET 0x0001a000
+#define AWIN_TVE1_OFFSET 0x0001b000
+#define AWIN_USB2_OFFSET 0x0001c000
+#define AWIN_CSI1_OFFSET 0x0001d000
+#define AWIN_TZASC_OFFSET 0x0001e000 /* A10 */
+#define AWIN_SPI3_OFFSET 0x0001f000
+#define AWIN_CCM_OFFSET 0x00020000
+#define AWIN_INTC_OFFSET 0x00020400
+#define AWIN_PIO_OFFSET 0x00020800
+#define AWIN_TIMER_OFFSET 0x00020c00
+#define AWIN_SPDIF_OFFSET 0x00021000 /* A20 */
+#define AWIN_AC97_OFFSET 0x00021400
+#define AWIN_IR0_OFFSET 0x00021800
+#define AWIN_IR1_OFFSET 0x00021c00
+#define AWIN_IIS0_OFFSET 0x00022000
+#define AWIN_IIS1_OFFSET 0x00022400
+#define AWIN_LRADC_OFFSET 0x00022800
+#define AWIN_ADDA_OFFSET 0x00022c00
+#define AWIN_KEYPAD_OFFSET 0x00023000
+#define AWIN_TZPC_OFFSET 0x00023400 /* A10 */
+#define AWIN_SID_OFFSET 0x00023800
+#define AWIN_SJTAG_OFFSET 0x00023c00
+#define AWIN__RSVD3_OFFSET 0x00024000
+#define AWIN_IIS2_OFFSET 0x00024400
+#define AWIN__RSVD4_OFFSET 0x00024800
+#define AWIN__RSVD5_OFFSET 0x00024c00
+#define AWIN_TP_OFFSET 0x00025000
+#define AWIN_PMU_OFFSET 0x00025400
+#define AWIN__RSVD6_OFFSET 0x00025800
+#define AWIN_CPUCNF_OFFSET 0x00025c00
+#define AWIN__RSVD7_OFFSET 0x00026000
+#define AWIN__RSVD8_OFFSET 0x00026400
+#define AWIN__RSVD9_OFFSET 0x00026800
+#define AWIN__RSVD10_OFFSET 0x00026c00
+#define AWIN__RSVD11_OFFSET 0x00027000
+#define AWIN__RSVD12_OFFSET 0x00027400
+#define AWIN__RSVD13_OFFSET 0x00027800
+#define AWIN__RSVD14_OFFSET 0x00027c00
+#define AWIN_UART_FREQ (24*1000*1000) /* 24MHz */
+#define AWIN_UART_SIZE 0x00000100
+#define AWIN_UART0_OFFSET 0x00028000
+#define AWIN_UART1_OFFSET 0x00028400
+#define AWIN_UART2_OFFSET 0x00028800
+#define AWIN_UART3_OFFSET 0x00028c00
+#define AWIN_UART4_OFFSET 0x00029000
+#define AWIN_UART5_OFFSET 0x00029400
+#define AWIN_UART6_OFFSET 0x00029800
+#define AWIN_UART7_OFFSET 0x00029c00
+#define AWIN_PS20_OFFSET 0x0002a000
+#define AWIN_PS21_OFFSET 0x0002a400
+#define AWIN__RSVD15_OFFSET 0x0002a800
+#define AWIN_TWI0_OFFSET 0x0002ac00
+#define AWIN_TWI1_OFFSET 0x0002b000
+#define AWIN_TWI2_OFFSET 0x0002b400
+#define AWIN_TWI3_OFFSET 0x0002b800
+#define AWIN_CAN_OFFSET 0x0002bc00
+#define AWIN_TWI4_OFFSET 0x0002c000 /* A20 */
+#define AWIN_SCR_OFFSET 0x0002c400
+#define AWIN_GPS_OFFSET 0x00030000
+#define AWIN_MALI400_OFFSET 0x00040000
+#define AWIN_GMAC_OFFSET 0x00050000
+#define AWIN_HSTMR_OFFSET 0x00060000 /* A20 */
+#define AWIN_GIC_OFFSET 0x00080000 /* A20 */
+#define AWIN_HDMI1_OFFSET 0x000E0000 /* A20 */
+#define AWIN_SRAMC_OFFSET 0x00100000
+#define AWIN_DE_FE0_OFFSET 0x00200000
+#define AWIN_DE_FE1_OFFSET 0x00220000
+#define AWIN_DE_BE1_OFFSET 0x00240000
+#define AWIN_DE_BE0_OFFSET 0x00260000
+#define AWIN_MP_OFFSET 0x00280000
+#define AWIN_AVG_OFFSET 0x002A0000
+#define AWIN_SDRAM_PBASE 0x40000000
+
+/* A10/A20 DRAM Controller */
+#define AWIN_DRAM_CCR_REG 0x0000
+#define AWIN_DRAM_DCR_REG 0x0004
+#define AWIN_DRAM_IOCR_REG 0x0008
+#define AWIN_DRAM_CSR_REG 0x000c
+#define AWIN_DRAM_DRR_REG 0x0010
+#define AWIN_DRAM_TPR0_REG 0x0014
+#define AWIN_DRAM_TPR1_REG 0x0018
+#define AWIN_DRAM_TPR2_REG 0x001c
+#define AWIN_DRAM_GDLLCR_REG 0x0020
+#define AWIN_DRAM_RSLR0_REG 0x004c
+#define AWIN_DRAM_RSLR1_REG 0x0050
+#define AWIN_DRAM_RDGR0_REG 0x005c
+#define AWIN_DRAM_RDGR1_REG 0x0060
+#define AWIN_DRAM_ODTCR_REG 0x0098
+#define AWIN_DRAM_DTR0_REG 0x009c
+#define AWIN_DRAM_DTR1_REG 0x00a0
+#define AWIN_DRAM_DTAR_REG 0x00a4
+#define AWIN_DRAM_ZQCR0_REG 0x00a8
+#define AWIN_DRAM_ZQCR1_REG 0x00ac
+#define AWIN_DRAM_ZQSR_REG 0x00b0
+#define AWIN_DRAM_IDCR_REG 0x00b4
+#define AWIN_DRAM_MR_REG 0x01f0
+#define AWIN_DRAM_EMR1_REG 0x01f4
+#define AWIN_DRAM_EMR2_REG 0x01f8
+#define AWIN_DRAM_EMR3_REG 0x01fc
+#define AWIN_DRAM_DLLCTR_REG 0x0200
+#define AWIN_DRAM_DLLCR0_REG 0x0204
+#define AWIN_DRAM_DLLCR1_REG 0x0208
+#define AWIN_DRAM_DLLCR2_REG 0x020c
+#define AWIN_DRAM_DLLCR3_REG 0x0210
+#define AWIN_DRAM_DLLCR4_REG 0x0214
+#define AWIN_DRAM_DQTR0_REG 0x0218
+#define AWIN_DRAM_DQTR1_REG 0x021c
+#define AWIN_DRAM_DQTR2_REG 0x0220
+#define AWIN_DRAM_DQTR3_REG 0x0224
+#define AWIN_DRAM_DQSTR_REG 0x0228
+#define AWIN_DRAM_DQSBTR_REG 0x022c
+#define AWIN_DRAM_MCR_REG 0x0230
+#define AWIN_DRAM_PPWRSCTRL_REG 0x0240
+#define AWIN_DRAM_APR_REG 0x0244
+#define AWIN_DRAM_PLDTR_REG 0x023c
+#define AWIN_DRAM_HPCR0_REG 0x0240
+#define AWIN_DRAM_HPCRn_REG(n) (0x0240+4*(n))
+#define AWIN_DRAM_CSEL_REG 0x02e0
+
+#define AWIN_DRAM_DCR_IO_WIDTH __BITS(2,1)
+#define AWIN_DRAM_DCR_IO_WIDTH_16BIT 2
+#define AWIN_DRAM_DCR_IO_WIDTH_8BIT 1
+#define AWIN_DRAM_DCR_CHIP_DENSITY __BITS(5,3)
+#define AWIN_DRAM_DCR_CHIP_DENSITY_256M 0
+#define AWIN_DRAM_DCR_CHIP_DENSITY_512M 1
+#define AWIN_DRAM_DCR_CHIP_DENSITY_1G 2
+#define AWIN_DRAM_DCR_CHIP_DENSITY_2G 3
+#define AWIN_DRAM_DCR_CHIP_DENSITY_4G 4
+#define AWIN_DRAM_DCR_CHIP_DENSITY_8G 5
+#define AWIN_DRAM_DCR_BUS_WIDTH __BITS(8,6)
+#define AWIN_DRAM_DCR_BUS_WIDTH_32BIT 3
+#define AWIN_DRAM_DCR_BUS_WIDTH_16BIT 1
+#define AWIN_DRAM_DCR_BUS_WIDTH_8BIT 0
+#define AWIN_DRAM_DCR_RANK_SEL __BITS(11,10)
+
+#define AWIN_PLL1_CFG_REG 0x0000
+#define AWIN_PLL1_TUN_REG 0x0004
+#define AWIN_PLL2_CFG_REG 0x0008
+#define AWIN_PLL2_TUN_REG 0x000c
+#define AWIN_PLL3_CFG_REG 0x0010
+#define AWIN_PLL4_CFG_REG 0x0018
+#define AWIN_PLL5_CFG_REG 0x0020
+#define AWIN_PLL5_TUN_REG 0x0024
+#define AWIN_PLL6_CFG_REG 0x0028
+#define AWIN_PLL6_TUN_REG 0x002c
+#define AWIN_PLL7_CFG_REG 0x0030
+#define AWIN_PLL1_TUN2_REG 0x0038
+#define AWIN_PLL6_TUN2_REG 0x003c
+#define AWIN_PLL8_CFG_REG 0x0040
+#define AWIN_OSC24M_CFG_REG 0x0050
+#define AWIN_CPU_AHB_APB0_CFG_REG 0x0054
+#define AWIN_APB1_CLK_DIV_REG 0x0058
+
+#define AWIN_OSC24M_CFG_ENABLE __BIT(0)
+
+#define AWIN_PLL_CFG_ENABLE __BIT(31)
+#define AWIN_PLL_CFG_EXG_MODE __BIT(25)
+#define AWIN_PLL_CFG_OUT_EXP_DIVP __BITS(17,16)
+#define AWIN_PLL_CFG_FACTOR_N __BITS(12,8)
+#define AWIN_PLL_CFG_FACTOR_K __BITS(5,4)
+#define AWIN_PLL_CFG_FACTOR_M __BITS(1,0)
+
+#define AWIN_CPU_CLK_SRC_SEL __BITS(17,16)
+#define AWIN_CPU_CLK_SRC_SEL_LOSC 0
+#define AWIN_CPU_CLK_SRC_SEL_OSC24M 1
+#define AWIN_CPU_CLK_SRC_SEL_PLL1 2
+#define AWIN_CPU_CLK_SRC_SEL_200MHZ 3
+#define AWIN_APB0_CLK_RATIO __BITS(9,8)
+
+/* USB device offsets */
+#define AWIN_EHCI_OFFSET 0x0000
+#define AWIN_OHCI_OFFSET 0x0400
+
+/* A10 Interrupt Register Definitions */
+#define AWIN_INTC_VECTOR_REG 0x0000
+#define AWIN_INTC_BASE_ADDR_REG 0x0004
+#define AWIN_NMI_INT_CTRL_REG 0x000C
+#define AWIN_INTC_IRQ_PEND0_REG 0x0010
+#define AWIN_INTC_IRQ_PEND1_REG 0x0014
+#define AWIN_INTC_IRQ_PEND2_REG 0x0018
+#define AWIN_INTC_FIQ_PEND0_REG 0x0020
+#define AWIN_INTC_FIQ_PEND1_REG 0x0024
+#define AWIN_INTC_FIQ_PEND2_REG 0x0028
+#define AWIN_INTC_IRQ_TYPE_SEL0_REG 0x0030
+#define AWIN_INTC_IRQ_TYPE_SEL1_REG 0x0034
+#define AWIN_INTC_IRQ_TYPE_SEL2_REG 0x0038
+#define AWIN_INTC_EN0_REG 0x0040
+#define AWIN_INTC_EN1_REG 0x0044
+#define AWIN_INTC_EN2_REG 0x0048
+#define AWIN_INTC_MASK0_REG 0x0050
+#define AWIN_INTC_MASK1_REG 0x0054
+#define AWIN_INTC_MASK2_REG 0x0058
+#define AWIN_INTC_RESP0_REG 0x0060
+#define AWIN_INTC_RESP1_REG 0x0064
+#define AWIN_INTC_RESP2_REG 0x0068
+#define AWIN_INTC_FF0_REG 0x0070
+#define AWIN_INTC_FF1_REG 0x0074
+#define AWIN_INTC_FF2_REG 0x0078
+#define AWIN_INTC_PRIO0_REG 0x0080
+#define AWIN_INTC_PRIO1_REG 0x0084
+#define AWIN_INTC_PRIO2_REG 0x0088
+#define AWIN_INTC_PRIO3_REG 0x008C
+#define AWIN_INTC_PRIO4_REG 0x0090
+
+/* Standard Timer (A10) */
+#define AWIN_TMR_IRQ_EN_REG 0x0000
+#define AWIN_TMR_IRQ_STA_REG 0x0004
+#define AWIN_TMR0_CTRL_REG 0x0010
+#define AWIN_TMR0_INTV_VALUE_REG 0x0014
+#define AWIN_TMR0_CUR_VALUE_REG 0x0018
+#define AWIN_TMR1_CTRL_REG 0x0020
+#define AWIN_TMR1_INTV_VALUE_REG 0x0024
+#define AWIN_TMR1_CUR_VALUE_REG 0x0028
+#define AWIN_TMR2_CTRL_REG 0x0030
+#define AWIN_TMR2_INTV_VALUE_REG 0x0034
+#define AWIN_TMR2_CUR_VALUE_REG 0x0038
+#define AWIN_TMR3_CTRL_REG 0x0040
+#define AWIN_TMR3_INTV_VALUE_REG 0x0044
+#define AWIN_TMR4_CTRL_REG 0x0050
+#define AWIN_TMR4_INTV_VALUE_REG 0x0054
+#define AWIN_TMR4_CUR_VALUE_REG 0x0058
+#define AWIN_TMR5_CTRL_REG 0x0060
+#define AWIN_TMR5_INTV_VALUE_REG 0x0064
+#define AWIN_TMR5_CUR_VALUE_REG 0x0068
+#define AWIN_AVS_CNT_CTL_REG 0x0080
+#define AWIN_AVS_CNT0_REG 0x0084
+#define AWIN_AVS_CNT1_REG 0x0088
+#define AWIN_AVS_CNT_DIV_REG 0x008C
+#define AWIN_WDOG_CTRL_REG 0x0090
+#define AWIN_WDOG_MODE_REG 0x0094
+#define AWIN_CNT64_CTRL_REG 0x00A0 /* A10 */
+#define AWIN_CNT64_LO_REG 0x00A4 /* A10 */
+#define AWIN_CNT64_HI_REG 0x00A8 /* A10 */
+#define AWIN_LOSC_CTRL_REG 0x0100
+#define AWIN_RTC_YY_MM_DD_REG 0x0104
+#define AWIN_RTC_HH_MM_SS_REG 0x0108
+#define AWIN_DD_HH_MM_SS_REG 0x010C
+#define AWIN_ALARM_WK_HH_MM_SS_REG 0x0110
+#define AWIN_ALARM_EN_REG 0x0114
+#define AWIN_ALARM_IRQ_EN_REG 0x0118
+#define AWIN_ALARM_IRQ_STA_REG 0x011C
+#define AWIN_TMR_GP_DATA0_REG 0x0120
+#define AWIN_TMR_GP_DATA1_REG 0x0124
+#define AWIN_TMR_GP_DATA2_REG 0x0128
+#define AWIN_TMR_GP_DATA3_REG 0x012C
+#define AWIN_CPU_CFG_REG 0x0140
+
+#define AWIN_TWI_ADDR_REG 0x0000
+#define AWIN_TWI_XADDR_REG 0x0004
+#define AWIN_TWI_DATA_REG 0x0008
+#define AWIN_TWI_CNTR_REG 0x000C
+#define AWIN_TWI_STAT_REG 0x0010
+#define AWIN_TWI_CCR_REG 0x0014
+#define AWIN_TWI_SRST_REG 0x0018
+#define AWIN_TWI_EFR_REG 0x001C
+#define AWIN_TWI_LCR_REG 0x0020
+
+#define AWIN_SPI_RXDATA_REG 0x0000
+#define AWIN_SPI_TXDATA_REG 0x0004
+#define AWIN_SPI_CTL_REG 0x0008
+#define AWIN_SPI_INTCTL_REG 0x000C
+#define AWIN_SPI_ST_REG 0x0010
+#define AWIN_SPI_DMACTL_REG 0x0014
+#define AWIN_SPI_WAIT_REG 0x0018
+#define AWIN_SPI_CCTL_REG 0x001C
+#define AWIN_SPI_BC_REG 0x0020
+#define AWIN_SPI_TC_REG 0x0024
+#define AWIN_SPI_FIFO_STA_REG 0x0028
+
+/* A20 CPU Configuration definitions */
+#define AWIN_CPU0_RST_CTRL_REG 0x0040
+#define AWIN_CPU0_CTRL_REG 0x0044
+#define AWIN_CPU0_STATUS_REG 0x0048
+#define AWIN_CPU1_RST_CTRL_REG 0x0080
+#define AWIN_CPU1_CTRL_REG 0x0084
+#define AWIN_CPU1_STATUS_REG 0x0088
+#define AWIN_GENER_CTRL_REG 0x0184
+#define AWIN_EVENT_IN_REG 0x0190
+#define AWIN_PRIVATE_REG 0x01a4
+#define AWIN_IDLE_CNT0_LOW_REG 0x0200
+#define AWIN_IDLE_CNT0_HIGH_REG 0x0204
+#define AWIN_IDLE_CNT0_CTRL_REG 0x0208
+#define AWIN_IDLE_CNT1_LOW_REG 0x0210
+#define AWIN_IDLE_CNT1_HIGH_REG 0x0214
+#define AWIN_IDLE_CNT1_CTRL_REG 0x0218
+#define AWIN_OSC24M_CNT64_CTRL_REG 0x0280
+#define AWIN_OSC24M_CNT64_LOW_REG 0x0284
+#define AWIN_OSC24M_CNT64_HIGH_REG 0x0288
+#define AWIN_LOSC_CNT64_CTRL_REG 0x0290
+#define AWIN_LOSC_CNT64_LOW_REG 0x0294
+#define AWIN_LOSC_CNT64_HIGH_REG 0x0298
+
+#define AWIN_CPU_CORE_RESET __BIT(1)
+#define AWIN_CPU_RESET __BIT(0)
+
+/* High Speed Timer (A20) */
+#define AWIN_HSTMR_IRQ_EN_REG 0x0000
+#define AWIN_HSTMR_IRQ_STAT_REG 0x0004
+#define AWIN_HSTMR_TMR0_CTRL_REG 0x0010
+#define AWIN_HSTMR_TMR0_INTV_LO_REG 0x0014
+#define AWIN_HSTMR_TMR0_INTV_HI_REG 0x0018
+#define AWIN_HSTMR_TMR0_CURNT_LO_REG 0x001c
+#define AWIN_HSTMR_TMR0_CURNT_HI_REG 0x0020
+#define AWIN_HSTMR_TMR1_CTRL_REG 0x0030
+#define AWIN_HSTMR_TMR1_INTV_LO_REG 0x0034
+#define AWIN_HSTMR_TMR1_INTV_HI_REG 0x0038
+#define AWIN_HSTMR_TMR1_CURNT_LO_REG 0x003c
+#define AWIN_HSTMR_TMR1_CURNT_HI_REG 0x0040
+#define AWIN_HSTMR_TMR2_CTRL_REG 0x0050
+#define AWIN_HSTMR_TMR2_INTV_LO_REG 0x0054
+#define AWIN_HSTMR_TMR2_INTV_HI_REG 0x0058
+#define AWIN_HSTMR_TMR2_CURNT_LO_REG 0x005c
+#define AWIN_HSTMR_TMR2_CURNT_HI_REG 0x0060
+#define AWIN_HSTMR_TMR3_CTRL_REG 0x0070
+#define AWIN_HSTMR_TMR3_INTV_LO_REG 0x0074
+#define AWIN_HSTMR_TMR3_INTV_HI_REG 0x0078
+#define AWIN_HSTMR_TMR3_CURNT_LO_REG 0x007c
+#define AWIN_HSTMR_TMR3_CURNT_HI_REG 0x0080
+
+#endif /* _ARM_ALLWINNER_AWIN_REG_H_ */
Index: src/sys/arch/arm/allwinner/awin_var.h
diff -u /dev/null src/sys/arch/arm/allwinner/awin_var.h:1.1
--- /dev/null Tue Sep 3 18:02:26 2013
+++ src/sys/arch/arm/allwinner/awin_var.h Tue Sep 3 18:02:26 2013
@@ -0,0 +1,42 @@
+/* $NetBSD: awin_var.h,v 1.1 2013/09/03 18:02:26 matt Exp $ */
+/*-
+ * Copyright (c) 2013 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ALLWINNER_AWIN_VAR_H_
+#define _ARM_ALLWINNER_AWIN_VAR_H_
+
+#include <sys/types.h>
+#include <sys/bus.h>
+
+extern struct bus_space awin_bs_tag;
+extern struct bus_space awin_a4x_bs_tag;
+
+bool awinwdt_enable(bool);
+
+#endif /* _ARM_ALLWINNER_AWIN_VAR_H_ */
Index: src/sys/arch/arm/allwinner/files.awin
diff -u /dev/null src/sys/arch/arm/allwinner/files.awin:1.1
--- /dev/null Tue Sep 3 18:02:26 2013
+++ src/sys/arch/arm/allwinner/files.awin Tue Sep 3 18:02:26 2013
@@ -0,0 +1,101 @@
+# $NetBSD: files.awin,v 1.1 2013/09/03 18:02:26 matt Exp $
+#
+# Configuration info for Allwinner ARM Peripherals
+#
+
+include "arch/arm/pic/files.pic"
+include "arch/arm/cortex/files.cortex"
+
+file arch/arm/arm32/arm32_boot.c
+file arch/arm/arm32/arm32_kvminit.c
+file arch/arm/arm32/arm32_reboot.c
+file arch/arm/arm32/irq_dispatch.S
+
+file arch/arm/allwinner/awin_board.c
+file arch/arm/allwinner/awingen_space.c
+file arch/arm/allwinner/awin_a4x_space.c
+file arch/arm/arm/bus_space_a4x.S
+
+# Console parameters
+defparam opt_allwinner.h CONADDR
+defparam opt_allwinner.h CONSPEED
+defparam opt_allwinner.h CONMODE
+defparam opt_allwinner.h MEMSIZE
+defflag opt_allwinner.h AWIN_CONSOLE_EARLY
+defflag opt_allwinner.h AWINETH_COUNTERS
+defflag opt_allwinner.h ALLWINNER_A10
+defflag opt_allwinner.h ALLWINNER_A20
+defflag opt_allwinner.h ALLWINNER_A31
+
+# SoC I/O attach point
+device awinio { [port=-1] } : bus_space_generic
+attach awinio at mainbus
+file arch/arm/allwinner/awinio.c awinio
+
+# A10 Interrupt Controller
+device awinicu
+attach awinicu at awinio
+file arch/arm/allwinner/awinicu.c awinicu
+
+# A10/A20 Watchdog
+device awinwdt
+attach awinwdt at awinio
+file arch/arm/allwinner/awinwdt.c awinwdt
+
+# A10 Timers
+device awintmr
+attach awintmr at awinio
+file arch/arm/allwinner/awintmr.c awintmr
+
+# A10/A20 UART
+attach com at awinio with com_awinio
+file arch/arm/allwinner/awin_com.c com_awinio
+
+# A10/A20 GPIO
+device awingpio : gpiobus
+attach awingpio at awinio
+file arch/arm/allwinner/awin_gpio.c awingpio
+
+# A10/A20 TWI (IIC)
+device awiniic : i2cbus, i2cexec
+attach awiniic at awinio
+file arch/arm/allwinner/awin_twi.c awiniic
+
+# A10/A20 NAND controller
+device awinnand : nandbus
+attach awinnand at awinio
+file arch/arm/allwinner/awin_nand.c awinnand
+
+# A10/A20 Security System
+device awincrypto : opencrypto
+attach awincrypto at awinio
+file arch/arm/allwinner/awin_rng.c awinrng needs-flag
+
+# A10/A20 EMAC
+device awinfe { } : ether, ifnet, arp
+attach awinfe at awinio
+file arch/arm/allwinner/awin_eth.c awinfe
+
+# A20 GMAC
+device awinge { } : ether, ifnet, arp
+attach awinge at awinio
+file arch/arm/allwinner/awin_gige.c awinge
+
+# USB2 Host Controller (EHCI/OHCI)
+device awinusb { }
+attach awinusb at awinio
+attach ohci at awinusb with ohci_awinusb
+attach ehci at awinusb with ehci_awinusb
+file arch/arm/allwinner/awin_usb.c awinusb
+
+# A10/A20 SD/MMC Controller (SDHC)
+attach sdhc at awinio with sdhc_awin
+file arch/arm/allwinner/awin_sdhc.c sdhc_awin
+
+# A10 WDC Controller (PATA)
+attach wdc at awinio with wdc_awin
+file arch/arm/allwinner/awin_wdc.c wdc_awin
+
+# A20 AHCI Controller (SATA)
+attach ahcisata at awinio with ahcisata_awin
+file arch/arm/allwinner/awin_ahcisata.c ahcisata_awin
