Module Name: src
Committed By: matt
Date: Mon Oct 28 22:51:16 UTC 2013
Modified Files:
src/sys/arch/arm/broadcom: bcm53xx_board.c bcm53xx_ccb.c bcm53xx_eth.c
bcm53xx_intr.h bcm53xx_reg.h bcm53xx_usb.c bcm53xx_var.h
bcmgen_space.c files.bcm53xx
Added Files:
src/sys/arch/arm/broadcom: bcm53xx_nand.c
Log Message:
Add support for the BCM56340 iProc based switch
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/broadcom/bcm53xx_board.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/broadcom/bcm53xx_ccb.c \
src/sys/arch/arm/broadcom/bcm53xx_usb.c \
src/sys/arch/arm/broadcom/bcmgen_space.c \
src/sys/arch/arm/broadcom/files.bcm53xx
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/broadcom/bcm53xx_eth.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/broadcom/bcm53xx_intr.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/broadcom/bcm53xx_nand.c
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/broadcom/bcm53xx_reg.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/broadcom/bcm53xx_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/broadcom/bcm53xx_board.c
diff -u src/sys/arch/arm/broadcom/bcm53xx_board.c:1.16 src/sys/arch/arm/broadcom/bcm53xx_board.c:1.17
--- src/sys/arch/arm/broadcom/bcm53xx_board.c:1.16 Thu Aug 29 15:46:17 2013
+++ src/sys/arch/arm/broadcom/bcm53xx_board.c Mon Oct 28 22:51:16 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm53xx_board.c,v 1.16 2013/08/29 15:46:17 riz Exp $ */
+/* $NetBSD: bcm53xx_board.c,v 1.17 2013/10/28 22:51:16 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.16 2013/08/29 15:46:17 riz Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.17 2013/10/28 22:51:16 matt Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -46,6 +46,7 @@ __KERNEL_RCSID(1, "$NetBSD: bcm53xx_boar
#include <net/if.h>
#include <net/if_ether.h>
+#define CCA_PRIVATE
#define CRU_PRIVATE
#define DDR_PRIVATE
#define DMU_PRIVATE
@@ -67,6 +68,7 @@ bus_space_handle_t bcm53xx_armcore_bsh;
static struct cpu_softc cpu_softc;
struct arm32_dma_range bcm53xx_dma_ranges[] = {
+#ifdef BCM5301X
[0] = {
.dr_sysbase = 0x80000000,
.dr_busbase = 0x80000000,
@@ -75,6 +77,16 @@ struct arm32_dma_range bcm53xx_dma_range
.dr_sysbase = 0x90000000,
.dr_busbase = 0x90000000,
},
+#elif defined(BCM56340)
+ [0] = {
+ .dr_sysbase = 0x60000000,
+ .dr_busbase = 0x60000000,
+ .dr_len = 0x20000000,
+ }, [1] = {
+ .dr_sysbase = 0xa0000000,
+ .dr_busbase = 0xa0000000,
+ }.
+#endif
};
struct arm32_bus_dma_tag bcm53xx_dma_tag = {
@@ -86,6 +98,7 @@ struct arm32_bus_dma_tag bcm53xx_dma_tag
};
struct arm32_dma_range bcm53xx_coherent_dma_ranges[] = {
+#ifdef BCM5301X
[0] = {
.dr_sysbase = 0x80000000,
.dr_busbase = 0x80000000,
@@ -95,6 +108,17 @@ struct arm32_dma_range bcm53xx_coherent_
.dr_sysbase = 0x90000000,
.dr_busbase = 0x90000000,
},
+#elif defined(BCM563XX)
+ [0] = {
+ .dr_sysbase = 0x60000000,
+ .dr_busbase = 0x60000000,
+ .dr_len = 0x20000000,
+ .dr_flags = _BUS_DMAMAP_COHERENT,
+ }, [1] = {
+ .dr_sysbase = 0xa0000000,
+ .dr_busbase = 0xa0000000,
+ },
+#endif
};
struct arm32_bus_dma_tag bcm53xx_coherent_dma_tag = {
@@ -453,6 +477,11 @@ bcm53xx_cpu_softc_init(struct cpu_info *
cpu->cpu_armcore_bst = bcm53xx_armcore_bst;
cpu->cpu_armcore_bsh = bcm53xx_armcore_bsh;
+
+ const uint32_t chipid = bus_space_read_4(cpu->cpu_ioreg_bst,
+ cpu->cpu_ioreg_bsh, CCA_MISC_BASE + MISC_CHIPID);
+
+ cpu->cpu_chipid = __SHIFTOUT(chipid, CHIPID_ID);
}
void
@@ -525,7 +554,8 @@ bcm53xx_bootstrap(vaddr_t iobase)
curcpu()->ci_data.cpu_cc_freq = clk->clk_cpu;
- arml2cc_init(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, ARMCORE_L2C_BASE);
+ arml2cc_init(bcm53xx_armcore_bst, bcm53xx_armcore_bsh,
+ ARMCORE_L2C_BASE);
}
void
Index: src/sys/arch/arm/broadcom/bcm53xx_ccb.c
diff -u src/sys/arch/arm/broadcom/bcm53xx_ccb.c:1.3 src/sys/arch/arm/broadcom/bcm53xx_ccb.c:1.4
--- src/sys/arch/arm/broadcom/bcm53xx_ccb.c:1.3 Wed Oct 3 19:18:41 2012
+++ src/sys/arch/arm/broadcom/bcm53xx_ccb.c Mon Oct 28 22:51:16 2013
@@ -34,7 +34,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_ccb.c,v 1.3 2012/10/03 19:18:41 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_ccb.c,v 1.4 2013/10/28 22:51:16 matt Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -101,18 +101,35 @@ static const struct bcm_locators bcmccb_
{ "bcmtmr", TIMER1_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT, 2, { IRQ_TIMER1_1, IRQ_TIMER1_2 } },
{ "bcmsw", SRAB_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT, },
{ "bcmcom", UART2_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT, 1, { IRQ_UART2 } },
- { "bcmi2c", SMBUS_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT, 1, { IRQ_SMBUS } },
+#ifdef BCM5301X
+ { "bcmi2c", SMBUS1_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT, 1, { IRQ_SMBUS1 } },
+#endif
+#ifdef BCM536XX
+ { "bcmi2c", SMBUS1_BASE, 0x1000, 1, 1, { IRQ_SMBUS1 } },
+ { "bcmi2c", SMBUS2_BASE, 0x1000, 2, 1, { IRQ_SMBUS2 } },
+#endif
{ "bcmcru", CRU_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT },
{ "bcmdmu", DMU_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT },
{ "bcmddr", DDR_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT, 1, { IRQ_DDR_CONTROLLER } },
{ "bcmeth", GMAC0_BASE, 0x1000, 0, 1, { IRQ_GMAC0 }, },
{ "bcmeth", GMAC1_BASE, 0x1000, 1, 1, { IRQ_GMAC1 }, },
+#ifdef GMAC2_BASE
{ "bcmeth", GMAC2_BASE, 0x1000, 2, 1, { IRQ_GMAC2 }, },
+#endif
// { "bcmeth", GMAC3_BASE, 0x1000, 3, 1, { IRQ_GMAC3 }, },
{ "bcmpax", PCIE0_BASE, 0x1000, 0, 6, { IRQ_PCIE_INT0 }, },
{ "bcmpax", PCIE1_BASE, 0x1000, 1, 6, { IRQ_PCIE_INT1 }, },
+#ifdef PCIE2_BASE
{ "bcmpax", PCIE2_BASE, 0x1000, 2, 6, { IRQ_PCIE_INT2 }, },
+#endif
+#ifdef SDIO_BASE
{ "sdhc", SDIO_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT, 1, { IRQ_SDIO } },
+#endif
+ { "bcmnand", NAND_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT, 8,
+ { IRQ_NAND_RD_MISS, IRQ_NAND_BLK_ERASE_COMP,
+ IRQ_NAND_COPY_BACK_COMP, IRQ_NAND_PGM_PAGE_COMP,
+ IRQ_NAND_RO_CTLR_READY, IRQ_NAND_RB_B,
+ IRQ_NAND_ECC_MIPS_UNCORR, IRQ_NAND_ECC_MIPS_CORR } },
{ "bcmusb", EHCI_BASE, 0x2000, BCMCCBCF_PORT_DEFAULT, 1, { IRQ_USB2 } },
};
@@ -159,22 +176,27 @@ bcmccb_mainbus_attach(device_t parent, d
aprint_naive("\n");
aprint_normal("\n");
- bcm53xx_srab_init(); // need this for ethernet.
-
for (size_t i = 0; i < __arraycount(bcmccb_locators); i++) {
+ const struct bcm_locators *loc = &bcmccb_locators[i];
+
+#ifdef BCM5301X
+ if (strcmp(loc->loc_name, "bcmsw") == 0) {
+ bcm53xx_srab_init(); // need this for ethernet.
+ }
+#endif
+
struct bcmccb_attach_args ccbaa = {
.ccbaa_ccb_bst = sc->sc_bst,
.ccbaa_ccb_bsh = sc->sc_bsh,
.ccbaa_dmat = &bcm53xx_dma_tag,
- .ccbaa_loc = bcmccb_locators[i],
+ .ccbaa_loc = *loc,
};
/*
* If the device might be in reset, let's try to take it
* out of it. If it fails or is unavailable, skip it.
*/
- if (!bcm53xx_idm_device_init(&bcmccb_locators[i],
- sc->sc_bst, sc->sc_bsh))
+ if (!bcm53xx_idm_device_init(loc, sc->sc_bst, sc->sc_bsh))
continue;
cfdata_t cf = config_search_ia(bcmccb_find, self, "bcmccb",
Index: src/sys/arch/arm/broadcom/bcm53xx_usb.c
diff -u src/sys/arch/arm/broadcom/bcm53xx_usb.c:1.3 src/sys/arch/arm/broadcom/bcm53xx_usb.c:1.4
--- src/sys/arch/arm/broadcom/bcm53xx_usb.c:1.3 Thu Nov 29 17:38:26 2012
+++ src/sys/arch/arm/broadcom/bcm53xx_usb.c Mon Oct 28 22:51:16 2013
@@ -32,7 +32,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_usb.c,v 1.3 2012/11/29 17:38:26 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_usb.c,v 1.4 2013/10/28 22:51:16 matt Exp $");
#include <sys/bus.h>
#include <sys/device.h>
@@ -227,6 +227,8 @@ bcmusb_ccb_match(device_t parent, cfdata
return 1;
}
+#define OHCI_OFFSET (OHCI_BASE - EHCI_BASE)
+
void
bcmusb_ccb_attach(device_t parent, device_t self, void *aux)
{
@@ -237,10 +239,10 @@ bcmusb_ccb_attach(device_t parent, devic
usbsc->usbsc_bst = ccbaa->ccbaa_ccb_bst;
usbsc->usbsc_dmat = ccbaa->ccbaa_dmat;
- bus_space_subregion(usbsc->usbsc_bst, ccbaa->ccbaa_ccb_bsh, EHCI_BASE,
- 0x1000, &usbsc->usbsc_ehci_bsh);
- bus_space_subregion(usbsc->usbsc_bst, ccbaa->ccbaa_ccb_bsh, OHCI_BASE,
- 0x1000, &usbsc->usbsc_ohci_bsh);
+ bus_space_subregion(usbsc->usbsc_bst, ccbaa->ccbaa_ccb_bsh,
+ loc->loc_offset, 0x1000, &usbsc->usbsc_ehci_bsh);
+ bus_space_subregion(usbsc->usbsc_bst, ccbaa->ccbaa_ccb_bsh,
+ loc->loc_offset + OHCI_OFFSET, 0x1000, &usbsc->usbsc_ohci_bsh);
/*
* Bring the PHYs out of reset.
Index: src/sys/arch/arm/broadcom/bcmgen_space.c
diff -u src/sys/arch/arm/broadcom/bcmgen_space.c:1.3 src/sys/arch/arm/broadcom/bcmgen_space.c:1.4
--- src/sys/arch/arm/broadcom/bcmgen_space.c:1.3 Mon Aug 12 21:20:02 2013
+++ src/sys/arch/arm/broadcom/bcmgen_space.c Mon Oct 28 22:51:16 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: bcmgen_space.c,v 1.3 2013/08/12 21:20:02 matt Exp $ */
+/* $NetBSD: bcmgen_space.c,v 1.4 2013/10/28 22:51:16 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bcmgen_space.c,v 1.3 2013/08/12 21:20:02 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bcmgen_space.c,v 1.4 2013/10/28 22:51:16 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -39,6 +39,7 @@ __KERNEL_RCSID(0, "$NetBSD: bcmgen_space
#include <uvm/uvm_extern.h>
#include <sys/bus.h>
+#include <sys/endian.h>
/* Prototypes for all the bus_space structure functions */
bs_protos(bcmgen);
@@ -46,6 +47,12 @@ bs_protos(generic);
bs_protos(generic_armv4);
bs_protos(bs_notimpl);
+#if BYTE_ORDER == BIG_ENDIAN
+#define NSWAP(n) n ## _swap
+#else
+#define NSWAP(n) n
+#endif
+
struct bus_space bcmgen_bs_tag = {
/* cookie */
(void *) 0,
@@ -70,38 +77,38 @@ struct bus_space bcmgen_bs_tag = {
/* read (single) */
generic_bs_r_1,
- generic_armv4_bs_r_2,
- generic_bs_r_4,
+ NSWAP(generic_armv4_bs_r_2),
+ NSWAP(generic_bs_r_4),
bs_notimpl_bs_r_8,
/* read multiple */
generic_bs_rm_1,
- generic_armv4_bs_rm_2,
- generic_bs_rm_4,
+ NSWAP(generic_armv4_bs_rm_2),
+ NSWAP(generic_bs_rm_4),
bs_notimpl_bs_rm_8,
/* read region */
generic_bs_rr_1,
- generic_armv4_bs_rr_2,
- generic_bs_rr_4,
+ NSWAP(generic_armv4_bs_rr_2),
+ NSWAP(generic_bs_rr_4),
bs_notimpl_bs_rr_8,
/* write (single) */
generic_bs_w_1,
- generic_armv4_bs_w_2,
- generic_bs_w_4,
+ NSWAP(generic_armv4_bs_w_2),
+ NSWAP(generic_bs_w_4),
bs_notimpl_bs_w_8,
/* write multiple */
generic_bs_wm_1,
- generic_armv4_bs_wm_2,
- generic_bs_wm_4,
+ NSWAP(generic_armv4_bs_wm_2),
+ NSWAP(generic_bs_wm_4),
bs_notimpl_bs_wm_8,
/* write region */
generic_bs_wr_1,
- generic_armv4_bs_wr_2,
- generic_bs_wr_4,
+ NSWAP(generic_armv4_bs_wr_2),
+ NSWAP(generic_bs_wr_4),
bs_notimpl_bs_wr_8,
/* set multiple */
@@ -112,7 +119,7 @@ struct bus_space bcmgen_bs_tag = {
/* set region */
generic_bs_sr_1,
- generic_armv4_bs_sr_2,
+ NSWAP(generic_armv4_bs_sr_2),
bs_notimpl_bs_sr_4,
bs_notimpl_bs_sr_8,
@@ -125,38 +132,38 @@ struct bus_space bcmgen_bs_tag = {
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
/* read (single) */
generic_bs_r_1,
- generic_armv4_bs_r_2,
- generic_bs_r_4,
+ NSWAP(generic_armv4_bs_r_2),
+ NSWAP(generic_bs_r_4),
bs_notimpl_bs_r_8,
/* read multiple */
generic_bs_rm_1,
- generic_armv4_bs_rm_2,
- generic_bs_rm_4,
+ NSWAP(generic_armv4_bs_rm_2),
+ NSWAP(generic_bs_rm_4),
bs_notimpl_bs_rm_8,
/* read region */
generic_bs_rr_1,
- generic_armv4_bs_rr_2,
- generic_bs_rr_4,
+ NSWAP(generic_armv4_bs_rr_2),
+ NSWAP(generic_bs_rr_4),
bs_notimpl_bs_rr_8,
/* write (single) */
generic_bs_w_1,
- generic_armv4_bs_w_2,
- generic_bs_w_4,
+ NSWAP(generic_armv4_bs_w_2),
+ NSWAP(generic_bs_w_4),
bs_notimpl_bs_w_8,
/* write multiple */
generic_bs_wm_1,
- generic_armv4_bs_wm_2,
- generic_bs_wm_4,
+ NSWAP(generic_armv4_bs_wm_2),
+ NSWAP(generic_bs_wm_4),
bs_notimpl_bs_wm_8,
/* write region */
generic_bs_wr_1,
- generic_armv4_bs_wr_2,
- generic_bs_wr_4,
+ NSWAP(generic_armv4_bs_wr_2),
+ NSWAP(generic_bs_wr_4),
bs_notimpl_bs_wr_8,
#endif
};
Index: src/sys/arch/arm/broadcom/files.bcm53xx
diff -u src/sys/arch/arm/broadcom/files.bcm53xx:1.3 src/sys/arch/arm/broadcom/files.bcm53xx:1.4
--- src/sys/arch/arm/broadcom/files.bcm53xx:1.3 Fri Dec 7 22:18:45 2012
+++ src/sys/arch/arm/broadcom/files.bcm53xx Mon Oct 28 22:51:16 2013
@@ -1,4 +1,4 @@
-# $NetBSD: files.bcm53xx,v 1.3 2012/12/07 22:18:45 matt Exp $
+# $NetBSD: files.bcm53xx,v 1.4 2013/10/28 22:51:16 matt Exp $
#
# Configuration info for Broadcom BCM5301X ARM Peripherals
#
@@ -21,6 +21,8 @@ defparam opt_broadcom.h CONMODE
defparam opt_broadcom.h MEMSIZE
defflag opt_broadcom.h BCM53XX_CONSOLE_EARLY
defflag opt_broadcom.h BCMETH_COUNTERS
+defflag opt_broadcom.h BCM563XX
+defflag opt_broadcom.h BCM5301X
# ChipCommonA attach point
device bcmcca { [channel=-1] } : bus_space_generic, gpiobus, sysmon_wdog
@@ -42,6 +44,10 @@ device bcmi2c : i2cbus, i2cexec
attach bcmi2c at bcmccb with bcmi2c_ccb
file arch/arm/broadcom/bcm53xx_i2c.c bcmi2c_ccb
+device bcmnand : nandbus
+attach bcmnand at bcmccb with bcmnand_ccb
+file arch/arm/broadcom/bcm53xx_nand.c bcmnand_ccb
+
device bcmrng
attach bcmrng at bcmccb with bcmrng_ccb
file arch/arm/broadcom/bcm53xx_rng.c bcmrng_ccb needs-flag
Index: src/sys/arch/arm/broadcom/bcm53xx_eth.c
diff -u src/sys/arch/arm/broadcom/bcm53xx_eth.c:1.24 src/sys/arch/arm/broadcom/bcm53xx_eth.c:1.25
--- src/sys/arch/arm/broadcom/bcm53xx_eth.c:1.24 Tue Feb 19 02:18:29 2013
+++ src/sys/arch/arm/broadcom/bcm53xx_eth.c Mon Oct 28 22:51:16 2013
@@ -35,7 +35,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_eth.c,v 1.24 2013/02/19 02:18:29 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_eth.c,v 1.25 2013/10/28 22:51:16 matt Exp $");
#include <sys/param.h>
#include <sys/atomic.h>
@@ -903,7 +903,7 @@ bcmeth_rx_buf_alloc(
}
KASSERT(map->dm_mapsize == MCLBYTES);
#ifdef BCMETH_RCVMAGIC
- *mtod(m, uint32_t *) = BCMETH_RCVMAGIC;
+ *mtod(m, uint32_t *) = htole32(BCMETH_RCVMAGIC);
bus_dmamap_sync(sc->sc_dmat, map, 0, sizeof(uint32_t),
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
bus_dmamap_sync(sc->sc_dmat, map, sizeof(uint32_t),
@@ -955,9 +955,9 @@ bcmeth_rxq_produce(
bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t);
KASSERT(map);
- producer->rxdb_buflen = MCLBYTES;
- producer->rxdb_addrlo = map->dm_segs[0].ds_addr;
- producer->rxdb_flags &= RXDB_FLAG_ET;
+ producer->rxdb_buflen = htole32(MCLBYTES);
+ producer->rxdb_addrlo = htole32(map->dm_segs[0].ds_addr);
+ producer->rxdb_flags &= htole32(RXDB_FLAG_ET);
*rxq->rxq_mtail = m;
rxq->rxq_mtail = &m->m_next;
m->m_len = MCLBYTES;
@@ -1063,6 +1063,7 @@ bcmeth_rxq_consume(
bus_dmamap_sync(sc->sc_dmat, map, 0, arm_dcache_align,
BUS_DMASYNC_POSTREAD);
memcpy(&rxsts, rxq->rxq_mhead->m_data, 4);
+ rxsts = le32toh(rxsts);
#if 0
KASSERTMSG(rxsts != BCMETH_RCVMAGIC, "currdscr=%u consumer=%zd",
currdscr, consumer - rxq->rxq_first);
@@ -1138,7 +1139,7 @@ bcmeth_rxq_consume(
* Wrap at the last entry!
*/
if (++consumer == rxq->rxq_last) {
- KASSERT(consumer[-1].rxdb_flags & RXDB_FLAG_ET);
+ KASSERT(consumer[-1].rxdb_flags & htole32(RXDB_FLAG_ET));
rxq->rxq_consumer = rxq->rxq_first;
} else {
rxq->rxq_consumer = consumer;
@@ -1166,7 +1167,7 @@ bcmeth_rxq_consume(
* Wrap at the last entry!
*/
if (++consumer == rxq->rxq_last) {
- KASSERT(consumer[-1].rxdb_flags & RXDB_FLAG_ET);
+ KASSERT(consumer[-1].rxdb_flags & htole32(RXDB_FLAG_ET));
consumer = rxq->rxq_first;
}
}
@@ -1227,13 +1228,13 @@ bcmeth_rxq_reset(
*/
struct gmac_rxdb *rxdb;
for (rxdb = rxq->rxq_first; rxdb < rxq->rxq_last - 1; rxdb++) {
- rxdb->rxdb_flags = RXDB_FLAG_IC;
+ rxdb->rxdb_flags = htole32(RXDB_FLAG_IC);
}
/*
* Last descriptor has the wrap flag.
*/
- rxdb->rxdb_flags = RXDB_FLAG_ET|RXDB_FLAG_IC;
+ rxdb->rxdb_flags = htole32(RXDB_FLAG_ET|RXDB_FLAG_IC);
/*
* Reset the producer consumer indexes.
@@ -1415,14 +1416,16 @@ bcmeth_txq_produce(
struct gmac_txdb *start = producer;
size_t count = map->dm_nsegs;
- producer->txdb_flags |= first_flags;
- producer->txdb_addrlo = map->dm_segs[0].ds_addr;
- producer->txdb_buflen = map->dm_segs[0].ds_len;
+ producer->txdb_flags |= htole32(first_flags);
+ producer->txdb_addrlo = htole32(map->dm_segs[0].ds_addr);
+ producer->txdb_buflen = htole32(map->dm_segs[0].ds_len);
for (u_int i = 1; i < map->dm_nsegs; i++) {
#if 0
printf("[%zu]: %#x/%#x/%#x/%#x\n", producer - txq->txq_first,
- producer->txdb_flags, producer->txdb_buflen,
- producer->txdb_addrlo, producer->txdb_addrhi);
+ le32toh(producer->txdb_flags),
+ le32toh(producer->txdb_buflen),
+ le32toh(producer->txdb_addrlo),
+ le32toh(producer->txdb_addrhi));
#endif
if (__predict_false(++producer == txq->txq_last)) {
bcmeth_txq_desc_presync(sc, txq, start,
@@ -1431,14 +1434,14 @@ bcmeth_txq_produce(
producer = txq->txq_first;
start = txq->txq_first;
}
- producer->txdb_addrlo = map->dm_segs[i].ds_addr;
- producer->txdb_buflen = map->dm_segs[i].ds_len;
+ producer->txdb_addrlo = htole32(map->dm_segs[i].ds_addr);
+ producer->txdb_buflen = htole32(map->dm_segs[i].ds_len);
}
- producer->txdb_flags |= last_flags;
+ producer->txdb_flags |= htole32(last_flags);
#if 0
printf("[%zu]: %#x/%#x/%#x/%#x\n", producer - txq->txq_first,
- producer->txdb_flags, producer->txdb_buflen,
- producer->txdb_addrlo, producer->txdb_addrhi);
+ le32toh(producer->txdb_flags), le32toh(producer->txdb_buflen),
+ le32toh(producer->txdb_addrlo), le32toh(producer->txdb_addrhi));
#endif
if (count)
bcmeth_txq_desc_presync(sc, txq, start, count);
@@ -1448,8 +1451,8 @@ bcmeth_txq_produce(
*/
txq->txq_free -= map->dm_nsegs;
KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer);
- KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txdb_flags & TXDB_FLAG_EF) == 0);
- KASSERT(producer->txdb_flags & TXDB_FLAG_EF);
+ KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txdb_flags & htole32(TXDB_FLAG_EF)) == 0);
+ KASSERT(producer->txdb_flags & htole32(TXDB_FLAG_EF));
#if 0
printf("%s: mbuf %p: produced a %u byte packet in %u segments (%zd..%zd)\n",
@@ -1622,7 +1625,7 @@ bcmeth_txq_consume(
* If this is the last descriptor in the chain, get the
* mbuf, free its dmamap, and free the mbuf chain itself.
*/
- const uint32_t txdb_flags = consumer->txdb_flags;
+ const uint32_t txdb_flags = le32toh(consumer->txdb_flags);
if (txdb_flags & TXDB_FLAG_EF) {
struct mbuf *m;
@@ -1650,7 +1653,7 @@ bcmeth_txq_consume(
* Wrap at the last entry!
*/
if (txdb_flags & TXDB_FLAG_ET) {
- consumer->txdb_flags = TXDB_FLAG_ET;
+ consumer->txdb_flags = htole32(TXDB_FLAG_ET);
KASSERT(consumer + 1 == txq->txq_last);
consumer = txq->txq_first;
} else {
@@ -1705,7 +1708,7 @@ bcmeth_txq_reset(
/*
* Last descriptor has the wrap flag.
*/
- txdb->txdb_flags = TXDB_FLAG_ET;
+ txdb->txdb_flags = htole32(TXDB_FLAG_ET);
/*
* Reset the producer consumer indexes.
Index: src/sys/arch/arm/broadcom/bcm53xx_intr.h
diff -u src/sys/arch/arm/broadcom/bcm53xx_intr.h:1.1 src/sys/arch/arm/broadcom/bcm53xx_intr.h:1.2
--- src/sys/arch/arm/broadcom/bcm53xx_intr.h:1.1 Sat Sep 1 00:04:44 2012
+++ src/sys/arch/arm/broadcom/bcm53xx_intr.h Mon Oct 28 22:51:16 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm53xx_intr.h,v 1.1 2012/09/01 00:04:44 matt Exp $ */
+/* $NetBSD: bcm53xx_intr.h,v 1.2 2013/10/28 22:51:16 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -31,6 +31,10 @@
#ifndef _ARM_BROADCOM_BCM53XX_INTR_H_
#define _ARM_BROADCOM_BCM53XX_INTR_H_
+#ifdef _KERNEL_OPT
+#include "opt_broadcom.h"
+#endif
+
#define PIC_MAXSOURCES 256
#define PIC_MAXMAXSOURCES 280
@@ -81,58 +85,95 @@
#define IRQ_QSPI_S0_PINS_BUS 70
#define IRQ_A9JTAG_S0_PINS_BUS 71
#define IRQ_APBX_S0_PINS_BUS 72
-#define IRQ_DS_0_PINS_BUS 73
-#define IRQ_DS_1_PINS_BUS 74
-#define IRQ_DS_2_PINS_BUS 75
-#define IRQ_DS_3_PINS_BUS 76
-#define IRQ_DS_4_PINS_BUS 77
-#define IRQ_DDR_CONTROLLER 78
-#define IRQ_DMAC 79 /* 16 */
-#define IRQ_DMAC_ABORT 95
-#define IRQ_NAND_RD_MISS 96
-#define IRQ_NAND_BLK_ERASE_COMP 97
-#define IRQ_NAND_COPY_BACK_COMP 98
-#define IRQ_NAND_PGM_PAGE_COMP 99
-#define IRQ_NAND_RO_CTLR_READY 100
-#define IRQ_NAND_RB_B 101
-#define IRQ_NAND_ECC_MIPS_UNCORR 102
-#define IRQ_NAND_ECC_MIPS_CORR 103
-#define IRQ_SPI_FULLNESS_REACHED 104
-#define IRQ_SPI_TRUNCATED 105
-#define IRQ_SPI_IMPATIENT 106
-#define IRQ_SPI_SESSION_DONE 107
-#define IRQ_SPI_INTERRUPT_OVERREAD 108
-#define IRQ_SPI_MSPI_INTERRUPT_DONE 109
-#define IRQ_SPI_MSPI_INTERRUPT_HALT_SET_TRANSACTION_DONE 110
-#define IRQ_USB2 111
-#define IRQ_XHCI_0 112
-#define IRQ_XHCI_1 113
-#define IRQ_XHCI_2 114
-#define IRQ_XHCI_3 115
-#define IRQ_XHCI_HSE 116
-#define IRQ_CCA 117
-#define IRQ_UART2 118
-#define IRQ_RSVD119 119
-#define IRQ_I2S 120
-#define IRQ_SMBUS 121
-#define IRQ_TIMER0_1 122
-#define IRQ_TIMER0_2 123
-#define IRQ_TIMER1_1 124
-#define IRQ_TIMER1_2 125
-#define IRQ_RNG 126
-#define IRQ_SWITCH_SOC 127 /* 32 */
-#define IRQ_NETWORK_LINK_EVENT 127 /* 8 */
-#define IRQ_PHY 135
-#define IRQ_TIMESYNC 136
-#define IRQ_IMP_SLEEP_TIMER 137 /* 3 */
-#define IRQ_PCIE_INT0 159 /* 6 */
-#define IRQ_PCIE_INT1 165 /* 6 */
-#define IRQ_PCIE_INT2 171 /* 6 */
-#define IRQ_SDIO 177
-#define IRQ_FA 178
-#define IRQ_GMAC0 179
-#define IRQ_GMAC1 180
-#define IRQ_GMAC2 181
-#define IRQ_GMAC3 182
+
+#ifdef BCM5301X
+#define BCM53XXX_IRQ(a,c) ((a))
+#elif defined(BCM563XX)
+#define BCM53XXX_IRQ(a,c) ((a) + (c))
+#else
+#error unknown iProc variant
+#endif
+
+#define IRQ_DS_0_PINS_BUS BCM53XXX_IRQ(73, 6)
+#define IRQ_DS_1_PINS_BUS BCM53XXX_IRQ(74, 6)
+#define IRQ_DS_2_PINS_BUS BCM53XXX_IRQ(75, 6)
+#define IRQ_DS_3_PINS_BUS BCM53XXX_IRQ(76, 6)
+#define IRQ_DS_4_PINS_BUS BCM53XXX_IRQ(77, 6)
+#define IRQ_DDR_CONTROLLER BCM53XXX_IRQ(78, 6)
+#define IRQ_DMAC BCM53XXX_IRQ(79, 6) /* 16 */
+#define IRQ_DMAC_ABORT BCM53XXX_IRQ(95, 6)
+#define IRQ_NAND_RD_MISS BCM53XXX_IRQ(96, 6)
+#define IRQ_NAND_BLK_ERASE_COMP BCM53XXX_IRQ(97, 6)
+#define IRQ_NAND_COPY_BACK_COMP BCM53XXX_IRQ(98, 6)
+#define IRQ_NAND_PGM_PAGE_COMP BCM53XXX_IRQ(99, 6)
+#define IRQ_NAND_RO_CTLR_READY BCM53XXX_IRQ(100, 6)
+#define IRQ_NAND_RB_B BCM53XXX_IRQ(101, 6)
+#define IRQ_NAND_ECC_MIPS_UNCORR BCM53XXX_IRQ(102, 6)
+#define IRQ_NAND_ECC_MIPS_CORR BCM53XXX_IRQ(103, 6)
+
+#define IRQ_SPI_FULLNESS_REACHED BCM53XXX_IRQ(104, 6)
+#define IRQ_SPI_TRUNCATED BCM53XXX_IRQ(105, 6)
+#define IRQ_SPI_IMPATIENT BCM53XXX_IRQ(106, 6)
+#define IRQ_SPI_SESSION_DONE BCM53XXX_IRQ(107, 6)
+#define IRQ_SPI_INTERRUPT_OVERREAD BCM53XXX_IRQ(108, 6)
+#define IRQ_SPI_MSPI_INTERRUPT_DONE BCM53XXX_IRQ(109, 6)
+#define IRQ_SPI_MSPI_INTERRUPT_HALT_SET_TRANSACTION_DONE \
+ BCM53XXX_IRQ(110, 6)
+#define IRQ_USB2 BCM53XXX_IRQ(111, 6)
+
+#define IRQ_CCA BCM53XXX_IRQ(117, 6)
+#define IRQ_UART2 BCM53XXX_IRQ(118, 6)
+#define IRQ_GPIO BCM53XXX_IRQ(119, 6)
+#define IRQ_I2S BCM53XXX_IRQ(120, 6)
+#define IRQ_SMBUS1 BCM53XXX_IRQ(121, 6)
+#define IRQ_TIMER0_1 BCM53XXX_IRQ(122, 7)
+#define IRQ_TIMER0_2 BCM53XXX_IRQ(123, 7)
+#define IRQ_TIMER1_1 BCM53XXX_IRQ(124, 7)
+#define IRQ_TIMER1_2 BCM53XXX_IRQ(125, 7)
+#define IRQ_RNG BCM53XXX_IRQ(126, 7)
+#define IRQ_SWITCH_SOC BCM53XXX_IRQ(127, 7) /* 32 */
+#define IRQ_NETWORK_LINK_EVENT BCM53XXX_IRQ(127, 7) /* 8 */
+#define IRQ_PHY BCM53XXX_IRQ(135, 7)
+#define IRQ_TIMESYNC BCM53XXX_IRQ(136, 7)
+#define IRQ_IMP_SLEEP_TIMER BCM53XXX_IRQ(137, 7) /* 3 */
+#define IRQ_PCIE_INT0 BCM53XXX_IRQ(159, 55) /* 6 */
+#define IRQ_PCIE_INT1 BCM53XXX_IRQ(165, 55) /* 6 */
+#define IRQ_PCIE_INT2 BCM53XXX_IRQ(171, 55) /* 6 */
+#define IRQ_SDIO BCM53XXX_IRQ(177, 55)
+#define IRQ_GMAC0 BCM53XXX_IRQ(179, 55)
+#define IRQ_GMAC1 BCM53XXX_IRQ(180, 55)
+
+#ifdef BCM5301X
+#define IRQ_XHCI_0 (112)
+#define IRQ_XHCI_1 (113)
+#define IRQ_XHCI_2 (114)
+#define IRQ_XHCI_3 (115)
+#define IRQ_XHCI_HSE (116)
+#define IRQ_FA (178)
+#define IRQ_GMAC2 (181)
+#define IRQ_GMAC3 (182)
+#endif
+
+#ifdef BCM563XX
+#define IRQ_SATA_PINS_BUS (73)
+#define IRQ_SRAM_PINS_BUS (74)
+#define IRQ_APBW_PINS_BUS (75)
+#define IRQ_APBX_PINS_BUS (76)
+#define IRQ_APBY_PINS_BUS (77)
+#define IRQ_APBZ_PINS_BUS (78)
+#define IRQ_SMBUS2 (128)
+#define IRQ_SATA0 (190)
+#define IRQ_SATA1 (191)
+#define IRQ_I2S_INTR (201)
+#define IRQ_MACSEC0 (202)
+#define IRQ_MACSEC1 (203)
+#define IRQ_USB2D (238)
+#define IRQ_APBV_PINS_BUS (239)
+#define IRQ_SRAM_MEM_CORRECTABLE (240)
+#define IRQ_SRAM_MEM_UNCORRECTABLE (241)
+#define IRQ_SRAM_MEM_ACCESS_VIO (242)
+#define IRQ_SRAM_MEM_SBMA_MISMATCH (243)
+#define IRQ_CCB_WDT (244)
+#endif /* BCM563XX */
#endif /* _ARM_BROADCOM_BC53XX_INTR_H_ */
Index: src/sys/arch/arm/broadcom/bcm53xx_reg.h
diff -u src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.13 src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.14
--- src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.13 Fri Jan 25 22:37:59 2013
+++ src/sys/arch/arm/broadcom/bcm53xx_reg.h Mon Oct 28 22:51:16 2013
@@ -94,8 +94,6 @@
#define TIMER0_BASE 0x005000
#define TIMER1_BASE 0x006000
#define SRAB_BASE 0x007000
-#define UART2_BASE 0x008000
-#define SMBUS_BASE 0x009000
#define CRU_BASE 0x00b000
#define DMU_BASE 0x00c000
@@ -104,16 +102,38 @@
#define PCIE0_BASE 0x012000
#define PCIE1_BASE 0x013000
-#define PCIE2_BASE 0x014000
+#ifdef BCM5301X
+#define UART2_BASE 0x008000
+#define SMBUS1_BASE 0x009000
+#define PCIE2_BASE 0x014000
#define SDIO_BASE 0x020000
#define EHCI_BASE 0x021000
#define OHCI_BASE 0x022000
-
#define GMAC0_BASE 0x024000
#define GMAC1_BASE 0x025000
#define GMAC2_BASE 0x026000
#define GMAC3_BASE 0x027000
+#define NAND_BASE 0x028000
+#define QSPI_BASE 0x029000
+#define I2S_BASE 0x02A000
+#define DMAC_BASE 0x02C000
+#endif
+
+#ifdef BCM563XX
+#define UART2_BASE 0x007000
+#define SMBUS1_BASE 0x008000
+#define WDT_BASE 0x009000
+#define PKA_BASE 0x00a000
+#define SMBUS2_BASE 0x00b000
+#define DMAC_BASE 0x020000
+#define GMAC0_BASE 0x022000
+#define GMAC1_BASE 0x023000
+#define NAND_BASE 0x026000
+#define QSPI_BASE 0x027000
+#define EHCI_BASE 0x02A000
+#define OHCI_BASE 0x02B000
+#endif
#define IDM_BASE 0x100000
#define IDM_SIZE 0x100000
@@ -129,6 +149,7 @@
#define ID_BCM53011 0xcf13 // 53011
#define ID_BCM53012 0xcf14 // 53012
#define ID_BCM53013 0xcf15 // 53013
+#define ID_BCM56340 0xdc14 // 56340
#define MISC_CAPABILITY 0x004
#define CAPABILITY_JTAG_PRESENT __BIT(22)
@@ -904,4 +925,97 @@ struct gmac_rxdb {
#endif /* GMAC_PRIVATE */
+#ifdef NAND_PRIVATE
+
+#define NAND_REVISION 0x0000 // NAND Revision
+#define NAND_CMD_START 0x0004 // Nand Flash Command Start
+#define NAND_CMD_EXT_ADDR 0x0008 // Nand Flash Command Extended Address
+#define NAND_CMD_ADDR 0x000c // Nand Flash Command Address
+#define NAND_CMD_END_ADDR 0x0010 // Nand Flash Command End Address
+#define NAND_INTFC_STATUS 0x0014 // Nand Flash Interface Status
+#define NAND_CS_NAND_XOR 0x001c // Nand Flash EBI
+#define NAND_LL_OP 0x0020 // Nand Flash Low Level Operation
+#define NAND_MPLANE_BASE_EXT_ADDR 0x0024 // Nand Flash Multiplane base address
+#define NAND_MPLANE_BASE_ADDR 0x0028 // Nand Flash Multiplane base address
+#define NAND_ACC_CONTROL_CS0 0x0050 // Nand Flash Access Control
+#define NAND_CONFIG_CS0 0x0054 // Nand Flash Config
+#define NAND_TIMING_1_CS0 0x0058 // Nand Flash Timing Parameters 1
+#define NAND_TIMING_2_CS0 0x005c // Nand Flash Timing Parameters 2
+#define NAND_ACC_CONTROL_CS1 0x0060 // Nand Flash Access Control
+#define NAND_CONFIG_CS1 0x0064 // Nand Flash
+#define NAND_TIMING_1_CS1 0x0068 // Nand Flash Timing Parameters 1
+#define NAND_TIMING_2_CS1 0x006c // Nand Flash Timing Parameters 2
+#define NAND_CORR_STAT_THRESHOLD 0x00c0 // Correctable Error Reporting Threshold
+#define NAND_BLK_WR_PROTECT 0x00c8 // Block Write Protect Enable and Size for EBI_CS0b
+#define NAND_MULTIPLANE_OPCODES_1 0x00cc // Nand Flash Multiplane Customized Opcodes
+#define NAND_MULTIPLANE_OPCODES_2 0x00d0 // Nand Flash Multiplane Customized Opcodes
+#define NAND_MULTIPLANE_CTRL 0x00d4 // Nand Flash Multiplane Control
+#define NAND_UNCORR_ERROR_COUNT 0x00fc // Read Uncorrectable Event Count
+#define NAND_CORR_ERROR_COUNT 0x0100 // Read Error Count
+#define NAND_READ_ERROR_COUNT 0x0104 // Read Error Count
+#define NAND_BLOCK_LOCK_STATUS 0x0108 // Nand Flash Block Lock Status
+#define NAND_ECC_CORR_EXT_ADDR 0x010c // ECC Correctable Error Extended Address
+#define NAND_ECC_CORR_ADDR 0x0110 // ECC Correctable Error Address
+#define NAND_ECC_UNC_EXT_ADDR 0x0114 // ECC Uncorrectable Error Extended Address
+#define NAND_ECC_UNC_ADDR 0x0118 // ECC Uncorrectable Error Address
+#define NAND_FLASH_READ_EXT_ADDR 0x011c // Flash Read Data Extended Address
+#define NAND_FLASH_READ_ADDR 0x0120 // Flash Read Data Address
+#define NAND_PROGRAM_PAGE_EXT_ADDR 0x0124 // Page Program Extended Address
+#define NAND_PROGRAM_PAGE_ADDR 0x0128 // Page Program Address
+#define NAND_COPY_BACK_EXT_ADDR 0x012c // Copy Back Extended Address
+#define NAND_COPY_BACK_ADDR 0x0130 // Copy Back Address
+#define NAND_BLOCK_ERASE_EXT_ADDR 0x0134 // Block Erase Extended Address
+#define NAND_BLOCK_ERASE_ADDR 0x0138 // Block Erase Address
+#define NAND_INV_READ_EXT_ADDR 0x013c // Flash Invalid Data Extended Address
+#define NAND_INV_READ_ADDR 0x0140 // Flash Invalid Data Address
+#define NAND_INIT_STATUS 0x0144 // Initialization status
+#define NAND_ONFI_STATUS 0x0148 // ONFI Status
+#define NAND_ONFI_DEBUG_DATA 0x014c // ONFI Debug Data
+#define NAND_SEMAPHORE 0x0150 // Semaphore
+#define NAND_FLASH_DEVICE_ID 0x0194 // Nand Flash Device ID
+#define NAND_FLASH_DEVICE_ID_EXT 0x0198 // Nand Flash Extended Device ID
+#define NAND_LL_RDDATA 0x019c // Nand Flash Low Level Read Data
+
+#define NAND_SPARE_AREA_READ_OFSn(n) (0x0200+4*(n)) // Nand Flash Spare Area Read Bytes
+#define NAND_SPARE_AREA_WRITE_OFSn(n) (0x0280+4*(n)) // Nand Flash Spare Area Write Bytes 8-11
+#define NAND_FLASH_CACHEn(n) (0x0400+4*(n)) // Flash Cache Buffer Read Access
+
+#define NAND_DIRECT_READ_RD_MISS 0x0f00 // Interrupt from Nand indicating a read miss on internal memory
+#define NAND_BLOCK_ERASE_COMPLETE 0x0f04 // Interrupt from Nand indicating block erase
+#define NAND_COPY_BACK_COMPLETE 0x0f08 // Interrupt from Nand indicating Copy-Back complete.
+#define NAND_PROGRAM_PAGE_COMPLETE 0x0f0c // Interrupt from nand indicating page program is complete.
+#define NAND_RO_CTLR_READY 0x0f10 // Interrupt from nand indicating controller ready
+#define NAND_NAND_RB_B 0x0f14 // Interrupt from nand indicating status of Nand Flash ready_bus pin
+#define NAND_ECC_MIPS_UNCORR 0x0f18 // Interrupt from Nand indicating Uncorrectable error
+#define NAND_ECC_MIPS_CORR 0x0f1c // Interrupt from Nand indicating correctable error
+
+#define NAND_CMD_START_OPCODE __BITS(28,24)
+#define NAND_CMD_START_OPCODE_DEFAULT 0
+#define NAND_CMD_START_OPCODE_NULL 0
+#define NAND_CMD_START_OPCODE_PAGE_READ 1
+#define NAND_CMD_START_OPCODE_SPARE_AREA_READ 2
+#define NAND_CMD_START_OPCODE_STATUS_READ 3
+#define NAND_CMD_START_OPCODE_PROGRAM_PAGE 4
+#define NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA 5
+#define NAND_CMD_START_OPCODE_COPY_BACK 6
+#define NAND_CMD_START_OPCODE_DEVICE_ID_READ 7
+#define NAND_CMD_START_OPCODE_BLOCK_ERASE 8
+#define NAND_CMD_START_OPCODE_FLASH_RESET 9
+#define NAND_CMD_START_OPCODE_BLOCKS_LOCK 10
+#define NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN 11
+#define NAND_CMD_START_OPCODE_BLOCKS_UNLOCK 12
+#define NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS 13
+#define NAND_CMD_START_OPCODE_PARAMETER_READ 14
+#define NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL 15
+#define NAND_CMD_START_OPCODE_LOW_LEVEL_OP 16
+#define NAND_CMD_START_OPCODE_PAGE_READ_MULTI 17
+#define NAND_CMD_START_OPCODE_STATUS_READ_MULTI 18
+#define NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI 19
+#define NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI_CACHE 20
+#define NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI 21
+#define NAND_CMD_START_CSEL __BITS(18,16)
+#define NAND_CMD_EXT_ADDRESS __BITS(15,0)
+
+#endif /* NAND_PRIVATE */
+
#endif /* _ARM_BROADCOM_BCM53XX_REG_H_ */
Index: src/sys/arch/arm/broadcom/bcm53xx_var.h
diff -u src/sys/arch/arm/broadcom/bcm53xx_var.h:1.5 src/sys/arch/arm/broadcom/bcm53xx_var.h:1.6
--- src/sys/arch/arm/broadcom/bcm53xx_var.h:1.5 Tue Feb 19 02:15:18 2013
+++ src/sys/arch/arm/broadcom/bcm53xx_var.h Mon Oct 28 22:51:16 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm53xx_var.h,v 1.5 2013/02/19 02:15:18 matt Exp $ */
+/* $NetBSD: bcm53xx_var.h,v 1.6 2013/10/28 22:51:16 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -40,7 +40,7 @@ struct bcm_locators {
bus_size_t loc_size;
int loc_port;
uint8_t loc_nintrs;
- u_int loc_intrs[4];
+ u_int loc_intrs[8];
int loc_mdio;
int loc_phy;
};
@@ -95,6 +95,7 @@ struct cpu_softc {
bus_space_handle_t cpu_armcore_bsh;
struct bcm53xx_clock_info cpu_clk;
+ uint32_t cpu_chipid;
};
Added files:
Index: src/sys/arch/arm/broadcom/bcm53xx_nand.c
diff -u /dev/null src/sys/arch/arm/broadcom/bcm53xx_nand.c:1.1
--- /dev/null Mon Oct 28 22:51:16 2013
+++ src/sys/arch/arm/broadcom/bcm53xx_nand.c Mon Oct 28 22:51:16 2013
@@ -0,0 +1,92 @@
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_nand.c,v 1.1 2013/10/28 22:51:16 matt Exp $");
+
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+
+#define NAND_PRIVATE
+
+#include <arm/broadcom/bcm53xx_reg.h>
+#include <arm/broadcom/bcm53xx_var.h>
+
+#include <dev/nand/nand.h>
+#include <dev/nand/onfi.h>
+
+static int bcmnand_ccb_match(device_t, cfdata_t, void *);
+static void bcmnand_ccb_attach(device_t, device_t, void *);
+
+struct bcmnand_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ bus_dma_tag_t sc_dmat;
+};
+
+CFATTACH_DECL_NEW(bcmnand_ccb, sizeof(struct bcmnand_softc),
+ bcmnand_ccb_match, bcmnand_ccb_attach, NULL, NULL);
+
+static int
+bcmnand_ccb_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct bcmccb_attach_args * const ccbaa = aux;
+ const struct bcm_locators * const loc = &ccbaa->ccbaa_loc;
+
+ if (strcmp(cf->cf_name, loc->loc_name))
+ return 0;
+
+ KASSERT(cf->cf_loc[BCMCCBCF_PORT] == BCMCCBCF_PORT_DEFAULT);
+
+ return 1;
+}
+
+static void
+bcmnand_ccb_attach(device_t parent, device_t self, void *aux)
+{
+ struct bcmnand_softc * const sc = device_private(self);
+ struct bcmccb_attach_args * const ccbaa = aux;
+ const struct bcm_locators * const loc = &ccbaa->ccbaa_loc;
+
+ sc->sc_dev = self;
+
+ sc->sc_bst = ccbaa->ccbaa_ccb_bst;
+ sc->sc_dmat = ccbaa->ccbaa_dmat;
+ bus_space_subregion(sc->sc_bst, ccbaa->ccbaa_ccb_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+
+ aprint_naive("\n");
+ aprint_normal("\n");
+}
