Module Name: src
Committed By: kiyohara
Date: Thu Nov 21 13:33:15 UTC 2013
Modified Files:
src/sys/arch/powerpc/conf: files.ibm4xx
src/sys/arch/powerpc/ibm4xx/dev: plb.c plbvar.h
src/sys/arch/powerpc/include/ibm4xx: dcr4xx.h
Added Files:
src/sys/arch/powerpc/ibm4xx/dev: dwctwo_plb.c
Log Message:
Support Synopsys DesigneWave OTG on PowerPC 405EX.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/powerpc/conf/files.ibm4xx
cvs rdiff -u -r0 -r1.1 src/sys/arch/powerpc/ibm4xx/dev/dwctwo_plb.c
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/powerpc/ibm4xx/dev/plb.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/powerpc/ibm4xx/dev/plbvar.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/powerpc/include/ibm4xx/dcr4xx.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/conf/files.ibm4xx
diff -u src/sys/arch/powerpc/conf/files.ibm4xx:1.14 src/sys/arch/powerpc/conf/files.ibm4xx:1.15
--- src/sys/arch/powerpc/conf/files.ibm4xx:1.14 Wed Jun 22 18:06:34 2011
+++ src/sys/arch/powerpc/conf/files.ibm4xx Thu Nov 21 13:33:15 2013
@@ -1,4 +1,4 @@
-# $NetBSD: files.ibm4xx,v 1.14 2011/06/22 18:06:34 matt Exp $
+# $NetBSD: files.ibm4xx,v 1.15 2013/11/21 13:33:15 kiyohara Exp $
#
# IBM 4xx specific configuration info
@@ -12,7 +12,7 @@ file arch/powerpc/ibm4xx/pic_uic.c
file arch/powerpc/ibm4xx/board_prop.c
# Processor Local Bus
-device plb { [irq = -1] }
+device plb {[addr = -1], [irq = -1]}
attach plb at root
file arch/powerpc/ibm4xx/dev/plb.c plb
@@ -77,3 +77,7 @@ file arch/powerpc/ibm4xx/dev/gpiic_opb.c
#device exb {[addr = -1]}
#attach exb at plb
#file arch/powerpc/ibm4xx/dev/exb.c exb
+
+# On-chip USB OTG bridge (Synopsys DesigneWave OTG)
+attach dwctwo at plb with dwctwo_plb
+file arch/powerpc/ibm4xx/dev/dwctwo_plb.c dwctwo_plb
Index: src/sys/arch/powerpc/ibm4xx/dev/plb.c
diff -u src/sys/arch/powerpc/ibm4xx/dev/plb.c:1.20 src/sys/arch/powerpc/ibm4xx/dev/plb.c:1.21
--- src/sys/arch/powerpc/ibm4xx/dev/plb.c:1.20 Sat Jun 18 06:41:42 2011
+++ src/sys/arch/powerpc/ibm4xx/dev/plb.c Thu Nov 21 13:33:15 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: plb.c,v 1.20 2011/06/18 06:41:42 matt Exp $ */
+/* $NetBSD: plb.c,v 1.21 2013/11/21 13:33:15 kiyohara Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -66,7 +66,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: plb.c,v 1.20 2011/06/18 06:41:42 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: plb.c,v 1.21 2013/11/21 13:33:15 kiyohara Exp $");
#include "locators.h"
#include "emac.h"
@@ -107,7 +107,7 @@ const struct plb_dev plb_devs [] = {
{ AMCC405EX, "cpu", },
{ AMCC405EX, "ecc", },
{ AMCC405EX, "opb", },
- { AMCC405EX, "pchb", },
+ { AMCC405EX, "dwctwo", },
{ 0, NULL }
};
@@ -174,6 +174,7 @@ plb_attach(device_t parent, device_t sel
continue;
paa.plb_name = plb_devs[i].plb_name;
+ paa.plb_addr = PLBCF_ADDR_DEFAULT;
paa.plb_dmat = &ibm4xx_default_bus_dma_tag;
paa.plb_irq = PLBCF_IRQ_DEFAULT;
@@ -185,6 +186,7 @@ plb_attach(device_t parent, device_t sel
continue;
paa.plb_name = local_plb_devs->plb_name;
+ paa.plb_addr = PLBCF_ADDR_DEFAULT;
paa.plb_dmat = &ibm4xx_default_bus_dma_tag;
paa.plb_irq = PLBCF_IRQ_DEFAULT;
@@ -200,6 +202,8 @@ plb_print(void *aux, const char *pnp)
if (pnp)
aprint_normal("%s at %s", paa->plb_name, pnp);
+ if (paa->plb_addr != PLBCF_ADDR_DEFAULT)
+ aprint_normal(" address 0x%08x", paa->plb_addr);
if (paa->plb_irq != PLBCF_IRQ_DEFAULT)
aprint_normal(" irq %d", paa->plb_irq);
Index: src/sys/arch/powerpc/ibm4xx/dev/plbvar.h
diff -u src/sys/arch/powerpc/ibm4xx/dev/plbvar.h:1.6 src/sys/arch/powerpc/ibm4xx/dev/plbvar.h:1.7
--- src/sys/arch/powerpc/ibm4xx/dev/plbvar.h:1.6 Sat Jun 18 06:41:42 2011
+++ src/sys/arch/powerpc/ibm4xx/dev/plbvar.h Thu Nov 21 13:33:15 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: plbvar.h,v 1.6 2011/06/18 06:41:42 matt Exp $ */
+/* $NetBSD: plbvar.h,v 1.7 2013/11/21 13:33:15 kiyohara Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -45,5 +45,6 @@ struct plb_dev {
struct plb_attach_args {
const char *plb_name;
bus_dma_tag_t plb_dmat; /* DMA tag */
+ bus_addr_t plb_addr;
int plb_irq;
};
Index: src/sys/arch/powerpc/include/ibm4xx/dcr4xx.h
diff -u src/sys/arch/powerpc/include/ibm4xx/dcr4xx.h:1.2 src/sys/arch/powerpc/include/ibm4xx/dcr4xx.h:1.3
--- src/sys/arch/powerpc/include/ibm4xx/dcr4xx.h:1.2 Sat Nov 6 16:32:08 2010
+++ src/sys/arch/powerpc/include/ibm4xx/dcr4xx.h Thu Nov 21 13:33:15 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: dcr4xx.h,v 1.2 2010/11/06 16:32:08 uebayasi Exp $ */
+/* $NetBSD: dcr4xx.h,v 1.3 2013/11/21 13:33:15 kiyohara Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -239,6 +239,50 @@
/* Indirectly accessed Clocking Controller DCRs */
+#define DCR_SDR0_SRST0 0x0200 /* Soft Reset */
+#define SDR0_SRST0_BGO (1 << 31) /* PLB4 to OPB bridge */
+#define SDR0_SRST0_PLB4 (1 << 30) /* PLB4 arbiter */
+#define SDR0_SRST0_EBC (1 << 29) /* External bus controller */
+#define SDR0_SRST0_OPB (1 << 28) /* OPB arbiter */
+#define SDR0_SRST0_UART0 (1 << 27) /* Universal asynchronous receiver/transmitter 0 */
+#define SDR0_SRST0_UART1 (1 << 26) /* Universal asynchronous receiver/transmitter 1 */
+#define SDR0_SRST0_IIC0 (1 << 25) /* Inter integrated circuit 0 */
+#define SDR0_SRST0_BGI (1 << 24) /* OPB to PLB bridge */
+#define SDR0_SRST0_GPIO (1 << 23) /* General purpose I/O */
+#define SDR0_SRST0_GPT (1 << 22) /* General purpose timer */
+#define SDR0_SRST0_DMC (1 << 21) /* DDR1/2 SDRAM memory controller */
+#define SDR0_SRST0_RGMII (1 << 20) /* RGMII bridge */
+#define SDR0_SRST0_EMAC0 (1 << 19) /* Ethernet media access controller 0 */
+#define SDR0_SRST0_EMAC1 (1 << 18) /* Ethernet media access controller 1 */
+#define SDR0_SRST0_CPM (1 << 17) /* Clock and power management */
+#define SDR0_SRST0_EPLL (1 << 16) /* Ethernet PLL */
+#define SDR0_SRST0_UIC (1 << 15) /* UIC0, UIC1, UIC2 */
+#define SDR0_SRST0_UPRST (1 << 14) /* USB PRST */
+#define SDR0_SRST0_IIC1 (1 << 13) /* Inter integrated circuit 1 */
+#define SDR0_SRST0_SCP (1 << 12) /* Serial communications port */
+#define SDR0_SRST0_UHRST (1 << 11) /* USB HRESET (AHB) */
+#define SDR0_SRST0_DMA (1 << 10) /* Direct memory access controller */
+#define SDR0_SRST0_DMAC (1 << 9) /* DMA channel */
+#define SDR0_SRST0_MAL (1 << 8) /* Media access layer */
+#define SDR0_SRST0_EBM (1 << 7) /* External bus master */
+#define SDR0_SRST0_GPTR (1 << 6) /* General purpose timer */
+#define SDR0_SRST0_PE0 (1 << 5) /* PCI Express 0 */
+#define SDR0_SRST0_PE1 (1 << 4) /* PCI Express 1 */
+#define SDR0_SRST0_CRYP (1 << 3) /* Security */
+#define SDR0_SRST0_PKP (1 << 2) /* Public Key Accelerator and TRNG1 */
+#define SDR0_SRST0_AHB (1 << 1) /* AHB to PLB bridge */
+#define SDR0_SRST0_NDFC (1 << 0) /* NAND Flash controller */
+#define DCR_SDR0_PFC1 0x4101 /* Pin Function Control Register 1 */
+#define SDR0_PFC1_U1ME (1 << 25) /* UART1 Mode Enable */
+#define SDR0_PFC1_U0ME (1 << 19) /* UART0 Mode Enable */
+#define SDR0_PFC1_U0IM (1 << 18) /* UART0 Interface Mode */
+#define SDR0_PFC1_SIS (1 << 17) /* SPI/IIC 1 Selection */
+#define SDR0_PFC1_DMAAEN (1 << 16) /* DMA Channel A Enable */
+#define SDR0_PFC1_DMADEN (1 << 15) /* DMA Channel D Enable */
+#define SDR0_PFC1_USBEN (1 << 14) /* USB OTG Enable */
+#define SDR0_PFC1_AHBSWAP (1 << 5) /* AHB Data Swap Enable */
+#define SDR0_PFC1_USBBIGEN (1 << 4) /* USB OTG - AHB Interface Endian Mode */
+#define SDR0_PFC1_GPTFREQ(x) ((x) & 0xf) /* GPT Variable Frequency Generator */
#define DCR_SDR0_MFR 0x4300 /* Miscellaneous Function Register */
#define SDR0_MFR_ECS(n) (1 << (27 - (n))) /* Ethernet n Clock Selection */
#define SDR0_MFR_ETXFL(n) (1 << (15 - ((n) << 2))) /* Force Parity Error EMACn Tx FIFO Bits 0:63 */
Added files:
Index: src/sys/arch/powerpc/ibm4xx/dev/dwctwo_plb.c
diff -u /dev/null src/sys/arch/powerpc/ibm4xx/dev/dwctwo_plb.c:1.1
--- /dev/null Thu Nov 21 13:33:15 2013
+++ src/sys/arch/powerpc/ibm4xx/dev/dwctwo_plb.c Thu Nov 21 13:33:15 2013
@@ -0,0 +1,161 @@
+/* $NetBSD: dwctwo_plb.c,v 1.1 2013/11/21 13:33:15 kiyohara Exp $ */
+/*
+ * Copyright (c) 2013 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: dwctwo_plb.c,v 1.1 2013/11/21 13:33:15 kiyohara Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/errno.h>
+#include <sys/extent.h>
+
+#include <powerpc/ibm4xx/cpu.h>
+#include <powerpc/ibm4xx/dev/plbvar.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdivar.h>
+#include <dev/usb/usb_mem.h>
+
+#include <dwc2/dwc2.h>
+#include <dwc2/dwc2var.h>
+#include "dwc2_core.h"
+
+#include "locators.h"
+
+#define DWCTWO_SIZE 0x40000
+
+static int dwctwo_plb_match(device_t, cfdata_t, void *);
+static void dwctwo_plb_attach(device_t, device_t, void *);
+
+static void dwctwo_plb_deferred(device_t);
+
+CFATTACH_DECL_NEW(dwctwo_plb, sizeof(struct dwc2_softc),
+ dwctwo_plb_match, dwctwo_plb_attach, NULL, NULL);
+
+static struct powerpc_bus_space dwctwo_tag = {
+ _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE,
+ 0x00000000,
+ 0x00000000,
+ DWCTWO_SIZE
+};
+static char ex_storage[EXTENT_FIXED_STORAGE_SIZE(8)]
+ __attribute__((aligned(8)));
+
+static struct dwc2_core_params dwctwo_405ex_params = {
+ .otg_cap = 0, /* HNP/SRP capable */
+ .otg_ver = 0, /* 1.3 */
+ .dma_enable = 1,
+ .dma_desc_enable = 0,
+ .speed = 0, /* High Speed */
+ .enable_dynamic_fifo = 1,
+ .en_multiple_tx_fifo = 0,
+ .host_rx_fifo_size = 531, /* 531 DWORDs */
+ .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
+ .host_perio_tx_fifo_size = 256, /* 256 DWORDs */
+ .max_transfer_size = 524287,
+ .max_packet_count = 1023,
+ .host_channels = 4,
+ .phy_type = 2, /* ULPI */
+ .phy_utmi_width = 8, /* 8 bits */
+ .phy_ulpi_ddr = 0, /* Single */
+ .phy_ulpi_ext_vbus = 0,
+ .i2c_enable = 0,
+ .ulpi_fs_ls = 0,
+ .host_support_fs_ls_low_power = 0,
+ .host_ls_low_power_phy_clk = 0, /* 48 MHz */
+ .ts_dline = 0,
+ .reload_ctl = 0,
+ .ahbcfg = 0x10,
+ .uframe_sched = 1,
+};
+
+
+static int
+dwctwo_plb_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct plb_attach_args *paa = aux;
+
+ if (strcmp(paa->plb_name, match->cf_name) != 0)
+ return 0;
+
+ if (match->cf_loc[PLBCF_ADDR] == PLBCF_ADDR_DEFAULT)
+ panic("dwctwo_plb_match: wildcard addr not allowed");
+ if (match->cf_loc[PLBCF_IRQ] == PLBCF_IRQ_DEFAULT)
+ panic("dwctwo_plb_match: wildcard IRQ not allowed");
+
+ paa->plb_addr = match->cf_loc[PLBCF_ADDR];
+ paa->plb_irq = match->cf_loc[PLBCF_IRQ];
+ return 1;
+}
+
+static void
+dwctwo_plb_attach(device_t parent, device_t self, void *aux)
+{
+ struct dwc2_softc *sc = device_private(self);
+ struct plb_attach_args *paa = aux;
+ uint32_t srst0;
+
+ sc->sc_dev = self;
+ sc->sc_params = &dwctwo_405ex_params;
+
+ dwctwo_tag.pbs_base = paa->plb_addr;
+ dwctwo_tag.pbs_limit += paa->plb_addr;
+ if (bus_space_init(&dwctwo_tag, "dwctwotag", ex_storage,
+ sizeof(ex_storage)))
+ panic("dwctwo_attach: Failed to initialise opb_tag");
+ sc->sc_iot = &dwctwo_tag;
+ bus_space_map(sc->sc_iot, paa->plb_addr, DWCTWO_SIZE, 0, &sc->sc_ioh);
+ sc->sc_bus.dmatag = paa->plb_dmat;
+
+ intr_establish(paa->plb_irq, IST_LEVEL, IPL_USB, dwc2_intr, sc);
+
+ /* Enable the USB interface. */
+ mtsdr(DCR_SDR0_PFC1, mfsdr(DCR_SDR0_PFC1) | SDR0_PFC1_USBEN);
+ srst0 = mfsdr(DCR_SDR0_SRST0);
+ mtsdr(DCR_SDR0_SRST0, srst0 | SDR0_SRST0_UPRST | SDR0_SRST0_AHB);
+ delay(200 * 1000); /* XXXX */
+ mtsdr(DCR_SDR0_SRST0, srst0);
+
+ config_defer(self, dwctwo_plb_deferred);
+}
+
+static void
+dwctwo_plb_deferred(device_t self)
+{
+ struct dwc2_softc *sc = device_private(self);
+ int error;
+
+ error = dwc2_init(sc);
+ if (error != 0) {
+ aprint_error_dev(self, "couldn't initialize host, error=%d\n",
+ error);
+ return;
+ }
+ sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint);
+}
