Module Name: src
Committed By: matt
Date: Thu Mar 13 23:44:31 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_reg.h
Log Message:
More CPUCFG registers
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/allwinner/awin_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.12 src/sys/arch/arm/allwinner/awin_reg.h:1.13
--- src/sys/arch/arm/allwinner/awin_reg.h:1.12 Tue Feb 25 00:08:29 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Thu Mar 13 23:44:31 2014
@@ -622,7 +622,12 @@
#define AWIN_CPUCFG_CPU1_RST_CTRL_REG 0x0080
#define AWIN_CPUCFG_CPU1_CTRL_REG 0x0084
#define AWIN_CPUCFG_CPU1_STATUS_REG 0x0088
+#define AWIN_CPUCFG_GENCTRL_REG 0x0184
#define AWIN_CPUCFG_PRIVATE_REG 0x01A4
+#define AWIN_CPUCFG_CPU1_PWRCLAMP_REG 0x01B0
+#define AWIN_CPUCFG_CPU1_PWROFF_REG 0x01B4
+#define AWIN_CPUCFG_DBGCTRL0_REG 0x01E0
+#define AWIN_CPUCFG_DBGCTRL1_REG 0x01E4
#define AWIN_CPUCFG_CPU_RST_CTRL_CORE_RESET __BIT(1)
#define AWIN_CPUCFG_CPU_RST_CTRL_RESET __BIT(0)
@@ -633,6 +638,12 @@
#define AWIN_CPUCFG_CPU_STATUS_STANDBYWFE __BIT(1)
#define AWIN_CPUCFG_CPU_STATUS_SMP_AMP __BIT(0)
+#define AWIN_CPUCFG_GENCTRL_CPU1_L1INV __BIT(1)
+#define AWIN_CPUCFG_GENCTRL_CPU0_L1INV __BIT(0)
+
+#define AWIN_CPUCFG_DBGCTL0_CPU1_DBGPWRDUP __BIT(1)
+#define AWIN_CPUCFG_DBGCTL0_CPU0_DBGPWRDUP __BIT(1)
+
#define AWIN_PLL1_CFG_REG 0x0000
#define AWIN_PLL1_TUN_REG 0x0004
#define AWIN_PLL2_CFG_REG 0x0008
